Review. You Are Here! Precise Traps. Terminology 8/11/15. CS 61C: Great Ideas in Computer Architecture Lecture 23: Virtual Memory Part 2

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1 CS 6C: Great Ideas in Computer Architecture Lecture : Virtual Memory Part Instructor: Sagar Karandikar sagark@eecs.berkeley.edu Review Programmed I/O Polling vs. Interrupts BooNng a Computer BIOS, Bootloader, OS Boot, Init Supervisor Mode, Syscalls Base and Bounds Simple, but doesn t give us everything we want Intro to VM hfp://inst.eecs.berkeley.edu/~cs6c Parallel Requests Assigned to computer e.g., Search Katz Parallel Threads Assigned to core e.g., Lookup, Ads Soware Parallel InstrucNons > one Nme e.g., 5 pipelined instrucnons Parallel > data one Nme e.g., Add of 4 pairs of words Hardware descripnons All one Nme Programming Languages You Are Here! Harness Parallelism & Achieve High Performance Hardware arehouse Scale Computer Today s Lecture Core Memory Input/Output InstrucNon Unit(s) Main Memory Computer () Core Core FuncNonal Unit(s) A 0 +B 0 A +B A +B A +B Smart Phone Logic Gates Traps/Interrupts/ExecepNons: altering the normal flow of control program I i- HI I i I i+ HI HI n trap handler An external or internal event that needs to be processed by another (system) program. The event is usually unexpected or rare from program s point of view. 4 Terminology In CS6C (you ll see other defininons in use elsewhere): Interrupt caused by an event external to current running program (e.g. key press, mouse acnvity) Asynchronous to current program, can handle interrupt on any convenient instrucnon ExcepNon caused by some event during execunon of one instrucnon of current running program (e.g., page fault, illegal instrucnon) Synchronous, must handle excepnon on instrucnon that causes excepnon Trap acnon of servicing interrupt or excepnon by hardware jump to trap handler code Precise Traps Trap handler s view of machine state is that every instrucnon prior to the trapped one has completed, and no instrucnon amer the trap has executed. Implies that handler can return from an interrupt by restoring user registers and jumping to E Interrupt handler somware doesn t need to understand the pipeline of the machine, or what program was doing! More complex to handle trap caused by an excepnon Providing precise traps is tricky in a pipelined superscalar out- of- order processor! But handling imprecise interrupts in somware is even worse. 5 6

2 Trap Handling in 5- Stage Pipeline Mem address Exception D Decode E + M Illegal Opcode Asynchronous Interrupts Overflow Mem address Exceptions How to handle mulnple simultaneous excepnons in different pipeline stages? How and where to handle external asynchronous interrupts? Select Handler Save ExcepNons UnNl Commit Mem address Exception Kill F Stage D Decode E + M Exc D D Illegal Opcode Kill D Stage Exc E E Overflow Kill E Stage Exc M Commit Point Mem address Exceptions Cause E M Asynchronous Kill Interrupts riteback 7 8 Handling Traps in In- Order Pipeline Hold excepnon flags in pipeline unnl commit point (M stage) ExcepNons in earlier pipe stages override later excepnons for a given instruc>on Inject external interrupts at commit point (override others) Trap Pipeline Diagram time t0 t t t t4 t5 t6 t7.... (I ) 096: ADD IF ID EX MA - overflow! (I ) 00: XOR IF ID EX - - (I ) 04: SUB IF ID (I 4 ) 08: ADD IF (I 5 ) Trap Handler code IF 5 ID 5 EX 5 MA 5 B 5 If excepnon/interrupt at commit: update Cause and E registers, kill all stages, inject handler into fetch stage 9 0 Bare 5- Stage Pipeline D Decode E + M Virtual Memory Memory Controller Main Memory (DRAM) In a bare machine, the only kind of address is a physical address

3 hat do we need Virtual Memory for? Reason : Adding Disks to Hierarchy Need to devise a mechanism to connect memory and disk in the memory hierarchy hat do we need Virtual Memory for? Reason : Simplifying Memory for Apps ApplicaNons should see the straightorward memory layout we saw earlier - > User- space applicanons should think they own all of memory So we give them a virtual view of memory ~ FFFF FFFF hex stack heap stanc data code ~ hex 4 hat do we need Virtual Memory for? Reason : ProtecNon Between Processes ith a bare system, addresses issued with loads/ stores are real physical addresses This means any program can issue any address, therefore can access any part of memory, even areas which it doesn t own Ex: The OS data structures e should send all addresses through a mechanism that the OS controls, before they make it out to DRAM - a transla5on mechanism 5 Spaces The set of addresses labeling all of memory that we can access Now, kinds: Virtual Space - the set of addresses that the user program knows about Space - the set of addresses that map to actual physical cells in memory Hidden from user applicanons So, we need a way to map between these two address spaces 6 Blocks vs. Pages In caches, we dealt with individual blocks Usually ~64B on modern systems e could divide memory into a set of blocks In VM, we deal with individual pages Usually ~4 KiB on modern systems Now, we ll divide memory into a set of pages Common point of confusion: Bytes, ords, Blocks, Pages are all just different ways of looking at memory! 6 KiB Bytes, ords, Blocks, Pages 6 KiB DRAM, 4 KiB Pages (for VM), 8 B blocks (for caches), 4 B words (for lw/sw) Memory Page Can think of Page memory as: - 4 Pages OR - 8 Blocks Page OR ords Page 0 Page Block Block ord Can think of a page as: - Blocks OR - 04 ords 7 Block 0 ord 0 8

4 TranslaNon TranslaNon So, what do we want to achieve at the hardware level? Take a Virtual, that points to a spot in the Virtual Space of a parncular program, and map it to a, which points to a physical spot in DRAM of the whole machine Virtual Virtual Page Number TranslaNon Page Number Copy Bits Virtual Virtual Page Number The rest of the lecture is all about implemennng Page Number 9 0 Processor- generated address can be split into: 0 Space of Program # Paged Memory Systems Virtual Page Number 0 of Program # 0 Page tables make it possible to store the pages of a program non-contiguously. A page table contains the physical address of the base of each page Memory Prog Prog Prog Private (Virtual) Space per Program Each prog has a page table Page table contains an entry for each prog page OS pages free Memory here Should s Reside? Space required by the page tables (PT) is propornonal to the address space, number of users,... Too large to keep in registers inside CPU Idea: Keep page tables in the main memory Needs one reference to retrieve the page base address and another to access the data word doubles the number of memory references! (but we can fix this using something we already know about ) s in Memory Prog Virtual Space Prog Virtual Space PT Prog PT Prog Memory 4 4

5 Administrivia Project - due tonight Project 4 out now CompeNNon for glory + EC, awards during last lecture H6 Out VM, I/O, Parity, ECC Guerrilla SecNon on VM, I/O, ECC, on Thursday from 5-7pm, oz Sign up for tutoring on Piazza 5 Administrivia Upcoming Lecture Schedule 8/0: VM (today) 8/04: I/O: DMA, Disks, Networking 8/05: Dependability: Parity, ECC, RAID Last day of new material 8/06: Final Exam Review, Day (Formerly GPUs) 8/0: Final Exam Review, Day (Formerly tools) 8/: Summary, hat s Next? (+ HKN reviews) Project 4 CompeNNon inners Announced 8/: No Lecture, I ll have OH in this room 6 Administrivia Final Exam is next Thursday (8/) 9am- pm, 0 Evans More info soon CS6C In the News: Moore s Law s 50 th Anniversary this year! Gordon Moore s paper appeared in 9 April 965 issue of Electronics. ith unit cost falling as the number of components per circuit rises, by 975 economics may dictate squeezing as many as 65,000 components on a single silicon chip. Today: 8- core Intel Xeon Haswell- E billion transistors on a chip 7 8 Break Linear Entry (PTE) contains: bit to indicate if page exists And either or : (physical page number) for a memory- resident page (disk page number) for a page on the disk Status bits for protecnon and usage (read, write, exec) OS sets the Base Register whenever acnve user process changes PT Base Register VPN Virtual address 9 0 VPN Pages word 5

6 hat if the page isn t in DRAM? e get a page fault : IniNate transfer of the page we re requesnng from disk to DRAM, should place it into an unused page If no unused page is lem, a page currently in DRAM is selected to be replaced (based on usage) The replaced page is wrifen back to disk, page table entry that maps that VPN- > is marked as invalid Page table entry of the page we re requesnng is updated with a (now) valid Size of Linear ith - bit addresses, 4- KB pages & 4- byte PTEs: 0 PTEs, i.e, 4 MB page table per user 4 GB of swap needed to back up full virtual address space Larger pages? Internal fragmentanon (Not all memory in page is used) Larger page fault penalty (more Nme to read from disk) hat about 64- bit virtual address space??? Even MB pages would require byte PTEs (5 TB!) hat is the saving grace? Root of the Current Hierarchical Virtual p p offset 0-bit 0-bit L index L index (Processor Register) p Level page in primary memory page in secondary memory PTE of a nonexistent page 0 p Level s offset Pages Memory Two- Level s in Memory Virtual Spaces User User Level PT User Memory User/ User/ Level PT User Level PT User 4 TranslaNon & ProtecNon Kernel/User Mode Read/rite Exception? Virtual Virtual Page No. (VPN) Protection Check Translation Page No. () offset offset TranslaNon Lookaside Buffers () translation is very expensive! In a two-level page table, each reference becomes several memory accesses Solution: translations in hit Single-Cycle Translation miss Page-Table alk to refill virtual address VPN offset Every instruction and data access needs address translation and protection checks A good VM design needs to be fast (~ one cycle) and space efficient V R D tag (VPN = virtual page number) ( = physical page number) hit? physical address offset 5 6 6

7 Designs Typically - 8 entries, usually fully associanve Each entry maps a large page, hence less spanal locality across pages è more likely that two entries conflict SomeNmes larger s (56-5 entries) are 4-8 way set- associanve Larger systems somenmes have muln- level (L and L) s Random or FIFO replacement policy No process informanon in? Reach: Size of largest virtual address space that can be simultaneously mapped by Example: 64 entries, 4KB pages, one page per entry Reach =? 7 VM- related events in pipeline Inst miss? Page Fault? Protection violation? D Decode E + M miss? Page Fault? Protection violation? Handling a miss needs a hardware or somware mechanism to refill usually done in hardware now Handling a page fault (e.g., page is on disk) needs a precise trap so somware handler can easily resume amer retrieving page Handling protecnon violanon may abort process 8 Hierarchical alk: SPARC v8 Virtual Index Index Index 7 0 Context Context Table Table Register L Table Context root ptr Register L Table PTP L Table PTP PTE 0 MMU does this table walk in hardware on a miss 9 Page- Based Virtual- Memory Machine (Hardware Page- Table alk) Page Fault? Protec>on viola>on? Virtual Miss? D Decode E + M P Register Memory Controller Main Memory (DRAM) Page Fault? Protec>on viola>on? Virtual Miss? Hardware Page Table alker Assumes page tables held in untranslated physical memory 40 TranslaNon: pu]ng it all together Virtual alk Page Fault (OS loads page) miss Lookup Update Protection Check the page is memory memory denied permitted here? hit hardware hardware or software software Protection Fault SEGFAULT (to cache) 4 Modern Virtual Memory Systems Illusion of a large, private, uniform store Protection & Privacy several users, each with their private address space and one or more shared address spaces page table name space Demand Paging Provides the ability to run programs larger than the primary memory Hides differences in machine configurations The price is address translation on each memory reference OS user i Swapping Store (Disk) Primary Memory VA mapping PA 4 7

8 Clicker QuesNon Let s try to extrapolate from caches hich one is false? A. # offset bits in V.A. = log(page size) B. # offset bits in P.A. = log(page size) C. # VPN bits in V.A. = log(# of physical pages) D. # bits in P.A. = log(# of physical pages) E. A single- level page table contains a PTE for every possible VPN in the system Conclusion: VM features track historical uses Bare machine, only physical addresses One program owned ennre machine Batch- style mul5programming Several programs sharing CPU while wainng for I/O Base & bound: translanon and protecnon between programs (not virtual memory) Problem with external fragmentanon (holes in memory), needed occasional memory defragmentanon as new jobs arrived Time sharing More interacnve programs, wainng for user. Also, more jobs/second. MoNvated move to fixed- size page translanon and protecnon, no external fragmentanon (but now internal fragmentanon, wasted bytes in page) MoNvated adopnon of virtual memory to allow more jobs to share limited physical memory resources while holding working set in memory Virtual Machine Monitors Run mulnple operanng systems on one machine Idea from 970s IBM mainframes, now common on laptops e.g., run indows on top of Mac OS X Hardware support for two levels of translanon/protecnon Guest OS virtual - > Guest OS physical - > Host machine physical Also basis of Cloud CompuNng 4 Virtual machine instances on EC for Lab 44 8