SOS : Software-based Out-of-Order Scheduling for High-Performance NAND Flash-Based SSDs

Transcription

1 SOS : Software-based Out-of-Order Scheduling for High-Performance NAND Flash-Based SSDs Sangwook Shane Hahn, Sungjin Lee and Jihong Kim Computer Architecture & Embedded Systems Laboratory School of Computer Science and Engineering Seoul National University Massive Storage Systems and Technologies 2013 (MSST 2013) May 9 th, / 12

2 Introduction NAND flash memory based devices Become more popular because of their performance Consist of multiple flash chips Each chip can perform only one flash operation at a time In order to increase the performance of NAND-based devices Exploiting multichip parallelism is a key Out-of-order execution model is ideal for multichip parallelism Head rite C0 rite T out-of-order T in-order Erase Read C1 C0 Erase Tail rite C0 C2 rite Read C1 rite Erase C0 C1 rite C2 C0 Read rite rite Chip2 rite Read Performance Improvement rite rite Chip2 2 / 12 Time

3 Out-of-order Support in SSDs Hardware-based Out-of-Order Scheduling (HOS) Receive requests with only physical address information translated by a flash translation layer (FTL) Execute requests in an out-of-order manner Logical address information File System (LBA0) E (LBA1) (LBA2) R (LBA4) (LBA5) (LBA0) Both Logical & Physical address information LBA FTL Mapping table (LBA0 -> PBA0) PBA NAND flash device Physical address information HOS PBA Data buffer (PBA2) E (PBA1) (PBA0) (PBA5) R (PBA4) (PBA7) Chip2 Chip3 Flash Memor y 3 / 12

4 HOS eakness #1 : Skewed Queue Problem Data locality & different operation latencies induce the skewed queue problem (PBA2) E (PBA1) (PBA0) HOS Data buffer (PBA5) R (PBA4) (PBA7) rite Read rite Chip2 How to balance Benchmark Bonnie++ Postmark skewed queues? Financial1 Financial2 ebsearch hen at least one of chips is PBA Balance skewed queues Chip2 Chip3 29% 32% 18% 11% 9% In order to reallocate requests, idle mapping table update process is inevitable Modifying mapping table is hard to hardware-based scheduler and easy to software-based one 4 / 12 rite rite Erase T rite Performance Improvement T HOS Time

5 rite How Chip2 to prohibit Chip2 Chip3 useless writes? Benchmarks Bonnie++ Postmark Financial1 Financial2 ebsearch HOS eakness #2 : Useless rite Problem Useless rites means overwrites at the data buffer HOS can t recognize useless writes without logical address (LBA2) E (LBA1) (LBA0) HOS Data buffer (LBA5) R (LBA4) (LBA0) PBA Same LBA = Overwrite rite 11.7% 14.3% 17.6% 9.2% 7.1% In order to cancel useless writes, logical address information of requests is essential Access logical address information of request is hard to hardware-based Read scheduler and easy to software-based one 5 / 12 Erase rite Erase rite T rite Performance Improvement T HOS Time

6 Our Contributions Propose software-based out-of-order scheduling (SOS) SOS can overcome the skewed queue problem & useless write problem without additional hardware resources and high design cost SOS was implemented at a prototype SSD, BlueSSD SOS improves the average I/O response time by up to 42% over HOS 6 / 12

7 Overview of SOS Host System Host I/O Request Software Level rite Buffer Cache Flash Translation Layer Software-Based Out-of-Order Scheduling rite Hit Manager Queue Size Leveler Dynamic Scheduler Software Queues Hardware Level Low-level Flash Controller Flash Memory SOS handles requests at the software queues with logical & physical address information Queue size leveler : detect the skewed queues and then rearranges requests rite hit manager : eliminate useless writes by canceling unnecessary writes 7 / 12

8 Queue Size Leveler (QSL) Balance the size of multiple I/O queues by reallocating write requests to idle chips Consider different latencies of each flash operations Triggered when one of chips become idle (PBA2) E E (PBA1) (PBA1) (PBA0) SOS SOS Data buffer Data buffer (PBA5) R (PBA4) (PBA5) (PBA7) Chip2 Chip3 (PBA0) LBA R (PBA7) Chip2 Chip3 Idle chip triggers QSL PBA Idle chip triggers QSL T Present rite Read 8 / 12 (PBA9) LBA Chip3 Erase FTL rite rite Chip2 rite PBA Mapping table LBA2 LBA0 LBA2 LBA0 -> PBA2 PBA0 -> PBA2 PBA0 -> PBA6 PBA9 T SOS Erase rite Chip2 rite Performance Improvement T HOS Time

9 rite Hit Manager (HM) Detect overwrites and cancel them to eliminate unnecessary writes and invalidations Additional flag at mapping table implemented for detection (LBA0) LBA Detect useless writes without full search FTL PBA Flag 0 means Previous write request Mapping table still exists at data buffer LBA0:PBA0(flag=0) Overwrite occurs & it triggers HM (PBA2) E (PBA1) (PBA0) LBA SOS Data buffer (PBA5) R (PBA4) PBA Chip2 Chip3 rite Erase Erase Read 9 / 12 rite rite rite Chip2 T SOS rite Performance Improvement T HOS Time

10 Experimental Settings e implemented the SOS in SSD prototype, BlueSSD BlueSSD supports 4 buses and 4 ways (Total 16 chips) PowerPC 405 processor (@100Mhz) on BlueSSD runs Linux kernel Realize HOS by rearranging the sequence of requests according to the out-of-order scheduling algorithm The rearranged I/O traces were replayed, using the in-order scheduling algorithm 10 / 12

11 Experimental Results Characteristics of benchmarks Benchmarks Bonnie++ Postmark Financial1 Financial2 ebsearch Read Ratio 52.1% 50.0% 32.8% 82.4% 91.1% rite Ratio 47.9% 50.0% 67.2% 17.6% 8.9% SOS improves I/O response times by 15% to 42% over HOS Normalized Response Time (%) IOS HOS SOS 37% 40% Bonnie++ Postmark Financial1 Financial2 ebsearch 11 / 12 42% 23% 15%

12 Conclusion & Future ork Software-based out-of-order scheduling Exploits the multichip parallelism more effectively than hardware-based one Queue size leveler addresses skewed queue problem rite hit manager addresses useless write problem Improves I/O response times by up to 42% over HOS Future work More flexible request scheduling techniques Reflect user-priority of requests from upper layer, etc. 12 / 12

13 End of Presentation Thank you 13 / 12