MSC711x Application Development System (MSC711xADS) Reference Manual

Transcription

1 Freescale Semiconductor Reference Manual MSC711xADSRM Rev. 1, 6/2007 MSC711x Application Development System (MSC711xADS) Reference Manual MSC7110, MSC7112, MSC7113, MSC7115, MSC7116, MSC7118, MSC7119 The MSC711xADS board uses one StarCore -based 16-bit MSC711x processor, the MSC7116, along with the PowerQUICC II MPC8272 as the host processor. The MSC711xADS board serves as a platform for software and hardware development in the MSC711x environment. Developers can use on-board resources and the associated debugger to perform a variety of tasks, such as downloading and running code, setting breakpoints, displaying memory and registers, and connecting proprietary hardware via the expansion connectors. The MSC711xADS board can also function as a demonstration system, with application software programmed into its Flash memory. The board works seamlessly with an evaluation copy of CodeWarrior Development Studio. The MSC711x family is a high-performance, cost-effective family of DSPs based on the StarCore SC1400 core, which offers system solutions, flexibility with peripherals and performance, and overall system cost savings. Devices in the MSC711x family target highbandwidth highly computational DSP applications and are optimized for packet telephony applications, providing a competitive price per channel for voice over packet systems. Designed with attention to system requirements from the start, the MSC711x family delivers one core architecture for digital signal processing that spans the low to high end. This manual is an operation guide for the MSC711xADS board. It describes the board architecture and functionality and provides instructions on how to use the board. CONTENTS 1 Overview How the MSC711xADS Works Product Documentation Third-Party Documentation Hardware Configuration and Boot Board Unpacking Board Installation Board Configuration DIP-Switch and Jumper Settings MSC711xADS Boot Board Controls and Indicators Board-Level Functions Reset Clocking Power Supply Memory Map/Programming Model Memory Map Board Control and Status Registers (BCSRx) MSC711xADS Interfaces HDI16 Host Processor Interface x Bus Buffering MSC711x Connection to the MPC RS-232 Ports JTAG/OCE10 Test Access Port (TAP) DDR SDRAM Interface Ethernet Synchronous DRAM (60x Bus) Flash Memory Time-Slot Interchanger (TSI) SLIC SLAC Interface E1/T1 Framer...50 Freescale Semiconductor, Inc., 2005, All rights reserved.

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3 Overview 1 Table 1-1 lists the features, components, and specifications of the MSC711xADS board. Table 1-1. Features of the MSC711xADS Board Feature Full-Featured Development Kit Board Specifications MSC7116 Device MPC8272 Description Kit contents (see Figure 1-1): MSC711xADS board. Evaluation copy of CodeWarrior Development Studio User documentation. Power supply and cables. Operating temperature: 0 C to 70 C (room temperature). Storage temperature: 25 C to 85 C. Dimensions: One single-slot 6U PCI form factor. Relative humidity: 5% to 90% (non-condensing) +12 V external DC power supply rate for a maximum current of 1.8 A. Functionality: SC1400 DSP core. 800 MMACS at 200 MHz. 408 KB total memory. Two time-division multiplex (TDM) interfaces, 128-channels each. 10/100 Ethernet MAC. 32-channel DMA controller. AHB-Lite internal bus. DDR external memory controller interface. 16-bit enhanced host port. JTAG/OCE10 emulator test. Process/Voltage: 0.13 μ, 1.2 V core; 2.5 V 3.3 V I/O Power Consumption: 300 to 400 mw target (200 MHz). Packaging Pb-free 400 MAPBGA (17 17 mm, 0.8 mm pitch). Footprint-compatible with MSC7110, MSC7112, MSC7113, and MSC MHz bus frequency, 200 MHz CPM frequency, and 400 MHz overall frequency. Efficient, dual-core architecture that combines the PowerPC 603e ecore with a separate RISCbased communications processor module. Superior integration with features optimized for cost-sensitive designs and security-oriented networking applications. Economical, powerful integrated security engine that supports industry-standard encryption algorithms. Smooth migration path for PowerQUICC and PowerQUICC II processor-based designs. Strong third-party tools support through the Freescale Smart Networks Alliance Program members. Freescale Semiconductor 3

4 Overview Table 1-1. Features of the MSC711xADS Board (Continued) Feature MSC711xADS Description MPC8272 is the MSC711x host. The MPC8272 system bus connects to the MSC711x HDI. Host/Slave connection through the 16-bit HDI16 port; the HDI16 interface is accessible via a PCI backplane multiplexed with PCI signals. 32-bit PCI host compatible. Host debug through a single JTAG connector supports both the MPC8272 and MSC711x processors. Debugging via either one JTAG chain (MPC8272 and MSC711x device together) or two independent JTAG connections (MPC8272 separate from the MSC711x device) through the COP/JTAG connection or the parallel port command converter. Flash memory for stand-alone applications. Memory: 8 MB Flash memory for the MPC8272 (16 bits wide). 64 MB SDR SDRAM for the MPC8272 (64 bits wide). 32 MB DDR SDRAM for the MSC711x device (32 bits wide). Communications ports/external connections (see Figure 1-2): 10/100Base-T Ethernet port (MII/RMII) using Davicom DM9161 connected to the MSC711x device. 10/100Base-T Ethernet port using Davicom DM9161 connected to the MPC8272 device. T1/E1 TDM interface using PMC-Sierra PM4351 connected to the TSI. Two PSTN connections using Legerity Le78D110VC/Le77D11xVC (SLIC/SLAC) connected to the TSI. H.110. RS-232 universal asynchronous receiver/transmitter (UART) port (9-pin D-connector attached to the MPC8272). RS-232 port (pins) connected to a UART that is connected to the MSC711x device. OCE10/JTAG connector for the MSC711x device. Parallel port that includes a JTAG command converter connected to the MP8272 device. COP/JTAG connector for the MPC8272. High-density (MICTOR) logic analyzer connectors to monitor MSC711x signals 6U PCI form factor. MSC711x devices boot through the HDI16 host port or the I 2 C port. After reset, selectable Debug Enable/Disable and Debug Request options. Board identification and board status read via the Board Control and Status Registers (BCSRx). Variant board configurations available via the dual-in-line package (DIP) switch setting. Push buttons for both the host and slave: Power-on reset. Soft reset. Hard reset. Abort. Time-slot interchanger (TSI) device connected to the TDM channels on the MSC711x processor; used as the H110 framer and TDM master. SLIC-SLAC interface enables use of 6-line communication board with Voice-over-Broadband SLIC/SLAC chip set. LEDs indicate power supply, peripheral enables, and software signals. 4 Freescale Semiconductor

5 Figure 1-1. Full-Featured MSC711x Development Kit Fast Ethernet to MSC711x PSTN Ports E1/T1 RS-232 (MSC711x) JTAG/OCE10 alignment indicators Parallel Port MSC711x Device HDI cpci (Backplane) Connections RS-232 (MPC8272) Fast Ethernet to MPC8272 Power On/Off Voltage Input Fuse JTAG/COP MPC8272 device Figure 1-2. MSC711xADS External Connections Freescale Semiconductor 5

6 Overview 1.1 How the MSC711xADS Works The MSC711xADS allows the application engineer to upload software to both the MSC7116 and MPC8272 devices and run that software with emulated debugging devices (JTAG or a PC). The software application can run in a bare bones operation with only the MSC7116 and MPC8272 processors or with various input or output data streams, such as from the E1/T1 connection, the Ethernet connections, or the PSTN connections. You can analyze the results with the CodeWarrior debugger or directly analyze the input or output data stream via other methods. Parallel OCE10 9-Pin COP EPP-to-JTAG 9-Pin RJ45 RS /100 PHY SCC FCC D A COP MPC8272 SDRAM (64 MB) PCI 60x Bus A Mictor D 16/8 Bit I 2 C EEPROM OCE10 UART MSC7116 HDI16 2 TDM 512 TS Switch A D DDR 32 TDM Mictor MAC 10/100 PHY T1/E1 Framer RS-232 DDR DDR 16 MB 16 Bits RJ45 RJ45 B 16 Bit 8 Bit BCSR 8 Bit 16 Bit XB 16 Bit 60x Bus H.110 SLICK SLACK RJ11 Flash Memory J1 J2 J4 Expansion Header Figure 1-3. MSC711xADS Block Diagram 1.2 Product Documentation Table 1-2 lists the documentation that supports the MSC711xADS. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office, or a Freescale Literature Distribution Center. For documentation updates, visit the Freescale DSP web site. Table 1-2. MSC711xADS Documentation Name Description Order Number MSC711xADS Reference Manual MSC711x Technical Data Detailed functional description of the MSC711xADS board, including memory and peripheral configuration, switch settings, operation, connections, and programming. MSC711x features list and physical, electrical, timing, and package specifications MSC711xADSRM MSC711x 6 Freescale Semiconductor

7 Third-Party Documentation Table 1-2. MSC711xADS Documentation (Continued) Name Description Order Number MSC711x Reference Manual MPC8272 PowerQUICC II Family Reference Manual MPC8272 PowerQUICC II Family Hardware Specifications SC1000 Family Processor Core Reference Manual OCE10 On-Chip Emulator Reference Manual Application Notes Detailed functional description of the MSC711x memory and peripheral configuration, operation, and register programming Describes the functional operation of the MPC82272 with an emphasis on peripheral functions. Details on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC8272 family of devices. Detailed description of the SC1000 family processor cores, including the SC1400, and instruction set Information on the architecture and programming model of the OCE10 on-chip emulator, which is the StarCore implementation of the EOnCE. The OCE10 on-chip emulator is a peripheral that facilitates debugging the StarCore SC1000-family processor core and peripherals. Documents describing specific applications or optimized device operation including code examples. Application notes of particular interest to developers working with the MSC711x board are as follows: AN2780, Getting Started With the MSC711x Application Development System (MSC711xADS). AN2786, MSC711x Design Checklist. AN2946, MSC711x Time-Division Multiplexing (TDM) Usage Examples (with accompanying software). AN2945, Booting an MSC711x Device from an MPC8272 Host Using the HDI16 Interface. AN2893, MSC711x Memory Controller Usage Guidelines: Supporting Double Data Rate (DDR) SDRAM Devices. AN2888, Glueless Packet Transport from PowerQUICC Network Processors to MSC711x DSP Devices. AN2715, Porting Code from the DSP56300 Family of Products to the SC140/SC1400 Core. MSC711xRM MPC8272RM MPC8272EC Refer to the MSC711x product pages on the Freescale Semiconductor web site. 1.3 Third-Party Documentation PMC-SIERRA PM4351 data sheet Infineon PEF20451 data sheet Davicom DM9161 data sheet Legerity SLIC/SLAC (Le78D110VC and Le77D11xVC) data sheet Freescale Semiconductor 7

8 Overview 8 Freescale Semiconductor

9 Board Unpacking Hardware Configuration and Boot 2 This chapter provides unpacking, installation, and hardware preparation instructions for the MSC711xADS. It also describes the boot procedure and familiarizes you with the board controls and indicators for use during board operation. 2.1 Board Unpacking The procedure for unpacking the MSC711xADS board is as follows: 1. Unpack the equipment from the shipping carton. If the shipping carton is damaged upon receipt, request that the carrier agent be present during unpacking and inspection of equipment. 2. Refer to the packing list and verify that all items are present. 3. Save the packing material for storing and reshipping equipment. CAUTION: Avoid touching areas of the integrated circuitry; static discharge can damage circuits. 2.2 Board Installation To install the MSC711xADS, perform the following steps: 1. Determine whether the MSC711xADS is to be accessed via a JTAG interface or a PC. a. For JTAG, connect the JTAG device to the JTAG/COP header connector (P14). b. For a PC, install the CodeWarrior test software or any other compatible debugging software on the PC. The MSC711xADS is optimized for CodeWarrior test software. 2. Determine whether board operation is to be host-controlled or stand-alone. Make the connections and configurations accordingly, as described in Section 2.3 on page If the board is to be inserted into a cpci rack, configure the JP7 jumper accordingly (see Section on page 17). 4. Prepare the equipment for testing.for example, if checking telecom, prepare the phone lines for the lab, and so on. 5. Configure the MSC711xADS switches and jumpers as described in Section 2.4 on page 10. The switches and jumpers that must be configured before you can proceed to step 6 are as follows: RP1 (Core voltage, see Section on page 12). SW6 (JTAG chain options, see Section on page 13). SW7 (I2C EEPROM configuration options, see Section on page 14). JP1 (Ethernet PHY MII/RMII mode, see Section on page 15). Initialize the SDRAM (see Section on page 47). 6. Insert the MSC7116 DSP device into the indicated socket (see Figure 1-2 on page 5). Ensure that the alignment indicator (a dot) on the device is next to the alignment indicator (a section of metal) on the chip socket. Freescale Semiconductor 9

10 Hardware Configuration and Boot 7. Establish the appropriate external connections (for a list of external connections and their locations, see Figure 1-2 on page 5). 8. Turn on the MSC711xADS voltage (SW9, as shown in Figure 1-2 on page 5). Note that ON is up and OFF is down. We recommend that you turn off the voltage if the MSC711xADS is unused for more than 48 hours. 2.3 Board Configuration The MSC711xADS can be installed for either host-controlled or stand-alone operation. In host-controlled operation, the MPC8272 and the MSC711x processors are both controlled by a host computer and are connected via a separate JTAG chain or a shared JTAG chain. Use the SW6 switch to configure the MSC711xADS JTAG options (see Section 2.4.4): Separate chain. The MPC8272 and the MSC711x processors each independently connects to a JTAG command converter. The MPC8272 connects via the JTAG/COP connector (P14) to a JTAG command converter or through the parallel port connector (P11) to a PC and does not use an external JTAG command converter. The MSC711x can directly connect through the JTAG/OCE10 connector (P8) via a JTAG command converter. Shared chain. Both the MPC8272 and MSC7116 processors share the same JTAG chain. The MPC8272 is the first device in the chain, so either the JTAG command converter connects to it via the JTAG/COP connector (P14) or it connects to a PC through the parallel port connector (P11) with no use of an external JTAG command converter. The debugging tool must support the shared JTAG chain option, as CodeWarrior does. In stand-alone operation, the host computer controls the MSC711xADS board not through the JTAG port but through one of its other ports, such as the RS-232 port or the fast Ethernet port. The application program must be programmed into the board Flash memory for the MPC8272 and into the board I 2 C EEPROM for the MSC DIP-Switch and Jumper Settings To select the desired configuration and ensure proper operation of the MSC711xADS board, you may have to change the DIP-Switch settings before installation. The location of the switches, indicators, DIP-Switches, and connectors is illustrated in Figure 2-1. The board has been factory tested and is shipped with DIP-Switch settings as described in the following paragraphs. Values can be changed for the following parameters: MSC711x internal voltage supply level via potentiometer (RP1). See Section on page 12. MSC711x power-up configuration (SW4). See Section on page 12. MSC711x event pin configuration (SW5). See Section on page 12. JTAG options (SW6). See Section on page 13. Select I 2 C EEPROM address and protection mode (SW7). See Section on page 14. MPC8272 clock mode settings (SW8). See Section on page 15. Main power switch (SW9). See Section on page 15. MSC711x Ethernet PHY MII/RMII mode (JP1). See Section on page 15. H110 back plane reset (JP2). See Section on page 16. TDM master selection (JP3). See Section on page 16. MSC711x clock-in source (JP4). Section on page 16. MPC8272 Hard Reset Configuration Word source (JP5). Section on page Freescale Semiconductor

11 DIP-Switch and Jumper Settings MPC8272 Hard Reset to MSC711x Hard Reset (JP6). See Section on page 17. PCI expansion enable/disable (JP7). See Section on page 17. Host (MPC8272) enable/disable (JP8). See Section on page 18. LD14 - LD15 P1 SW1 SW2 SW3 LD1 - LD13 P2 JP1 LD16 - LD19 P3 P5 J5 P6 P4 JP2 J4 JP3 P8 P10 P11 P12 SW4 SW5 P13 P15 P16 JP5 SW7 JP6 LD25-26 P17 P14 SW6 P18 J2 P20 P19 P21 LD27-28 SW8 J1 SW9 P22 P23 JP7 JP8 SW10 SW11 SW12 P24 Figure 2-1. MSC711xADS Switch and Jumper Locations Freescale Semiconductor 11

12 Hardware Configuration and Boot Internal Voltage Supply Level (RP1) The level of internal (core) voltage is tuned via RP1 and is in the range of V. You can measure voltage across JS5 with a digital voltmeter (DVM) or any other high input impedance voltage measurement device. Core voltage should be measured and tuned before the MSC711x processor is inserted into its socket MSC711x Power-Up Settings (SW4) The SW4 switches control the configuration for the MSC711x device. These switches are controlled through Board Control Status Register 2 (BCSR2) (see Chapter 4, Memory Map/Programming Model, on page 29). When a switch is in the ON position, its related signal is deasserted to 0. When the switch is in the OFF position, its related signal is asserted to 1. Table 2-1. SW4 Switch Settings Switch BSCR2 Bit OFF ON 1 DBREQ SWTE BM BM ON Figure 2-2. SW4 Factory Default Setting MSC711x Event Pin Configuration (SW5) The SW5 switches control the configuration of the MSC711x device and the EVNT[0 4] pins. When a switch is in the ON position, its related signal is deasserted to 0. When the switch is in the OFF position, its related signal is asserted to 1. Switches 1 5 control the EVNT[0 4] pin status. Switch 6 controls the JTAG mode. For normal operation it must be set to emulator (OCE10) mode. Switch 7 controls the polarity of the HDI control signals. The state of this switch is sampled only at power-on reset. Switch 8 controls the width of the HDI bus. It must remain in 16-bit mode because the host does not support an 8-bit bus. 12 Freescale Semiconductor

13 DIP-Switch and Jumper Settings Table 2-2. SW5 Switch Settings Switch JTAG Chain Options OFF ON 1 EVENT EVENT EVENT EVENT EVENT TPSEL (JTAG mode) Emulator (OCE10) Scan 7 HDI signal polarity Active high Active low 8 HDI 8-bit bus width 8 bits 16 bits ON Figure 2-3. SW5 Factory Settings JTAG Options (SW6) Switch SW6 determines the JTAG chain options. When a switch is in the ON position, its related signal is deasserted to 0. When the switch is in the OFF position, its related signal is asserted to 1. The combination of switches 1 and 2 determines the type of JTAG connection, as shown in Table 2-3 and Table 2-4. Switch 3 controls whether the parallel port connection is forced. In normal operation, the hardware automatically identifies the connection of the parallel port. On some computers, this may not happen so this switch forces the connection to the parallel port. Switch 4 selects the connection to the I 2 C EEPROM. When it is in the ON position, the I 2 C EEPROM is connected to the parallel port and can be programmed directly from the PC parallel port. Freescale Semiconductor 13

14 Hardware Configuration and Boot Table 2-3. SW6 Settings Switch Type of Connection OFF ON 1 Chain select Chain select Force parallel port Auto detection Force connection 4 I 2 C EEPROM connection MSC711x Parallel port Table 2-4. Chain Select Encoding JTAG Chain Options Chain Select 2 Chain Select 1 Separate OCE10 and COP 0 0 MPC8272 and MSC711x in one chain 0 1 Host mode JTAG chain not supported 1 1 Slave mode JTAG chain not supported ON Figure 2-4. SW6 Factory Default Settings I 2 C EEPROM Configuration (SW7) Switch SW7 determines the I 2 C EEPROM configuration options. When a switch is in the ON position, its related signal is deasserted to 0. When the switch is in the OFF position, its related signal is asserted to 1. The default factory settings for the MSC711xADS board are 1 4 = ON. Switches 1 3 set the EEPROM I 2 C bus address. Switch 4 sets the write protection mode for the EEPROM. Table 2-5. SW7 I 2 C EEPROM Settings Switch EEPROM Configuration OFF ON 1 EEPROM address EEPROM address EEPROM address Write protection Enabled Disabled 14 Freescale Semiconductor

15 2.4.6 MPC8272 Clock Mode Settings (SW8) DIP-Switch and Jumper Settings Switch SW8 determines the clock settings for the MPC8272 processor. When a switch is in the ON position, its related signal is deasserted to 0. When the switch is in the OFF position, its related signal is asserted to 1. For details, refer to the MPC8272 PowerQUICC II Family Reference Manual. The default factory settings for the MSC711xADS board are switches 1, 4, 6 = OFF and all other switches are ON. Switches 1 3 set MODCK[1 3], respectively. Switches 4 7 set MODCKH[0 3], respectively. Switch 8 sets the PCIMODCK bit. Table 2-6. SW8 MPC8272 Clock Configuration Switch SW8 OFF ON 1 MODCK MODCK MODCK MODCKH MODCKH MODCKH MODCKH PCIMODCK Main Power Switch (SW9) Switch 9 is the main power ON OFF switch. Toggling the switch turns the main power ON (down) or OFF (up) MSC711x Ethernet PHY MII/RMII Mode (JP1) JP1 selects the connection mode of the Ethernet PHY connected to the MSC711x. The mode must be selected before power is turned on. In the MII (1-2) position, the PHY is in MII mode (factory default). In the RMII (2-3) position, the PHY is in RMII mode. JP MII Mode RMII Mode Factory Default Figure 2-5. JP1, MII Versus RMII Mode Freescale Semiconductor 15

16 Hardware Configuration and Boot H.110 Back Plane Reset (JP2) JP2 selects the connection of the MSC711x hard reset to the H.110 back plane. When placed, the MSC711x hard reset is connected to the H.110 back plane reset. When not placed, the MSC711x hard reset is disconnected from the H.110 back plane reset. JP Hard Reset Connected to Back Plane Factory Default Hard Reset Disconnected from Back Plane Figure 2-6. JP2, Hard Rest Back Plane TDM Master Selection (JP3) JP3 selects the master (clock and frame source) of the TDM channels of the MSC711x. In the TSI (1-2) position, the TSI is the TDM master (factory default). In the external (2-3) position, the TSI frame and clock signals are disconnected from the MSC711x. The MSC711x can be the TDM master or an external master (clock and frame sources) can be connected through the J5 edge connector. JP TSI External Factory Default Figure 2-7. JP3, TSI TDM Master MSC711x Clock In Source (JP4) JP4 selects the source for the clock-in input of the MSC711x. In the external (1-2) position, the clock-in source is the SMB connector (P9) and the external clock generator must be used. In the oscillator (2-3) position, the clock-in source is the on-board oscillator (S2). JP External Oscillator Factory Default Figure 2-8. JP4, Clock Input setting Note: For the mode change to occur, JP4 should be set while the board is powered OFF. 16 Freescale Semiconductor

17 DIP-Switch and Jumper Settings MPC8272 Hard Reset Configuration Word Source (JP5) JP5 selects the source for the Hard Reset Configuration Word (HRCW) of the MPC8272 processor. In the Flash (1-2) position, the HRCW is sourced from the Flash memory. In the BCSR (2-3) position, the HRCW is sourced from the BCSR. JP Flash Factory Default BSCR Figure 2-9. JP5, HRCW Setting MPC8272 Hard Reset to MSC711x Hard Reset (JP6) JP6 selects the connection of the MPC8272 hard reset to the MSC711x hard reset. When the two hard resets are connected and an MPC8272 hard reset is generated, an MSC711x hard reset is also generated. The hard reset generation works in only one direction. An MSC711x hard reset does not generate a hard reset to the MPC8272 processor. When the hard resets are disconnected, the MPC8272 and the MSC711x processors have separate hard reset signals that do not affect each other. In the normal (1-2) position, the MPC8272 hard reset is connected to the MSC711x hard reset. In the test (2-3) position, the MPC8272 hard reset is disconnected from the MSC711x hard reset (factory default) JP Host and Slave Hard Resets Host and Slave Hard Resets Connected to Each Other Not Connected to Each Other Factory Default Figure JP6, Hard Resets PCI Expansion Enable/Disable (JP7) JP7 switches between the PCI host bus and the MPC x bus (and HDI) visibility on the J1 and J2 edge connectors. In the enable (1-2) position, the MPC8272 PCI host bus is visible on the J1 and J2 edge connectors, thus enabling the insertion of the board into a cpci rack. In the disable (2-3) position, the MPC x (and HDI) bus is visible on J1 and J2 edge connectors. Freescale Semiconductor 17

18 Hardware Configuration and Boot JP Enable Figure Disable Factory Default JP7, PCI Enable/Disable Host (MPC8272) Enable/Disable (JP8) JP8 enables and disables the host (MPC8272). When enabled, the MPC8272 is connected to the MSC711x. When disabled, the MSC711x operates in stand-alone mode, regardless of the MPC8272 state. In the enable (1-2) position, the MPC8272 is enabled and connected to the MSC711x. In the disabled (2-3) position, the state of the MPC8272 does not influence the MSC711x, which therefore works independently in stand-alone mode. Note: The Disable mode is not yet supported. As a work around, disconnecting the MPC8272 HRESET signal from the MSC711x HRESET signal yields the same results. That is, the MSC711x work independently of the MPC8272 state. JP Enable Factory Default Figure Disable JP8, Host Enable 2.5 MSC711xADS Boot MSC711x devices can boot from the HDI16 bus or from an external EEPROM with a serial I 2 C interface. The MSC711xADS uses a serial EEPROM with a 256 Kb capacity (for example, M24256-B from Tmicroelectronics Co. 1 ). The EEPROM memory is organized as eight 32 KB rows. This device can perform a hardware-based writeprotect of its memory map, and it is equipped with a socket so that it can be reprogrammed by an external programmer. A PLD provides an optional connection to the host PC, which allows the user to reprogram the onboard boot EEPROM. At reset, the address of the I 2 C EEPROM is set to 000. The external pins of the I 2 C EEPROM are described in Figure 2-13 and Table 2-7. The state of the SCL and SDA lines is indicated by red and green LEDs. 1. Other devices that can be used are Microchip 24LC256, ATMEL AT24C256, or CATALYST CAT24WC Freescale Semiconductor

19 . MSC711xADS Boot V CC E[0 2] SCL 3 SDA WC V SS Figure I 2 C EEPROM Pins Table 2-7. Pin I 2 C EEPROM Pins Description E0, E1, E2 Chip enable SDA SCL WC V CC V SS Serial data Serial clock Write control Supply voltage Ground The I 2 C EEPROM is compatible with the I 2 C memory protocol, which defines a two-wire serial interface with a bidirectional data bus and serial clock. The memory carries a 4-bit unique device type identifier code (0b1010) in accordance with the I 2 C bus definition. The I 2 C bus is connected to a header with two test points, and its clock runs at 400 KHz. The I 2 C EEPROM behaves as a slave device according to the I 2 C protocol, with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition, which is generated by the bus master. The START condition is followed by a device select code and RW bit (see Figure 2-14). It is terminated by an acknowledge bit that is inserted by the memory immediately after the 8-bit transmission of the bus master, thus comprising a 9 th bit. When the bus master reads the data, it acknowledges the receipt of the data byte by placing an acknowledge 9 th bit into the transmission stream. Data transfers are terminated by a STOP condition after an Ack for WRITE, and after a No Ack for READ. Device Type Identifier Chip Enable RW Device Select Code RW Note: The most significant bit, 7, is sent first. Figure Device Select Code Freescale Semiconductor 19

20 Hardware Configuration and Boot 2.6 Board Controls and Indicators This section acquaints you with operational features of the MSC711xADS Abort and Reset Control Table 2-8 describes the MSC711xADS abort and reset features. Table 2-8. Abort and Reset Push Button Switches Switch Name Description SW1 MSC711x abort (NMI) Aborts program execution by issuing a level 0 interrupt to the MSC711x. The ABORT switch signal is debounced SW2 MSC711x hard resetã Generates a hard reset to the MSC711x but does not affect the host. The hard reset signal is debounced. SW3 Power-on reset Performs a power-on reset to the MPC8272 and to the MSC711x; all configuration and all data residing in volatile memories are lost. SW10 MPC8272 soft reset Generates a soft reset to the MPC8272. The soft reset switch signal is debounced. SW11 MPC8272 hard reset Generates a hard reset to the MPC8272. A hard reset to the MPC8272 also generates a hard reset to the MSC711x if JP6 is configured accordingly (see Section , MPC8272 Hard Reset to MSC711x Hard Reset (JP6), on page 17). The HRESET switch signal is debounced. SW12 MPC8272 abort (NMI)Ã Aborts program execution by issuing a level 0 interrupt to the MPC8272. The ABORT switch signal is debounced MSC711xADS Voltage Measurement Table 2-9 describes MSC711xADS voltage measurement. CAUTION: The job of removing JS5, JS8, and JS6 and soldering the current meter connections instead is very delicate and should be done by a skilled technician. If this process is done by unskilled hands or repeated more than 3 times, permanent damage may occur to the MSC711xADS. Name Table 2-9. MSC711xADS Voltage Measurement Description JS5 Core voltage measurement JS5 resides in MSC711x main core current flow. To measure core current, JS5 should be removed with a solder tool and a current meter should be connected instead with wires as short and thick as possible. JS8 JS6 MSC711x I/O voltage measurement MSC711x PLL voltage measurement JS8 resides in the MSC711x main I/O current flow. To measure I/O current, JS8 should be removed with a solder tool, and a current meter should be connected, with wires as short and thick as possible. JS6 resides in MSC711x main PLL current flow. To measure PLL current, JS6 should be removed with a solder tool, and a current meter should be connected instead, with wires as short and thick as possible. 20 Freescale Semiconductor

21 2.6.3 GND Bridges Board Controls and Indicators There are seven GND bridges on the MSC711xADS. These bridges assist you in taking general measurements and establishing logic-analyzer connections. CAUTION: Shortening power connection to ground may result in permanent damage to the MSC711xADS hardware. To prevent this condition, always use insulated ground clips to connect to a ground bridge LED Indicators Table 2-10 lists the MSC711xADS LED indicators. Table LED Indicators LED Indication Description LD11 12 V Green. Indicates whether the +12 V power supply is on. LD10 5 V Green. Indicates whether the +5 V power supply is on. LD V Green. Indicates whether the +3.3 V power supply is on. LD9 2.5 V Green. Indicates whether the +2.5 V power supply is on. LD V Green. Indicates whether the +1.5 V power supply is on. LD V Green. Presence of the +1.2 V power supply is on. LD18 RUN Green. The MPC8272 is performing cycles on the PowerPC bus. When this LED is dark, the MPC8272 is either running internally or stuck. LD19 LD1 LD2 LD3 LD28 LD27 LD14 LD15 MPC8272 fast Ethernet port enabled MSC711x fast Ethernet port enabled MPC8272 RS-232 port ON MSC711x RS232 Port ON MPC8272 fast Ethernet port full duplex MPC8272 fast Ethernet port 100Base-Tx MSC711x fast Ethernet port full duplex MSC711x fast Ethernet port 100Base-Tx Yellow. The fast Ethernet port PHY, the DM9161, is connected to FCC2. When this LED is not lit, the DM9161 is in power-down mode and is disconnected from FCC2. BCSR0 (see Chapter 4, Memory Map/Programming Model, on page 29) controls the state of LD19. Yellow. The fast Ethernet port PHY, the DM9161, is connected to the MSC711x. When this LED is not lit, the DM9161 is in power-down mode and is disconnected from the MSC711x, enabling the use of its associated MII pins for other functions. BCSR2 (see Chapter 4, Memory Map/Programming Model, on page 29) controls the state of LD1. Yellow. The RS-232 transceiver connected to P16 is active and communicating. When this LED is not lit, the transceiver is in shut-down mode. Yellow. The RS-232 transceiver connected to P7 is active and communicating. When this LED is not lit, the transceiver is in shut-down mode. Red. Indicates whether the DM9161 on the MPC8272 processor is enabled and is operating in full-duplex mode. Green. Indicates whether the DM9161 on the MPC8272 processor is enabled and is operating in 100 Mbps mode. Red. Indicates whether the DM9161 on the MSC711x processor is enabled and is operating in Full Duplex operation mode. Green. Indicates whether the DM9161 on the MSC711x processor is enabled and is operating in 100 Mbps mode. LD4 General-purpose LED 2 Red. A general-purpose LED that the user controls via BCSR0. LD5 General-purpose LED 1 Green. A general-purpose LED that the user controls via BCSR0. Freescale Semiconductor 21

22 Hardware Configuration and Boot Table LED Indicators (Continued) LED Indication Description LD6 MSC711x MII/TDM2 enable Green. Indicates whether the MSC711x MII/TDM port is connected to the TDM device/ethernet PHY. LD7 MSC711x MII enable Green. The MSC711x MII/TDM2 port is connected to the Ethernet PHY in MII mode. LD8 MSC711x TDM2 enable Green. The MSC711x MII/TDM2 port is connected to the TSI and/or Ethernet PHY in RMII mode. LD22 LD21 LD24 LD23 LD20 Parallel port connection in SPP mode Parallel port connection in EPP mode External debugger connection I 2 C EEPROM MSC711x connection I 2 C EEPROM parallel port connection Green. The board is connected directly to the PC parallel port in SPP mode and the COP/JTAG connector (P14) is irrelevant. Green. The board is connected directly to the PC parallel port in EPP Mode and the COP/JTAG connector (P14) is irrelevant. Green. A command converter can be connected to the COP/JTAG connector (P14). Green. The MSC711x is connected to the I 2 C EEPROM. Green. The parallel port is connected to the I 2 C EEPROM. LD17 Debug mode Green. Indicates whether the MSC711x is forced into Debug mode using SW4-1 (see Section 2.4.2, MSC711x Power-Up Settings (SW4), on page 12). 22 Freescale Semiconductor

23 Reset Board-Level Functions 3 This chapter discusses reset, clock, and power supply. 3.1 Reset There are several reset sources on the MSC711XADS: Power-on reset for both the MSC711x and MPC8272 processors (PORESET). Manual hard reset for both the MSC711x and MPC8272 processors (HRESET). Manual soft reset for the MPC8272 processor (SRESET). MPC8272 internal sources (see also the MPC8272 PowerQUICC II Family Reference Manual). MSC711x internal sources (see also the MSC711x Reference Manual) Power-On Reset The power-on reset to the MPC8272 and MSC711x initializes the processor states after power-up. A dedicated logic unit asserts PORESET input long enough stabilize the MSC711x and MPC8272 core voltages, powered by a different voltage regulator. Power-on reset is either generated manually or by an on-board push button (SW3). At the end of power-on reset, the MPC8272 samples the MODCK[1 3] bits to configure its various clock modes (core, CPM, bus, PCI, and so on). The MODCK[1 3] combination options are selected by means of dip switches, as described in Section 2.4.6, MPC8272 Clock Mode Settings (SW8), on page 15. After deassertion of power-on reset, the hard-reset sequence starts. During the hard-reset sequence, many options are configured. Some of these options are additional clock configuration bits in MODCKH[0 3]. These bits are the most significant bits of the MODCK field, which determine additional options for the clock generator. Although these bits are sampled when the hard reset sequence is entered, they are influential only once: immediately after power-on reset. If a hard reset sequence is entered later, MODCKH[0 3] are sampled but no action is taken. The PCI_MODCK signal is sampled concurrently with the MODCK[0 3] bits and determines the PCI bus clock frequency. When it is asserted high, it divides the PCI bus frequency by two. When it is asserted low, the PCI bus frequency is as determined by the MODCK[1 3] and MODCKH[0 3] signals. At the rising edge of the power-on signal, the MSC711x processor samples four pins to determine its configuration. Those pins are BM0, BM1, SWTE, and HDPOL. These pins are sampled only once immediately after PORESET is deasserted Hard Reset Any one of the following sources can generate a hard reset on the MSC711xADS: COP/JTAG port. Asserting the HRESET line connected to the COP/JTAG port connector directly generates a hard-reset for both the MPC8272 and MSC711x devices, depending on the JP6 position. Freescale Semiconductor 23

24 Board-Level Functions OCE10/JTAG port. Asserting the HRESET line connected to the OCE10/JTAG port connector directly generates a hard reset for only the MSC711x processor. Manual hard reset. Both the MPC8272 and the MSC711x processors have their own HRESET push button. In addition, you can generate a manual hard reset for the MSC711x by toggling a bit in BCSR3. Internal sources. Both the MSC711x and MPC8272 have internal sources that can generate an HRESET in response to specific events. A hard reset causes the MPC8272 and MSC711x processors to reset all their internal hardware except for PLL logic and reacquires the hard-reset configuration from its current source (for the MPC8272). Since hard reset also resets the refresh logic for dynamic RAMs, their content is lost as well. The MPC8272 HRESET can generate an HRESET to the MSC711x processor, depending on the JP6 position. The MSC711x HRESET affects only the MSC711x and does not generate an MPC8272 HRESET. CAUTION: Contention on the HRESET may cause permanent damage to either board logic and/or to the MPC8272 and the MSC711x processors. To prevent contention, always drive HRESET with an open-drain gate. When a hard reset is applied to the MPC8272 (externally as well as internally), it samples the Hard Reset Configuration Word (HRCW). This configuration word can be taken from the Flash memory or BCSR (the most significant 8 bits of the data bus), depending on the JP5 position. 3.2 Clocking There are three main clock circuits on the MSC711xADS board: MPC8272 system clock PCI clock MSC711x system clock MPC8272 System Clock The MPC8272 requires a single clock source as the main clock source. All MPC x bus timings are referenced to the main clock input, CLKIN1. The timing ratio between the main clock input and the bus clock is 1:1, with internal skew elimination via a PLL. A 100 MHz 3.3 V clock oscillator is connected to a low inter-skew buffer (U10) to split the load between all clock consumers on both boards. To provide a clean clock input for proper operation, special care is taken to isolate and terminate the clock route between the on-board PLL and the MPC8272. The main clock scheme is shown in Figure x SDRAM CLK GEN 100 MHz Low Skew Buffers Expansion Mictor Figure 3-1. Main Clock Generator Scheme 24 Freescale Semiconductor

25 3.2.2 PCI Clock Clocking The PCI bus clock is derived internally from the main clock input, CLKIN1. The generated PCI clock is output from a PCI-dedicated PLL (named DLL). That clock output feeds an on-board low-skew and fast clock distributor that distributes the PCI clock to all on-board PCI devices. One of the outputs is fed back to the PCI clock in the MPC8272 via the CLKIN2 input. All PCI bus timings are referenced to the CLKIN2 input clock. This clock input is driven to the DLL, which synchronizes the DLL output clock to the CLKIN2 input clock and thereby maintains low skew between the DLL output and CLKIN2 input. To comply with the PCI standard and achieve bus synchronization and low skew, all copper traces are carefully kept from the clock distributor outputs at the same lengths, including the output that is fed back to CLKIN2. Low Skew Clock Buffer Clock Generator MPC8272 DLLOUT IN OUT1 PCI Device MHz CLKIN1 OUT2 PCI Device 2 CLKIN2 OUT4 OUT3 PCI Device 3 Figure 3-2. PCI Clock Generator Scheme MSC711x System Clock The MSC711x processor requires a reference clock input (CLKIN) by which the clock synthesis module in the MSC711x core generates all the timings needed. The recommended CLKIN frequency is 20 MHz. As Figure 3-3 shows, the clock synthesis module is composed of the following blocks: Phase lock loop (PLL) with associated multipliers and dividers AHB/APB bus clock divider Timer clock multiplex Wake-up control Control registers Together, these blocks generate the following clock signals for core and peripheral clocking: External input clock. provides a reference clock for the system. Core clock. Obtained by a predivision of the input clock and multiplying the frequency in the PLL. AHB clock. Generated similarly to the core clock but with an additional division stage. IPBus clock. Generated from the AHB clock. APB clock. Generated from the AHB clock. Timer clock. Can be derived from the external input clock or from the SkyBlue clock. The control register is used for programming the clock synthesis module. The wake-up control block wakes the processor out of its low-power modes. Freescale Semiconductor 25

26 Board-Level Functions CLKIN CLKO 1 Input Clock 4 CLKOUT MUX CLKCTL STOPCTL HLTREQ HLTACK DIV (/1 to /25) Wake-up Control MULT (x1 to x28) PLL /26 3 /2 5 MUX Timer Clock IPBus Clock / 2 Timer Clock / Clock Synthesis Module AHB DIV (/2) Core Clock ECore clock AHB Clock IPBus Clock APB Clock DDR Clock AHB Clock AHB Clock IPBus Clock CPU SC1400 Core DSP Extended Core to Crossbar Switch, DMA, M2, Boot ROM Device Resources to External. Memory. Controller /2 to DDR Clock Pins External Memory Interface to Ethernet MAC TX_CLK MDC RX_CLK /2, /4,.../126 Ethernet MAC /24 /1 to /216 to UART Tx, Rx UART /22,..., /3840 MUX to Serial Bit Clock I2C EVNT 32-bit Event Port IPBus Timer A Outputs Timer B Outputs Timer Clock MUX MUX to TDM Clock, Frame Sync Generator TDM Peripheral Timers Timer Module Debug Port Watchdog Clock to 32-Bit Watchdog Timer Watchdog Timer 1 Clocks can be disabled in Stop mode. Disables PLL, core clock, ECore clock, AHB clock, IPBus clock, and APB Clock. 2 Clocks can be disabled at this point in Stop mode. Disables ECore clock, AHB clock, IPBus clock, and APB clock. 3 Clocks are disabled at this point in Wait and Stop modes. Disables the ECore clock. 4 Clocks can be disabled at this point in Stop mode. Disables the input clock used in timer clock generation. 5 Clocks can be disabled at this point in Stop mode. Disables the watchdog timer clock. 6 Clocks can be disabled at this point in Stop mode. Disables the DDR clock. Figure 3-3. MSC711xADS Timing System 26 Freescale Semiconductor

27 3.3 Power Supply Power Supply The MSC711xADS uses the following voltages: 5 V: (Command converter). 3.3 V: (MSC711x and MPC8272 I/O and for most of the components) 2.5 V: (SSTL components: the DDR chip and the DDR interface in the MSC711xADS). V REF : (1.25 V for DDR active termination). 1.5 V: MPC8272 core voltage. 1.2 V: MSC711x core voltage. These voltages are derived from the 12 V main power supply (switch P23). The MSC711xADS maximum currents demands are: 100 ma for the I/O at 3.3 V. 240 ma for the SSTL_IO +DDR at 2.5 V. 511 ma for the core at 1.2 V. The MSC711xADS has three distinct power supplies (1.2 V core, 2.5 V DDR I/O, and 3.3V standard I/O). When the board is powered up or powered down, the following sequences of operations must be followed. The power-up sequence is as follows: 1. Turn on the highest supply (3.3 V standard I/O). 2. Turn on the 2.5 V DDR I/O supply. 3. Turn on the lowest supply (1.2 V core). The power-down sequence is as follows: 1. Turn off lowest supply (1.2 V core). 2. Turn off 2.5 V DDR IO. 3. Turn off highest supply last, 3.3 V standard I/O. CAUTION: Latch up forward biasing of ESD devices and excessive currents can lead to severe device damage. To avoid this problem, a proper power-up and power-down sequence at the board level must performed. Freescale Semiconductor 27

28 Board-Level Functions Voltage (VIO)t 3.3 V Ramp-Down (VSSTL)t 2.5 V Ramp-Up (VCORE)t 1.2 V Voltage Difference Must Be > 0.7V Time Figure 3-4. MSC711xADS Power Up/Power Down Sequence From a time variant viewpoint, when power is ramped up or down, the 2.5 V supply must at any instant maintain a voltage that is at least 0.7 V less than that of the 3.3 V supply. Also, at any instant, the 1.2 V supply must maintain a voltage that is at least 0.7 V less than that of the 2.5 V supply. 3.3 V DC 2 DC 12 V to 3.3 V 10A Max 3.3 V 10A LDO 2.5 V 2.5 V LDO 1.5 V 1.5 V LDO 1.2 V 1.2 V VTT 1.25 V 1.25 V LDO 12 V to 5 V 5 V Power Up Reset Power Sequence Figure 3-5. Power Supply Block Diagram 28 Freescale Semiconductor

29 Memory Map Memory Map/Programming Model 4 This chapter presents a recommended memory map and describes the MSC711xADS registers in detail. The MPC8272 memory controller is used as a chip-select generator to access on-board (and external) memories, saving board area and reducing cost and power consumption while increasing flexibility. When a CS region assigned to a buffered memory is disabled via the BCSR, the local data transceivers are disabled during access to that region to prevent possible contention on data lines. Table 3-1 shows the MPC8272 chip-select assignments to the various memories/registers on the MSC711xADS. 4.1 Memory Map Table 3-1. MPC8272 Chip-select Assignments Chip Select Assignment Bus CS0 Flash memory 60x (buffered) CS1 BCSR 60x (buffered) CS2 SDRAM 60x (main) CS3 PMC E1/T1 framer (via the BCSR) 60x (buffered) CS4 PEF20451 TSI switch (via the BCSR) 60x (buffered) CS5 SLIC-SLAC MPI (via the BCSR) 60x (buffered) CS6 HDI CS0 60x (buffered) CS7 HDI CS1 60x (buffered) All accesses to the MPC8272 memory slaves are controlled by the MPC8272 memory controller. Therefore, the memory map is reprogrammable. After a hard reset, the debugger checks for the size, delay, and type of the Flash memory on the board and programs the memory controller accordingly. The SDRAM and the Flash memory respond to all types of memory access; that is, problem /supervisory, program/data, and DMA. The memory map shown in Table 3-2 is a recommended memory map. However, the devices addresses can be moved around the map, according to your needs. Table 3-2. Memory Map Address Range Memory Type Port Size Memory Size 0x x03FFFFFF 60x SDRAM 64 bit 64 MB 0x x044FFFFF Empty Space 5 MB Freescale Semiconductor 29

30 Memory Map/Programming Model 0x x04507FFF 0x x x x C 0x x x x C Table 3-2. Memory Map (Continued) Address Range Memory Type Port Size Memory Size BCSR[0 7] BCSR0 BCSR1 BCSR2 BCSR3 BCSR4 BCSR5 BCSR6 BCSR7 32 Bits 32 KB 4 Bytes 4 Bytes 4 Bytes 4 Bytes 4 Bytes 4 Bytes 4 Bytes 4 Bytes 0x x045FFFFF Empty space 1 MB 0x x04607FFF E1/T1 Framer 8 Bits 32 KB 0x x0460FFFF SLIC/SLAC 32 Bits 32 KB 0x x04617FFFF TSI 8 Bits 32 KB 0x x0471FFFF MPC8272 internal map 32 Bits 128 KB 0x x04727FFFF HDI CS1 16 Bits 32 KB 0x x0472FFFF HDI CS2 16 Bits 32 KB 0x x047FFFFF Empty space ~800 MB 0x x04FFFFFF PCI memory agent PIMMR 32 Bits ~5 MB 0x x7FFFFFFF Empty space ~2 GB 0x xBFFFFFFF PCI memory GPL windows 32 Bits 1 GB 0xC xFF7FFFFF Empty space ~240 MB 0xFF xFFFFFFFF Flash 16 Bits 8 MB 4.2 Board Control and Status Registers (BCSRx) Most hardware options on the MSC711xADS are controlled or monitored by the BCSR, which is a 32-bit wide set of read/write registers. The BCSR is accessed via the MPC8272 memory controller and includes registers BCSR[0 7]. Since the minimum block size for a chip select region is 32 KB and only three lines, A[27 29], are decoded by the BCSR for register selection, BCSR[0 7] are duplicated inside that region. 30 Freescale Semiconductor

31 Board Control and Status Registers (BCSRx) BCSR0 Board Control Status Register 0 Offset 0x0 Bit PQETHEN PQETH PQRSEN CONFEN Bootp GPLLED0 GPLLED1 RST TYPE R/W R R/W R RESET Bit TYPE R RESET BCSR0 is accessed at offset 0x0 from the BCSR base address. BCSR0 gets its defaults at power-on reset. Table 4-1. BCSR0 Bit Descriptions Bit Reset Value Description Settings PQETHEN 0 PQETHRST 1 PQRSEN 2 0 MPC8272 Ethernet enable. 0 Disabled. 1 Enabled. 1 MPC8272 Ethernet reset. 1 Deasserted. 0 Asserted. 1 MPC8272 RS-232 transceiver enable. 1 Disabled. 0 Enabled. CONFEN 3 1 MPC8272 Hard Reset Configuration Word source. 0 Flash memory. 1 BCSR. Bootp 4 1 Flash boot sector write protect: 0 Protect. 1 Do not protect. 5 Reserved. Write to zero for future compatibility. GPLLED0 6 GPLLED General-purpose LED 0. 0 ON. 1 OFF. 1 General-purpose LED 1. 0 ON. 1 OFF. Reserved. Write to zero for future compatibility. Freescale Semiconductor 31