Maintenance/ Discontinued

Transcription

1 For Communications Equipment MN86062 CODEC LSI for Facsimile Images Overview The MN86062 is a high-speed LSI codec for compressing and decompressing images using the MH, MR, and MMR standard compression methods specified in the ITU-T T.4 and T.6 recommendation. Registers and other settings provide flexible support for a variety of processing. Features Compression methods MH, MR, and MMR Operating mode: Page mode Bus configuration: Choice of dual- or single-bus operation Decoding error processing: Choice of replacing with the previous line or a white line Image bus configuration: 8 bits, maximum 16 megabytes address space of image bus, 2-channel master DMA System bus configuration: X80 interface compatible, 8 bits, 2-channel slave DMA Pixels per line: maximum 64K, in byte increments Concurrent DMA transfers over image bus and command processing Support for pointer management for image buffer Wide selection of independent parameters for coding, decoding, transfers between buses, and DMA transfersr Support for time-shared processing by line for both coding and decoding Applications Facsimile equipment

2 MN86062 For Communications Equipment Pin Assignment N.C.1 N.C.2 IA18 IA17 IA16 IA15 IA14 IA13 IA12 IA11 IA10 IA9 IA8 IA7 IA6 IA5 IA4 IA3 IA2 IA1 IA0 IA19 IA20 IA21 IA22 IA23 NDCMP NDEND NDACK1 NDACK0 NDREQ1 NDREQ0 NIDACK IR/W NIAEN NDRUN NIBACK NIBREQ 2SYSCLK V DD1 V SS1 SYSCLK V SS2 V DD2 TACK V SS3 V DD3 N.C.3 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 V DD4 V SS4 TEST2 TEST1 TEST0 NACKD NACKC (TOP VIEW) QFP084-P TEST3 TEST4 D0 D1 D2 D3 D4 D5 D6 D7 NIRQ NRESET A0 A1 A2 A3 NCS NRD NWT NREQC NREQD

3 For Communications Equipment MN86062 Block Diagram A(3:0) D(7:0) NCS NRD NWT NIRQ NRESET 2SYSCLK SYSCLK NREQC NACKC NREQD NACKD V DD V SS TEST(4:0) Microprogram control block System bus interface Slave DMA (2 channels) Coding FIFO Decoding FIFO Main sequencer Sub sequencer ALU1 ALU2 Register bank Parameter register Table look-up block Coding table Decoding table Mode selection block Change point detector Image reconstruction block Image bus interface Master DMA (2 channels) Reference line FIFO Coding line FIFO IA(23:0) ID(7:0) IR/W NIAEN NIDACK NIBREQ NIBACK NDREQ0 NDACK0 NDREQ1 NDACK1 NDRUN NDEND NDCMP

4 MN86062 For Communications Equipment Pin Descriptions System Bus Interface Pin No. Symbol I/O Function Description 27 A3 I Address bus for accessing internal registers 28 A2 29 A1 30 A0 33 D7 I/O Data bus for bidirectional transfers over system bus 34 D6 Tristate 35 D5 36 D4 37 D3 38 D2 39 D1 40 D0 24 NWT I Connect to WR pin on X80-compatible microprocessor 25 NRD I Connect to RD pin on X80-compatible microprocessor 26 NCS I Chip select pin 23 NREQC O This output pin indicates a DMA transfer request from the to Tristate memory. 22 NREQD O This output pin indicates a DMA transfer request from the memory to Tristate NACKC I This input pin accepts the response to the NREQC signal. 20 NACKD I This input pin accepts the response to the NREQD signal. 32 NIRQ O Open drain This output pin indicates an interrupt request. 31 NRESET I External input resets the SYSCLK I This input pin accepts a clock signal with twice the system clock frequency. 43 SYSCLK O This output pin provides a clock signal with half the frequency of 2SYSCLK. 15 V DD4 I Connect these power supply pins to a 5 volt power supply. 5 V DD3 2 V DD2 45 V DD1 16 V SS4 I Connect these power supply pins to ground. 4 V SS3 1 V SS2 44 V SS1 41 TEST4 I Do not use these test pins. 42 TEST3 17 TEST2 18 TEST1 19 TEST0 3 TACK O Do not use these test pins.

5 For Communications Equipment MN86062 Pin Descriptions (continued) Image Bus Interface (continued) Pin No. Symbol I/O Function Description 59 IA23 O Image address bus. The address is valid when the NIAEN pin is at "L" 60 IA22 Tristate level. 61 IA21 62 IA20 63 IA19 66 IA18 67 IA17 68 IA16 69 IA15 70 IA14 71 IA13 72 IA12 73 IA11 74 IA10 75 IA9 76 IA8 77 IA7 78 IA6 79 IA5 80 IA4 81 IA3 82 IA2 83 IA1 84 IA0 7 ID7 I/O Image data bus for bidirectional transfers of image data 8 ID6 Tristate 9 ID5 10 ID4 11 ID3 12 ID2 13 ID1 14 ID0 47 IBREQ O This output pin indicates a request for control of the image bus. 48 IBACK I This input pin accepts the response to the NIBREQ signal. 50 IAEN O This output pin indicates whether the values of image address bus are Tristate valid. 51 IR/W O This output pin indicates the data transfer direction for the image bus. Tristate

6 MN86062 For Communications Equipment Pin Descriptions (continued) Image Bus Interface (continued) Pin No. Symbol I/O Function Description 52 IDACK I This input pin indicates the end of a data read or write operation. 49 DRUN O This output pin indicates whether a DMA transfer is in progress. Tristate 57 DEND O This output pin indicates the end of a DMA cycle. 58 DCMP O This output pin indicates successful completion of a DMA block transfer. 53 DREQ0 I This input pin indicates a DMA transfer request from the I/O block to memory. 54 DREQ1 I This input pin indicates a DMA transfer request from the memory to I/O block. 55 DACK0 O This output pin gives the response to the NDREQ0 signal. 56 DACK1 O This output pin gives the response to the NDREQ1 signal. Test Pin Setting Symbol Pin No. Fixed Level TEST0 19 GND TEST1 18 GND TEST2 17 GND TEST3 42 GND TEST4 41 GND

7 For Communications Equipment MN86062 Package Dimensions (Unit: mm) QFP084-P ± (1.00) 18.00± ±0.10 SEATING PLANE ± ±0.10 (1.00) 2.90 max ± ±0.40 (2.45±0.20) (1.30±0.20) 0 to 10

8 Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products, and no license is granted under any intellectual property right or other right owned by our company or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. Any applications other than the standard applications intended. (4) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd.