Maintenance/ Discontinued

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Miles Crawford
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1 For Communications Equipment High-Speed CODEC LSI for Facsimile Images Overview The is a high-speed LSI codec for compressing and decompressing facsimile images. Features include real-time printing to laser printers, built-in line memory, enlargement and reduction, and code conversion. Features Pixels per line: between 16 and 464 bits, in word (16-bit) increments. Processing time per line: Individual pixels are processed within two system clock cycles. For a machine cycle of 10 MHz, processing the worst-case pattern for a 4096-bit line takes no more than 1 ms. Time-shared, multiplex processing Support for time-shared, multiplex processing allows image I/O, enlargement/reduction processing, and coding/decoding to proceed concurrently for a group of lines. Image bus DMA transfers can also proceed concurrently with command processing. Multiple channels If lines consist of 2432 bits or fewer, commands can be processed simultaneously on two channels using time-sharing. These commands may be issued asynchronously. Bus configuration There are separate system and image buses. The latter features two independent master DMA channels; the former, four slave DMA channel pins. Image data I/O Image data I/O can use either the image or system bus. Byte conversion When the system bus is 16 bits wide, the chip can swap the upper and lower bytes of image or coded data. It can also swap the MSB and LSB. Memory management The chip includes pointer management for the image buffer connected to the image bus. Machine cycle The limit is 10 MHz. This means that the maximum input clock is twice this, or 20 MHz. Function Message coding: MH, MR, MMR, and MG3. The chip also supports data transfers on the image and system buses and DMA transfers on the image bus alone. Coding conversion The chip converts between all supported message coding systems: MH, MR, MMR, and MG3. Enlargement/reduction These may be added to coding, decoding, code conversion, and data transfer operations. (1) In the primary scan direction, the chip uses multiplication on the change point address. The scaling factor can be anywhere between approximately 0.1% and 200% in increments of approximately 0.1%. Integral multiplication is also available beyond this (2) In the subscanning direction, the chip uses decimation and replication. The scaling factor can be anywhere between approximately % and 200% in increments of approximately %. Integral multiplication is also available from 2 to 65,535. White masks for both edges These may be added to coding, decoding, code conversion, and data transfer operations. They change all pixels within the margins, specified in bit increments, to white. Decoding error processing The chip offers a choice of replacing with the previous line or a white line. Applications Facsimile equipment includes following four Product lifecycle stage.

2 For Communications Equipment Pin Assignment IA0 IA1 IA2 IA3 IA4 IA5 IA6 IA7 IA IA9 IA10 IA11 IA12 IA13 IA14 IA15 V DD2 V SS2 DACK1 DACK0 DSTR0 DSTR1 IMLE IMUE DCMP0 V SS3 V DD3 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 V SS4 V DD4 TEST3 TEST2 TEST1 TEST0 RESET HEX INTR0 INTR1 INTR2 2SYSCLK RD WR SYSCLK D15 D14 D13 D12 D11 D10 D9 D D7 D6 D5 D4 D3 D2 D1 D0 QFP100-P DCMP1 IREADY IOW IMW IOR IMR DREQ0 DREQ1 IHACK IHREQ V DD1 V SS1 A0 A1 A2 A3 ACKD1 ACKD0 ACKC1 ACKC0 REQD1 REQD0 REQC1 REQC0 UBE includes following four Product lifecycle stage.

3 For Communications Equipment Pin Configuration The features two buses: the system bus, which is primarily used for transferring coded data to and from a microprocessor and other components and the image bus, which is used for transferring image data to or from a scanner, printer, or the like. Pin Function Chart The chip has a total of 100 pins: 39 for the system bus, 49 for the image bus, and 12 for testing, power supply, and other purposes. System bus pins A0 to A3 D0 to D15 UBE RD WR HEX RESET INTR0 to 2 REQC0 REQC1 REQD0 REQD1 ACKC0 ACKC1 ACKD0 ACKD1 2SYSCLK SYSCLK TEST0 to 3 MN606X Image bus pins IA0 to 15 ID0 to 15 IHREQ IHACK IREADY IMUE IMLE IMR IMW DSTR0 DSTR1 DREQ0 DREQ1 DACK0 DACK1 DCMP0 DCMP1 IOR IOW includes following four Product lifecycle stage. VDD0 to 3 VSS0 to 3

4 For Communications Equipment Pin Descriptions System Bus 35 A3 I Address. Address bus for accessing internal registers 36 A2 37 A1 3 A0 9 D15 I/O Data. Data bus for bidirectional transfers over system bus 10 D14 11 D13 12 D12 13 D11 14 D10 15 D9 16 D 17 D7 1 D6 19 D5 20 D4 21 D3 22 D2 23 D1 24 D0 26 UBE I Upper byte enable. This input pin specifies whether the data from pins D15 D is effective. 6 RD I Read. This input pin specifies a read from the specified register. 7 WR I Write. This input pin specifies a write to the specified register. 25 I Chip select. This input pin specifies access to a register. 1 HEX I Data bus width selection. This input pin specifies the width of the system data bus: "0" for 16 bits; "1" for bits. 100 RESET I Reset. This input pin resets the internal circuitry, clearing all registers. 2 INTR0 O Interrupt request 0. This output pin indicates an interrupt request Open corrector triggered by the cause given in interrupt register 0 (STIR0) 3 INTR1 O Interrupt request 1. This output pin indicates an interrupt request Open triggered by the cause given in interrupt register 1 (STIR1) corrector 4 INTR2 O Interrupt request 2. This output pin indicates an interrupt request includes following four Product lifecycle stage. Open corrector triggered by the cause given in DMA transfer interrupt register (DMIR). 27 REQC0 O DMA transfer output request 0. This output pin indicates a request for data output on DMA channel 0. 2 REQC1 O DMA transfer output request 1. This output pin indicates a request for data output on DMA channel 1.

5 For Communications Equipment Pin Descriptions (continued) System Bus (continued) 29 REQD0 O DMA transfer input request 0. This output pin indicates a request for data input on DMA channel REQD1 O DMA transfer input request 1. This output pin indicates a request for data input on DMA channel ACKC0 I DMA transfer output acknowledge 0. This input pin accepts the response to a DMA transfer request with REQC0. 32 ACKC1 I DMA transfer output acknowledge 0. This input pin accepts the response to a DMA transfer request with REQC1. 33 ACKD0 I DMA transfer input acknowledge 0. This input pin accepts the response to a DMA transfer request with REQD0. 34 ACKD1 I DMA transfer input acknowledge 0. This input pin accepts the response to a DMA transfer request with REQD1. 5 2SYSCLK I 2 system clock. This input pin accepts a clock signal with a frequency twice that of the system clock. SYSCLK O System clock. This output pin provides a clock signal with half the frequency of 2SYSCLK. Image Bus 60 IA15 O Image address bus. These pins provide an address on the image data bus. 61 1A14 62 IA13 63 IA12 64 IA11 65 IA10 66 IA9 67 IA 6 IA7 69 IA6 70 IA5 71 IA4 72 IA3 73 IA2 74 IA1 75 IA0 includes following four Product lifecycle stage.

6 For Communications Equipment Pin Descriptions (continued) Image Bus (continued) 7 ID15 I/O Image data. These pins form a bus for bidirectional transfers of image data. 79 ID14 0 ID13 1 ID12 2 ID11 3 ID10 4 ID9 5 ID 6 ID7 7 ID6 ID5 9 ID4 90 ID3 91 ID2 92 ID1 93 ID0 41 IHREQ O Image bus request. This output pin indicates a request for control of the image bus. 42 IHACK I Image bus acknowledge. This input pin indicates when the chip can seize control of the image bus. 49 IREADY I Image data acknowledge. This input pin indicates the end of the read/ write operation. 52 IMUE O Image memory upper byte enable. This output pin specifies whether the data from pins ID15 ID is effective. 53 IMLE O Image memory lower byte enable. This output pin specifies whether the data from pins ID7 ID0 is effective. 45 IMR O Image memory read. This output pin indicates a read from the address on the image address bus. 47 IMW O Image memory write. This output pin indicates a write to the address on 55 DSTR0 O the image address bus. DMA start 0. This output indicates that the chip is ready for a DMA transfer from an I/O device to memory. 54 DSTR1 O DMA start 1. This output indicates that the chip is ready for a DMA transfer from memory to an I/O device. 44 DREQ0 I DMA request 0. This input pin indicates a request for a DMA transfer from an I/O device to memory. 43 DREQ1 I DMA request 1. This input pin indicates a request for a DMA transfer from memory to an I/O device. 56 DACK0 O DMA acknowledge 0. This output pin gives the response to the DREQ0 signal, initiating a DMA transfer from an I/O device to memory. 57 DACK1 O DMA acknowledge 1. This output pin gives the response to the DREQ1 signal, initiating a DMA transfer from memory to an I/O device. includes following four Product lifecycle stage.

7 For Communications Equipment Pin Descriptions (continued) Image Bus (continued) 51 DCMP0 O DMA complete 0. This output pin indicates the successful completion of the DMA transfer of 1 line of data from an I/O device to memory. 50 DCMP1 O DMA complete 1. This output pin indicates the successful completion of the DMA transfer of 1 line of data from memory to an I/O device. 46 IOR O I/O device read. This output pin indicates a read from an I/O device connected to the image address bus. 4 IOW O I/O device write. This output pin indicates a write to an I/O device Power on Reset Circuit connected to the image address bus. 96 TEST3 I Test mode. Connect all these pins to the ground. 97 TEST2 9 TEST1 99 TEST0 40 V DD1 I 5 volt power supply. Connect all these pins to a 5 volt power supply. 59 V DD2 77 V DD3 95 V DD4 39 V SS1 I Ground. Connect all these pins to the ground. 5 V SS2 76 V SS3 94 V SS4 includes following four Product lifecycle stage.

8 For Communications Equipment Application Circuit Example #1. Sample Connections to System Bus (MPU) CLKIN BUFR/W BUFEN AD(0 to 15) A(16 to 15) BS(0 to 2) ASTB HDACK UBE IORD IOWR MRD MWT DMARQ0 DMAAK0 DMARQ1 DMAAK1 DMARQ2 DMAAK2 DMARQ3 DMAAK3 INTR0 INTR1 INTR2 RST (Upper half of memory) 256-Kbit SRAM A(0 to 14) I/O(0 to 7) WE (Lower half of memory) OE 256-Kbit SRAM A(0 to 14) I/O(0 to 7) WE OE V +5V 74HC245 G B DIR A 2 pieces 74HC573 D Q C OC 3 pieces A(1 to 15) D( to 15) A(1 to 15) D(0 to 7) 15 Address Decoder 15 Address bus A0 A(0 to 3) BS(0 to 2) A(4 to 19) BS(0 to 2) A(16 to 19) Data bus 4 D(0 to 15) 16 Address Decoder Crystal oscillator circuit (20 MHz) A(0 to 3) D(0 to 15) UBE RD WT HEX REQC0 ACKC0 REQC1 ACKC1 REQD0 ACKD0 REQD1 ACKD1 INTR0 INTR1 INTR2 2SYSCLK RESET Power on reset circuit includes following four Product lifecycle stage.

9 For Communications Equipment Application Circuit Example #2. Sample Connections to Image Bus Address bus Data bus IHREQ IHACK IA(0 to 15) ID(0 to 15) DSTR0 DCMP0 DREQ0 DACK0 IOR SYSCLK IREADY DSTR1 DCMP1 DREQ1 DACK1 IOW IMUE IMLE IMR IMW +5V Low-speed device +5V Bus Arbiter Timing control IA(1 to 15) ID( to 15) IA(1 to 15) ID(0 to 7) (Upper half of memory) 256-Kbit SRAM A(0 to 14) I/O(0 to 7) WE OE (Lower half of memory) 256-Kbit SRAM A(0 to 14) I/O(0 to 7) WE OE Scanner Printer includes following four Product lifecycle stage.

10 For Communications Equipment Package Dimensions (Unit: mm) QFP100-P ± (1.20) 1.00± ±0.10 SEATING PLANE 2.50± ± (1.20) 2.90 max. 1.00± ±0.40 (1.30±0.20) 0.05 (2.45±0.20) 0 to 10 includes following four Product lifecycle stage.

11 Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products, and no license is granted under any intellectual property right or other right owned by our company or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. Any applications other than the standard applications intended. (4) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd. includes following four Product lifecycle stage.

Maintenance/ Discontinued

Maintenance/ Discontinued For Communications Equipment MN86062 CODEC LSI for Facsimile Images Overview The MN86062 is a high-speed LSI codec for compressing and decompressing images using the MH, MR, and MMR standard compression