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1 How to Transmit or Receive Frames Semiconductor Business Division AIS Company Panasonic Corporation 1 AP-MN87400_

2 CONTENTS 1 PURPOSE SEQUENCE TO TRANSMIT FRAMES BASIC TRANSMISSION SETTING DATA IN THE FRAME MEMORY Setting INFO Data Setting SFD Data Setting PHR Data Setting MACBODY START OF TRANSMISSION TRANSMISSION COMPLETION AND FAILURE PROCEDURE FOR RECEPTION BASIC RECEPTION RECEPTION START INTERRUPT RECEPTION COMPLETE INTERRUPT RECEPTION FAILURE INTERRUPT READING FRAMES FROM FRAME MEMORY CLEARING THE BUFFER AP-MN87400_

3 1 Purpose This application note summarizes the settings or sequence necessary to transmit or receive frames using MN87400 or MN To transmit or receive frames, the basic setting at 920 MHz described in the separate application note (AP_MN87400_004_Basic Setting Example) must be initially made as follows: SFD length = 2 bytes PHR length = 2 bytes CRC length = 4 bytes (Automatically appended by hardware) 2 Sequence to Transmit Frames 2.1 Basic Transmission Transmission without carrier sense A frame transmission is performed by writing INFO, SFD, PHR, and frame itself of the frame to be sent in the frame memory for transmission and then writing 1 to the ISSUE_TX bit of the TXFRMCTR register (004h). Completing a frame transmission generates a transmission complete interrupt. (Interrupt will be generated in case of failure.) uc MN87400//401 The other Write INFO. Write SFD. Write PHR. Write MACBOODY. Issue a transmission command. (TXFRMCTR.ISSUE_TX) ISSUE TX Frame Transmission is complete. INTR Figure 2-1 Transmission Sequence (without carrier sense) 3 AP-MN87400_

4 Two interrupts are used for transmission: transmission complete and transmission failure. The content of interrupt can be checked by the INTEVENT register Transmission with carrier sense When performing a carrier sense before transmission, first, write INFO, SFD, PHR, and frame itself of the frame to be sent in the frame memory for transmission. Second, execute carrier sense (Refer to the application note "AP_MN87400_003_RSSI+CarrierSense " for the carrier sense). After the carrier sense is done, if not busy, set the ISSUE_TX bit of the TXFRMCTR register (004h) to 1. Completing a frame transmission generates a transmission complete interrupt. (Interrupt will be generated in case of failure.) uc MN87400//401 The other Write INFO. Write SFD. Write PHR. Write MACBOODY. Request of carrier sense (TXFRMCTR.BKOFF_REQ) Carrier sense is complete. Read of the result BKOFF_REQ INTR RR If carrier sense is successful Issue a transmission command. (TXFRMCTR.ISSUE_TX) ISSUE TX Frame Transmission is complete. INTR Figure 2-2 Transmission Sequence (with carrier sense) 4 AP-MN87400_

5 2.1.3 Transmission expecting ACK frame When ACK reception is used to indicate of transmission frame output from TX frame buffer, set the ACKREQ_TX bit of the TXFRMCTR register (004h) to 1, before a frame transmission. A transmitting procedure follows Section or Section When ACK reception is used for transmission, waits for ACK on certain period, after frame transmission. If ACK is not received, the frame is re-transmitted. When ACK is not received even after 3 times re-transmission (re-transmission limitation can be set by register), transmission process is stopped and Interrupt will be generated. uc MN87400//401 The other Write INFO. Write SFD. Write PHR. Write MACBOODY. Issue a transmission command. (TXFRMCTR.ISSUE_TX) ISSUE TX Frame TX Frame (re-transmission) Transmission is complete. INTR ACK Figure 2-3 Transmission Sequence (expecting ACK frame) 2.2 Setting Data in the frame Memory Two planes of frame memory have been provided: TX frame buffer 1 and TX frame buffer 2. This section describes the way to set a transmission data by using TX frame buffer 1. The same setting is applied to TX frame buffer 2, but address is different. 5 AP-MN87400_

6 000h TX frame buffer 1 (256Bytes) info SFD PHR MHR 3bytes 0-3bytes 0-7bytes 100h 110h 120h 220h 240h ACK(16bytes) RESERVED(16bytes) TX frame buffer 2 (256Bytes) Reserved(32bytes) AUX CoM flag Payload Nonce MAC frame (exclude CRC) 340h 380h 3FFh (1024bytes) RX frame buffer (256Bytes) Reserved(64bytes) RFparams(128Bytes) info SFD PHR FC SQN Figure 2-4 Architecture of Frame Buffer 3bytes 0-3bytes 0-7bytes 2bytes 1bytes TX frame buffer 1 starts from address 000h. Write INFO information to addresses 000h through 002h, SFD information to 003h through 004h, PHR information to 005h through 006h, and MACBODY to 007h and subsequent addresses by the number of bytes required a INFO SFD PHR MAC BODY Figure 2-5 Setting Format of TX Frame Buffer 1 6 AP-MN87400_

7 2.2.1 Setting INFO Data INFO field of 3 bytes is used to specify transmission antenna information and frame length. In this INFO field, set the length of SFD and the frame length (MACBODY length) excluding PHR length. When appending CRC by hardware, set the length including CRC. INFO SFD PHR MAC BODY CRC Figure 2-6 Length of INFO Field Attached by hardware In the format of INFO field, as shown in Figure 2-7, set antenna information in INFO0(000h), and store the MACBODY + CRC length of 11 bits in INFO1(001h) and INFO2(002h) INFO0 ANT Reserved INFO1 Reserved PSDULen[10:8] INFO2 PSDULen[7:0] Figure 2-7 INFO Field Format The data set in INFO field is not output on AIR Setting SFD Data SFD and subsequent data are actually output on AIR. The transmission data is read from the address (003h) in TX frame buffer 1 sequentially in byte units and output on AIR. Before SFD, preamble pattern is output, but it is unnecessary to set preamble data in TX frame buffer 1. Data of multiple bytes (address, etc.) like SFD is stored in TX frame buffer 1 sequentially from the lower bytes. IEEE g defines that SFD = 7209h. In this case, beginning from its lower bytes, to output data on AIR, store the data as follows. TX frame buffer1 (003h) = 09h TX frame buffer1 (004h) = 72h 7 AP-MN87400_

8 2.2.3 Setting PHR Data PHR data is stored in TX frame buffer following SFD. The format of PHR consists of 2 bytes as shown in Figure 2.8. PHR[15:8] Length[7:0] R R PHR[7:0] C R C L D 1 W 0 L 0 9 L 0 8 Data Whitening On(1)/Off(0) CRC Len 2Octet(1)/4Octet(0) Figure 2-8 PHR Format for 2 Octets of PHR Length PHR is also stored in TX frame buffer 1 in the order of lower and upper bytes. For example, when setting Length = 9 octet (= 9 bytes), Data Whitening = OFF, and CRCLEN = 4 octet, PHR becomes 0900h. Therefore, set the following. TX frame buffer 1 (005h) = 00h TX frame buffer 1 (006h) = 09h Setting MACBODY MACBODY is a frame itself. Write the data of bytes specified by the length of INFO in TX frame buffer 1. To calculate CRC automatically by hardware, the number of bytes, length in INFO field length of CRC, is used for data transmission. When the length in INFO is set to 9 and CRC length is 4 bytes, the effective length of MACBODY is 5 bytes. In IEEE g, the first 2 bytes of MACBODY are defined as the FC part. FC part includes the information on ID lengths, the existence of an ACK demand, etc. When the frame of ACK expectation is transmitted, set TYPE= 001 or 011, AR =1 and other bits to 0. If not expectation, set all FC bits to 0. 8 AP-MN87400_

9 BEACON/DATA/ACK/COM FRAME (TYPE= ) FC part bit position SRC ADDR MODE VER DEST ADDR MODE IE PRESENT SQN Suppression PANID COMPRESS RESERVED AR PENDING SEC TYPE DATA FRAME (TYPE=101) FC part bit position IE PRESENT AR VER PENDING SQN Suppression SEC PANID PRESENT SRC ADDR MODE DEST ADDR MODE TYPE Figure 2-9 format of FC part If you wish to send MACBODY in the order of 11h, 22h, and 33h except FC part, the data stored in TX frame buffer 1 is in the following order, beginning from the address of 000h. The example of a frame of ACK expected nothing ----INFO SFD--- --PHR MACBODY CRC FC--- 00h 00h 09h 09h 72h 00h 09h 00h 00h 11h 22h 33h 00h 00h 00h 00h The example of a frame of ACK expected ----INFO SFD--- --PHR MACBODY CRC FC h 00h 09h 09h 72h 00h 09h 21h 00h 11h 22h 33h 00h 00h 00h 00h The portion of CRC is automatically calculated by hardware, so no data setting is required. In this example, the portion of CRC is padded with 00h. 9 AP-MN87400_

10 2.3 Setting of ACK expected To set of ACK expected, use ACKREQ_TX0 (or ACKREQ_TX1) of the TXFRMCTR register (004h). In this section, data has been stored in TX frame buffer 1, so set ACKREQ_TX0 to 1. RegisterName Address RW Default TXFRMCTR 004h RW 0000h Validation bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Reserved REST_CAL SYMCLK _STP bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 BKOFF_ BKOFF_ TX_FRM_PROP ACKREQ_ ACKREQ_ ISSUE_ ISSUE RESULT REQ TX1 TX0 TX1 _TX0 (Read Only) 2.4 Start of Transmission To start a frame transmission, use ISSUE_TX0 (or ISSUE_TX1) of the TXFRMCTR register (004h). In this section, data has been stored in TX frame buffer 1, so use ISSUE_TX0. RegisterName Address RW Default TXFRMCTR 004h RW 0000h Validation bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Reserved REST_CAL SYMCLK _STP bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 BKOFF_ BKOFF_ TX_FRM_PROP ACKREQ_ ACKREQ_ ISSUE_ ISSUE RESULT REQ TX1 TX0 TX1 _TX0 (Read Only) When the ISSUE_TX0 bit is set to 1, the data stored in TX frame buffer 1 is sequentially sent to AIR, following preamble. 10 AP-MN87400_

11 2.5 Transmission Completion and Failure When transmission is success or failure, the ISSUE_TX0 bit is automatically cleared to 0 and at the same time an interrupt is generated. The source of the interrupt is checked by reading the INTEVENT register. RegisterName Address RW Default INTEVENT 003h R 0000h Validation bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 UNLOCK BUFEMP DETPRE SSLOT INACT CAPEND BKOFF MISC bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 BEALOS GTS BEACON TXFAIL TXEND RXFAIL RXEND RXST The success of transmission generates an TXEND interrupt. Read the INTEVENT register and check the source of the interrupt. If TXEND (bit 3) is 1, clear the interrupt source to prepare for the next transmission. 11 AP-MN87400_

12 The failure of transmission generates an TXFAIL interrupt. Read the INTEVENT register and check the source of the interrupt. If TXFAIL (bit 4) is 1, the transmission is failure. To detect the source of the failure, read TXFAIL_INFO (bits 2:0) of the STATUS register. RegisterName Address RW Default STATUS 006h R 0180h Validation bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 VER bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CAP CUR_SLOT TXFAIL_INFO The source of failure involves the following 4 types. 000: Back-off failure 001: Re-transmission count limit has been exceeded. 010: Out of contention access period 011: Parameter error 12 AP-MN87400_

13 3 Procedure for Reception 3.1 Basic Reception The start of frame reception generates a reception start interrupt, and the completion of it generates a reception complete interrupt. The frames received are stored in RX frame buffer, and the frame data can be read from the buffer by uc. uc MN87400 The other RX Frame Reception starts. INT INT Reception is complete. MR Read the frame. RX BUFF Clr Clear the buffer. ( RXFRMCTR.RX_BUF_CLR) Figure3-1 Reception Sequence After reading of received frames is completed, clear the RX frame buffer. Interrupts used in frame reception are 3 types of reception start, reception complete, and reception failure. The content of the interrupt can be checked using the INTEVENT register. RegisterName Address RW Default INTEVENT 003h R 0000h Validation bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 UNLOCK BUFEMP DETPRE SSLOT INACT CAPEND BKOFF MISC bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 BEALOS GTS BEACON TXFAIL TXEND RXFAIL RXEND RXST 13 AP-MN87400_

14 3.2 Reception Start Interrupt The detection of SFD code of frame after preamble detection generates a reception start interrupt. This is performed to notify the microcontroller that reception processing has started. However, if the microcontroller does not relate to the processing, this interrupt may not be used. Because PHR is received following SFD code, by reading PHR using this interrupt, you can check the length of the frame receiving. In this case, the reading should be performed after waiting for PHR to be stored in RX frame buffer. The wait time should be set using the microcontroller's timer or other functions based on the calculation from the data rate. 3.3 Reception Complete Interrupt The completion of storing of frame data in RX frame buffer generates a reception complete interrupt. In addition, to avoid data overwriting, the RX_BUF_COND bit is automatically set to Reception Failure Interrupt When reception fails, the data until the error occurs have been stored in RX frame buffer. The source of failure has been stored in RXFAIL_INFO (bit[15:14]) of the STAT_RXFAIL register. RegisterName Address RW Default STAT_RXFAIL 036h R 0000h Validation bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 RXFAIL_INFO[1:0] STAT_CRCERR[13:8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 STAT_CRCERR[7:0] The sources of failure: 00: The frame reception started when the buffer is in busy state (RX_BUF_COND bit = 1). 01: Discarded in MAC header filter ring 10: CRC error has been detected. 11: Carrier lost (PHR specifies invalid length) Even when reception fails, the RX_BUF_COND bit is also set to 1 automatically to avoid data お overwriting. 3.5 Reading Frames from Frame Memory In frame reception, PHR and subsequent data (excluding preamble and SFD) are stored in RX frame buffer as reception frame data. In addition, LQI is stored following MAC frame. While in diversity mode, the reception antenna in information (RXANT) is stored following LQI. 14 AP-MN87400_

15 000h 100h 110h 120h TX frame buffer 1 (256Bytes) ACK(16bytes) RESERVED(16bytes) PHR MHR 0-7bytes 220h 240h TX frame buffer 2 (256Bytes) Reserved(32bytes) RX frame buffer (256Bytes) AUX CoM flag Nonce Payload MAC frame 340h Reserved(64bytes) CRC LQI RXANT 380h 3FFh RFparams(128Bytes) (1024bytes) Figure 3-2 RX Frame Buffer Memory Map In the example of transmission, the following data was sent. ----INFO SFD--- --PHR MACBODY CRC h 00h 09h 09h 72h 00h 09h 00h 00h 11h 22h 33h 00h 00h 00h 00h However, when received, this data has been stored in RX frame buffer as shown below. --PHR MACBODY CRC LQI- -ANT- 00h 09h 00h 00h11h 22h 33h xxh xxh xxh xxh 30h 00h LQI is the RSSI value when preamble is detected. 15 AP-MN87400_

16 3.6 Clearing the Buffer When completing a reception, a buffer clear processing is required independent of whether the result is success or failure. When reception is completed, the RX_BUF_COND bit becomes 1. While the RF_BUF_COND bit is 1, a protection is being applied to avoid overwriting of the data in RX frame buffer due to next frame reception. RegisterName Address RW Default RXFRMCTR 005h RW 0000h Validation bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 RSSI (Read Only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reserved SENSE_ RSSI_ SENSE_ RX_BUF_ RX_BUF_ RESULT REQ REQ CLR COND (Read Only) (Read Only) The microcontroller must clear the RX_BUF_COND bit by writing 1 to the RX_BUF_CLR bit after reading data from RX frame buffer to enable a next frame reception. However, the data in RX frame buffer is not cleared even by writing 1 to the RX_BUF_CLR bit. Next frame received while the RX_BUF_COND bit is 1 is detected as reception failure. 16 AP-MN87400_

17 3.7 Automatic ACK transmission When received frame s FC parts has AR bit=1 and TYPE bits = 001b, 011b or 101b, ACK frame will be generated and transmitted automatically. In this case, the completion interrupt of reception occurs at the time of the completion of ACK transmitting. uc MN87400 The other RX Frame Reception starts. INT ACK Reception is complete. Read the frame. Clear the buffer. ( RXFRMCTR.RX_BUF_CLR) INT MR RX BUFF Clr Figure3-3 Reception Sequence (Automatic ACK transmission) When you use Automatic ACK transmission, write INFO, SFD, PHR, and frame itself of the frame to be sent in the frame memory for ACK frame buff before transmission of frame. ACK frame buffer starts from address 100h. ACK frame s MACBODY length is 3byte. set TYPE of FC part to 010. The example of a frame of ACK ----INFO SFD--- --PHR-- -MACBODY CRC FC h 00h 07h 09h 72h 00h 07h 02h 00h 00h 00h 00h 00h 00h The portion of CRC is automatically calculated by hardware, so no data setting is required. In this example, the portion of CRC is padded with 00h. 17 AP-MN87400_

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