Maintenance/ Discontinued

Transcription

1 For Communications Equipment Digital Signal Processor for Image CODEC Overview The is a high-speed, programmable digital signal processor based on a vector pipeline architecture for image processing applications. It incorporates many features that make it ideal for highly efficient coding and decoding of still and moving pictures in applications involving the transmission, storage, and retrieval of images. Features Flexible support for complex processing by simply rewriting the contents of its internal program Built-in dedicated hardware effective for image CODEC, including Discrete cosine transform (DCT) converter Two-dimensional address generator Architecture that links internal, a generalpurpose arithmetic unit, dedicated arithmetic unit, and other components with a pipeline to better support vector calculations, multiply-and-accumulate, and other key image processing operations ITU-T H.261 coding for the QCIF size ( ) with a decoding rate of 15 frames per second or higher Applications Image-based communications: Moving picture videophones, video conferencing systems, cable television systems, image LANs, remote monitoring systems, etc. Image storage and retrieval: Electronic still cameras, optical disc files, image databases, etc. Multimedia computers

2 For Communications Equipment Pin Assignment SPCLK TEST0 TEST1 DRMODE0 DRMODE1 V SS6 V DD6 XWCS XSRE ST1 ST2 XHLD/RUN XRST XCS XSWE DRMODE2 V SS7 SCLK V DD7 X801 X802 XRESEN1 XRESEN2 XOE1 XOE2 XWE1 XWE2 TEST2 TEST3 V DDH XCAS1 XCAS2 XSIEMP SIRCLK S1 XSOBSY SOWCLK S0 V DD5 V SS5 P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] V DD4 V SS4 D2[15] D2[14] D2[13] D2[12] D2[11] D2[10] D2[9] D2[8] V DD3 V SS3 D2[7] D2[6] D2[5] D2[4] D2[3] D2[2] D2[1] D2[0] V DD2 V SS2 D1[15] D1[14] D1[13] D1[12] D1[11] D1[10] D1[9] D1[8] D1[7] D1[6] V DD1 V SS1 D1[5] D1[4] D1[3] D1[2] D1[1] D1[0] LQFP128-P XRAS1 XRAS2 V SS8 V DD8 A1[0] A1[1] A1[2] A1[3] A1[4] A1[5] A1[6] A1[7] A1[8] A1[9] V SS9 V DD9 A1[10] A1[11] A2[0] A2[1] A2[2] A2[3] A2[4] A2[5] A2[6] A2[7] A2[8] A2[9] V SS10 V DD10 A2[10] A2[11]

3 For Communications Equipment Vector Pipeline Processing Examples P instruction QP instruction Pipeline arithmetic unit Q instruction Pipeline arithmetic unit Pipeline arithmetic unit ADD ADD

4 For Communications Equipment Block Diagram D1 A1 D2 A2 BM1 BM2 DM IRAM, IROM F0 to 15 EALU BM1 1Kwd Program CTL CTL IRAM 2Kwd EALU F 16wd ACC BM2 1Kwd MPY Two-dimensional address generator ( bits) Instruction ( bits) Instruction ( bits) Instruction ( bits) General-purpose registers Arithmetic unit DM 1Kwd DCT DRAM IF FLT SIO PIO SIO PIO MPY Multiplier ACC Accumulator DCT Discrete cosine transform converter FLT Filter SIO Serial interface PIO Parallel interface

5 For Communications Equipment Pin Descriptions Pin No. Symbol I/O Function Description 15 to 24, D1 (15:0) I/O/Z Data bus for data transfers to and from external (EM1) 27 to to 48, A1 (11:0) I/O/Z Address bus for data transfers to and from external (EM1) 51 to XWE1 O/Z External write control output (negative logic) 73 XOE1 O/Z External read control output (negative logic) 77 XBO1 O External cycle bus occupation control output (negative logic) 64 XRAS1 O/Z External row address strobe output (negative logic) 66 XCAS1 O/Z External row address strobe output (negative logic) 75 XRFSEN1 I External refresh enable signal (negative logic) 123 to 128, D2 (15:0) I/O/Z Data bus for data transfers to and from external (EM2) 1, 2, 5 to 12 33, 34, A2 (11:0) O/Z Address bus for data transfers to and from external (EM2) 37 to XWE2 O/Z External write control output (negative logic) 72 XOE2 O/Z External read control output (negative logic) 76 XBO2 O External cycle bus occupation control output (negative logic) 63 XRAS2 O/Z External row address strobe output (negative logic) 65 XCAS2 O/Z External row address strobe output (negative logic) 74 XRFSEN2 I External refresh enable signal (negative logic) 79 SCLK I System clock input 96 SPCLK I Serial port clock input 85 XHLD/RUN I Operational mode transition control input 83 XCS I Chip select input (negative logic) 82 XSWE I write enable input for Hold/Slave mode (negative input) 88 XSRE I read enable input for Hold/Slave mode (negative input) 84 XRST I Reset input (negative input) 87 ST1 O Operating status output 86 ST2 O Operating status output 102 SO O/Z Serial out port data 101 SOWCLK O/Z Serial out port external write enable output 100 XSOBSY I Serial out port external busy input (negative logic) 99 SI I Serial in port data 98 SIRCLK O/Z Serial in port external read enable output 97 XSIEMP I Serial in port external external empty input (negative logic) 105 to 112 PO (7:0) O Parallel out port data bus (PO7 is MSB) 113 to 120 PI (7:0) I Parallel in port data bus (PI7 is MSB) 81, 92, 93 DRMODE(2:0) I External DRAM mode control inputs V dd I Power supply pin 3.3[V] V ddh I Power supply pin 5.0 to V dd [V] V ss I Power supply pin 0 [V]

6 For Communications Equipment Application Circuit Example Double buffer (for input data) Memory (DRAM) Image input Memory (DRAM) (for local retrieval) Memory (DRAM) Program load Port-1 Port-2 Serial port Execution control FIFO Code

7 For Communications Equipment Package Dimensions (Unit: mm) LQFP128-P ± ± (1.25) M SEATING PLANE (1.25) 0.1± ± ± max. 20.0± ±0.1 (1.0) 0.5±0.2 0 to 10

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