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1 TVL SC7 4 AC Specification Product Name Series Part No Package Size Transient Voltage Suppressor TVS Series TVL SC7 4 AC SC7-6L

2 TVL SC7 4 AC Engineering Specification 1. Scope TVL SC7 4 AC s are TVS arrays designed to protect high-speed signal lines from overvoltage hazard of Electrostatic Discharge (ESD), Electrical Fast Transients (EFT) and Lightning. These interfaces can be used for USB. power and data lines protection, notebook and personal computers, monitors and flat panel displays, IEEE 1394 Firewire Ports, etc. TVL SC7 4 AC incorporates a pair of rail-to-rail diodes with low capacitance for each of four I/O channels. Additional Zener diode is employed to minimize the influence of supply voltage. The ESD protection of TVS arrays meets the immunity standard of IEC 61-4-, level 4 (±15kV air, ±8kV contact discharge).. Explanation of Part Number TV L SC7 4 AC (1) () (3) (4) (5) 1. Product Type:TV=TVS Diode. Capacitance Code:L=Low Capacitance 3. Package Size Code 4. Channel Code:4=4 Channels 5. Specialized Specification Code 3. Circuit Diagram /Pin Configuration I/O 4 VDD I/O Circuit Diagram 1 3 I/O 1 GND I/O Pin Configuration SC7-6L (Top View) TVL SC7 4 AC Engineer Specification Version: A5 Page 1 of 6

3 4. Specifications 4.1. ABSOLUTE MAXIMUM RATINGS PARAMETER PARAMETER RATING UNITS Rated Power P 15 W Peak Pulse Current (tp =8/μs) I PP 6.5 A Operating Supply Voltage (VDD-GND) V DC 6 V ESD per IEC (Air) ESD per IEC (Contact) ESD per IEC 61-4-(Air)(VDD-GND) ESD per IEC 61-4-(Contact) (VDD-GND) V ESD V ESD_VDD kv kv Lead Soldering Temperature T SOL 6 (1 sec.) Operating Temperature T OP -55 to 85 Storage Temperature T STO -55 to 15 o C o C o C DC Voltage at any I/O pin V IO (GND.5) to (VDD.5) V 4.. ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Reverse Stand-Off Voltage V RWM Pin 5 to pin, T=5 o C 5 V Reverse Leakage Current Channel Leakage Current Reverse Breakdown Voltage Forward Voltage Clamping Voltage ESD Clamping Voltage I/O ESD Clamping Voltage VDD ESD Dynamic Turn-on Resistance I/O ESD Dynamic Turn-on Resistance VDD Channel Input Capacitance Channel to Channel Input Capacitance Variation of Channel Input Capacitance I Leak V RWM = 5V, T=5 o C, Pin 5 to pin 5 A I CH_Leak V BV V F V CL V clamp_io V clamp_vdd R dynamic_io R dynamic_vd D C IN C CROSS C IN V Pin 5 = 5V, V Pin = V, T=5 o C, V CH = ~ 5V I BV = 1mA, T=5 o C Pin 5 to Pin I F = 15mA, T=5 o C Pin to Pin 5 I PP =5A, tp=8/ s, T=5 o C Any Channel pin to Ground IEC kV, T=5 o C, Contact mode, Any Channel pin to Ground IEC kV, T=5 o C, Contact mode, VDD pin to Ground IEC ~6kV, T=5 o C, Contact mode, Any Channel pin to Ground IEC ~6kV, T=5 o C, Contact mode, VDD pin to Ground V pin5 = 5V, V pin = V, V IN =.5V, f = 1MHz, T=5 o C, Any Channel pin to Ground V pin5 = 5V, V pin = V, V IN =.5V, f = 1MHz, T=5 o C, Between Channel pins V pin5 = 5V, V pin = V, V IN =.5V, f = 1MHz, T=5 o C, Channel_x pin to Ground - Channel_y pin to Ground 1 A 6 9 V.8 1 V V.5 V 9 V pf..14 pf.5.7 pf TVL SC7 4 AC Engineer Specification Version: A5 Page of 6

4 4.3 TYPICAL CHARACTERISTICS % of Rated Power or I PP Power Derating Curve Ambient Temperature, T A ( o C) Clamping Voltage (V) Clamping Voltage vs. Peak Pulse Current I/O pin to GND pin Peak pulse Current (A) Waveform Parameters: tr=8μs td=μs Forward Voltage (V) Input Capacitance (pf) Forward Voltage vs. Forward Current I/O pin to GND pin Peak pulse Current (A) Typical Variation of C IN vs. Temp VDD = 5V, GND = V, V IN =.5V, f = 1MHz, Temperature ( o C) Waveform Parameters: tr=8μs td=μs Input Capacitance (pf) Transmission Line Pulsing (TLP) Current (A) Typical Variation of C IN vs. V IN VDD = 5V, GND = V, f = 1MHz, T=5 o C, Input Voltage (V) Transmission Line Pulsing (TLP) Measurement V_pulse Pulse from a transmission line TLP_I 1ns TLP_V DUT - I/O to GND Transmission Line Pulsing (TLP) Voltage (V) Transmission Line Pulsing (TLP) Current (A) Transmission Line Pulsing (TLP) Measurement V_pulse Pulse from a transmission line TLP_I 1ns TLP_V DUT - VDD to GND Transmission Line Pulsing (TLP) Voltage (V) TVL SC7 4 AC Engineer Specification Version: A5 Page 3 of 6

5 5. LAND LAYOUT Dimensions Index Millimeter Inches A B.9.35 C.65.5 D E.7.8 F.5.98 Notes: This LAND LAYOUT is for reference purposes only. Please consult your manufacturing partners to ensure your company s PCB design guidelines are met. 6. Application information Design Considerations The ESD protection scheme for system I/O connector is shown in the Fig. 1. In Fig. 1, the diodes D1 and D are general used to protect data line from ESD stress pulse. If the power-rail ESD clamping circuit is not placed between VDD and GND rails, the positive pulse ESD current (I ESD1 ) will pass through the ESD current path1. Thus, the ESD clamping voltage V CL of data line can be described as follow: V CL = Fwd voltage drop of D1 supply voltage of VDD rail L 1 d(i ESD1 )/dt L d(i ESD1 )/dt Where L 1 is the parasitic inductance of data line, and L is the parasitic inductance of VDD rail. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61-4- standard results in a current pulse that rises from zero to 3A in 1ns. Here d(i ESD1 )/dt can be approximated by ΔI ESD1 /Δt, or 3/(1x1-9). So just 1nH of total parasitic inductance (L 1 and L combined) will lead to over 3V increment in V CL! Besides, the ESD pulse current which is directed into the VDD rail may potentially damage any components that are attached to that rail. Moreover, it is common for the forward voltage drop of discrete diodes to exceed the damage threshold of the protected IC. This is due to the relatively small junction area of typical discrete components. Of course, the discrete diode is also possible to be destroyed due to its power dissipation capability is exceeded. TVL SC7 4 AC Engineer Specification Version: A5 Page 4 of 6

6 The TVL SC7 4 AC has an integrated power-rail ESD clamped circuit between VDD and GND rails. It can successfully overcome previous disadvantages. During an ESD event, the positive ESD pulse current (I ESD ) will be directed through the integrated power-rail ESD clamped circuit to GND rail (ESD current path). The clamping voltage V CL on the data line is small and protected IC will not be damaged because power-rail ESD clamped circuit offer a low impedance path to discharge ESD pulse current. power-rail ESD clamp ing circuit TVL SC7 4 AC L VDDrail Vp _ I ESD D1 D L 1 I ESD1 data line VESD V C _ Protected IC GND rail ESD current path 1 (I ESD1 ) ESD current path (I ESD ) Fig. 1 Application of positive ESD pulse between data line and GND rail. 7. MARKING CODE Marking Code: C7XY C15X S15X C7XY C7 = Device Code X = Date Code Y = Control Code TVL SC7 4 AC Engineer Specification Version: A5 Page 5 of 6

7 8. Mechanical Details SC7-6L PACKAGE DIAGRAMS PACKAGE DIMENSIONS Symbol Milimeters MIN. MAX. A A1..1 A b.15.4 C.8.15 D 1.9. E E1..45 e.65 BSC e1 1.3 BSC L.55 REF L L. REF θ 8 TVL SC7 4 AC Engineer Specification Version: A5 Page 6 of 6