0534S PESDR0534S2. 4-Line Low Capacitance TVS Diode Array. Mechanical Characteristics. Description. Applications. Features. Marking Information

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1 4-Line Low Capacitance TVS Diode Array Description The is a low capacitance TVS arrays, utilizing leading monolithic silicon technology to provide fast response time and low ESD clamping voltage, making this device an ideal solution for protecting voltage sensitive high-speed data lines. The complies with the IEC (ESD) standard with ±15kV air and ±8kV contact discharge. It is assembled into a 6-Pin lead-free SOT23-6 package. The leads are finished with lead-free matte tin. Each device will protect up to four high-speed lines. The combination of small size, low capacitance and high surge capability makes them ideal for use in applications such as Ethernet, USB2., and video interfaces. Features Low capacitance:.8pf typical (I/O to I/O) Ultra low leakage: na level Low operating voltage: 5V Low clamping voltage Up to 4 lines and one power line protects Complies with following standards: IEC (ESD) immunity test Air discharge: ±3kV Contact discharge: ±25kV IEC (EFT) 4A (5/5ns) IEC (Lightning) 6A (8/2µs) RoHS Compliant Dimensions and Pin Configuration Mechanical Characteristics Package: SOT23-6 Lead Finish: Matte Tin Case Material: Green Molding Compound UL Flammability Classification Rating 94V- Moisture Sensitivity: Level 3 per J-STD-2 Terminal Connections: See Diagram Below Marking Information: See Below Applications USB 2. power and data line Monitors and flat panel displays Set-top box and digital TV Digital video interface (DVI) Notebook Computers SIM Ports Gigabit Ethernet IEEE 1394 firewire ports Marking Information 534S 534S = Device Marking Code Dot denotes Pin1 Ordering Information Part Number Packaging Reel Size 3/Tape & Reel 7 inch Circuit and Pin Schematic Copyright 214 PN-Silicon Co., Ltd 1 / 6

2 Absolute Maximum Ratings (TA=25 C unless otherwise specified) Parameter Symbol Value Unit Peak Pulse Power (8/2µs) Ppk 15 W Peak Pulse Current (8/2µs) I PP 6 A ESD per IEC (Air) V ESD ESD per IEC (Contact) ±25 ±3 kv Operating Temperature Range T J 55 to +125 C Storage Temperature Range Tstg 55 to +15 C Electrical Characteristics (T A =25 C unless otherwise specified) Parameter Symbol Min Typ Max Unit Test Condition Reverse Working Voltage V RWM 5 V Any I/O pin to ground Breakdown Voltage V BR 6 V I T = 1mA, any I/O pin to ground Reverse Leakage Current I R.5 µa V RWM = 5V, any I/O pin to ground Clamping Voltage V C 12 V Clamping Voltage V C 25 V Junction Capacitance C J.8 pf Junction Capacitance C J 1.6 pf Note 1: I/O pins are Pin 1, 3, 4 and 6 I PP = 1A (8 x 2µs pulse), any I/O pin to ground I PP = 5A (8 x 2µs pulse), any I/O pin to ground V R = V, f = 1MHz, between I/O pins V R = V, f = 1MHz, any I/O pin to ground Copyright 214 PN-Silicon Co., Ltd 2 / 6

3 Typical Performance Characteristics (T A =25 C unless otherwise Specified) 2. 1 Junction Capacitance_Cj (pf) Peak Power_Ppp(W) Reverse Voltage_V R (V) Pulse Duration_tp(uS) Junction Capacitance vs. Reverse Voltage Peak Pulse Power vs. Pulse Time Clamping Voltage_VC (V) % of Rated Power Peak Pulse Current_Ipp (A) Clamping Voltage vs. Peak Pulse Current Ambient Temperature_Ta( ) Power Derating Curve 11 1 % of Peak Pulse Current CH1 5.V M 1.ns Time_t(μS) ESD Clamping Voltage 8 X 2uS Pulse Waveform 8 kv Contact per IEC Copyright 214 PN-Silicon Co., Ltd 3 / 6

4 Typical Application The is designed to protect four data lines from transient over-voltages by clamping them to fixed reference. When the voltage on the protected line exceeds the reference voltage (plus diode VF) the steering diodes are for ward biased, conducting the transient current away from the sensitive circuitry. Data lines are connected at pins 1, 3, 4 and 6. The negative reference (REF1) is connected at pin 2. This pin should be connected directly to a ground plane on the board for best results. The path length is kept as short as possible to minimize parasitic inductance. The positive reference (REF2) is connected at pin 5. I/O 1 I/O 2 To Protected IC V CC 3 4 I/O 3 I/O 4 To Protected IC on Digital Visual Interface (DVI) Application Copyright 214 PN-Silicon Co., Ltd 4 / 6

5 on USB Port Application USB Port USB Port on SIM Port Application I/O Clock Reset SIM Vcc GND Copyright 214 PN-Silicon Co., Ltd 5 / 6

6 SOT23-6 Package Outline Drawing D f DIMENSIONS SYM MILLIMETERS INCHES E E1 MIN NOM MAX MIN NOM MAX A A e1 A e D E 2.8 BSC.11 BSC A1 E e 1.9 BSC.75 BSC A2 A e1.95 BSC.37 BSC f Suggested Land Pattern X SYM MILLIMETERS DIMENSIONS INCHES C C G Z G P Y X.6.24 Y P Z Copyright 214 PN-Silicon Co., Ltd 6 / 6