SuperCam Bias System ICD

Transcription

1 SuperCam Bias System ICD draft 1, 26 January 2006 Overview: The SuperCam bias system builds upon the successful design constructed for DesertSTAR and PoleSTAR. However, in order to realize the power of heterodyne arrays at minimum complexity and cost, a more integrated approach will be adopted. The current bias system(s) are built into 19 inch subrack enclosures. A series of 3U 4 channel LNA, magnet, and SIS control cards are manipulated over a two wire (I2C) bus that is manipulated manually by "bit banging" a standard PC parallel port. Analog signals are multiplexed with dedicated cards to provide a single analog output that is digitized with a generic ISA data acquisition card in the controlling PC. A custom wire wrapped backplane and 96 pin eurocard connectors provide interconnectivity between cards and for analog multiplexing. Roadmap: In order to support ~100 pixel arrays, an additional degree of integration is needed. We have broken down the development path into several finite projects: 1: Combining the magnet and SIS card designs into a single 3U board, based upon the current SIS board. This eliminates the specialized dual magnet driver and controller boards. Shane Bussmann (AZ) is developing this board for lab testing. 2: The current monitoring system is noisy. We are looking to replace the current full fledged PC control system with an embedded ARM based system using the PC104 bus. This moves the digitization stage closer to the bias system and eliminate a noisy PC environment (w/ video boards,hard drives, complex processors, etc.). The TS 7200 from Technologic Systems, runs the NetBSD operating system and runs with 2W of power. An image of the board itself is shown below. Craig Kulesa is evaluating the board and rewriting the SORAL receiver control software into a client server architecture.

2 3: The next two enhancements will occur in parallel. Robert Stickney will evaluate a standalone ADC board that can serve to replace the PC or embedded ARM digitization stage. The second design stage will condense 8 channels of LNA, magnet and SIS, coupled with all necessary analog multiplexing, onto a single long 6U board. Surface mount components make this consolidation possible. Robert is handling the board design and layout. 4: Depending upon the success of the embedded ARM and standalone digitizers, we will choose either the PC, embedded ARM, or standalone ADC for instrument monitoring. If the standalone digitizer is chosen, it will be integrated onto the back of the 6U analog board. Multiple ground planes will provide necessary shielding and separation of the digital and analog components.

3 System Description: A block diagram of the bias system is shown below. A short summary of each component follows. A detailed schematic of each of these components, developed by Robert Stickney, is available on the SuperCam web site. Digital control of the bias system for the baseline system provided by an embedded computer as described in the roadmap (above). It provides a thin TCP/IP server architecture with which a GUI client can be connected via ethernet. It provides sufficient digital I/O for signals provided over a VME J1 bus to the 8 channel Universal Bias Cards (UBCs). The J1 bus will also supply +/ 15V analog power and ground, and +5V digital power and ground. Other analog voltages (such as +/ 5 and 2.5V) will be generated from +/ 15V analog power on the card itself (i.e. in situ). Digital signals from the computer include a 1 wire bias line, 2 lines each for SPI and I 2 C buses, and 8 lines for card select (CS). Each UBC card will have a unique DIP switched address which is compared to the CS address. If the two match, the CS circuit will enable the I 2 C and SPI buses for that card. All digital buses are opto isolated from the controlling computer.

4 The 1 wire bus is used to provide a unique 48 bit ID that can be used to identify a specific board, and verify that it is located in the proper slot. It will also be used to provide thermal sensors for the bias electronics. The SPI bus is specifically used for the Caltech MMIC LNA bias circuitry. The I 2 C bus is used for the biasing of all magnet and SIS channels, the SIS constant V/R mode switches, and for control of the analog multiplexers. The interface to the SIS mode switches and the analog multiplexers is diagrammed above. I 2 C control of Philips bit I/O expanders provides control over 16 SIS mode switches. The full complement of mode switches may be used when the 16 bias channels are all populated for S IS operation. SuperCam however will populate the boards with 8 SIS and 8 Magnet channels, thus only 8 of the SIS mode switches will be used.

5 An additional Philips I/O expander is used to provide the 8 bits of digital I/O needed to control the four Maxim channel analog multiplexers on each board. The first 4 bits are used to enable each of the four MUX chips. In normal operation, the Card Select itself will enable all four multiplexers. The remaining 4 bits are used to select which of the 16 channels of multiplexed inputs are to be switched to the analog output. Thus, 4 analog outputs are simultaneously enabled, generally allowing monitoring of both I sense and V sense for two SIS channels at a time (or the gate/drain currents and voltages for a single MMIC LNA). These analog outputs will be read by a suite of ADCs yet to be determined. As per the Bias System Roadmap, this will either be the ADC'son the embedded computer, a standalone ADC board controlled by a PIC or the embedded computer, or a digitizer integrated onto the bias board itself.

6 List of Major IC Components: VME bus assignments: Power Supplies: Card Layout and Enclosure: SIS Preamp integration: Wiring Harness Block Diagram: