LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

Transcription

1 S597T LOW SKEW CMOS PLL CLOCK IVE WITH INTEGATE LOOP FILTE LOW SKEW CMOS PLL CLOCK IVE WITH INTEGATE LOOP FILTE S597T FEATUES: 5V operation 2x output, /2 output, output Outputs tri-state while ST low Internal loop filter C network Low noise TTL level outputs < 500ps output skew, 0-4 PLL disable feature for low frequency testing Balanced rive Outputs ± 24mA 32MHz maximum frequency (2x output) Functional equivalent to Motorola MC8895 ES > 2000V Latch-up > 300mA Available in SOP and PLCC packages ESCIPTION The S597T Clock river uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 0-4, 2x, /2, 5. Careful layout and design insures < 500ps skew between the 0-4, and /2 outputs. The S597T includes an internal C filter which provides excellent jitter characteristics and eliminates the need for external components. In addition, TTL level outputs reduce clock signal noise. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The VCO can also be disabled by the PLL_EN signal to allow low frequency or C testing. The LOCK output asserts to indicate when phase lock has been achieved. The S597T is designed for use in high-performance workstations, multi-board computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. For more information on PLL clock driver products, see Application Note AN-227. FUNCTIONAL BLOCK IAGAM EF_SEL LOCK FEEBACK PLL_EN FE_SEL ST SYNC0 SYNC 0 PHASE ETECTO LOOP FILTE VCO 0 /2 0 / x The IT logo is a registered trademark of Integrated evice Technology, Inc. SEPTEMBE Integrated evice Technology, Inc. SC-5227/4

2 S597T LOW SKEW CMOS PLL CLOCK IVE WITH INTEGATE LOOP FILTE PIN CONFIGUATION ST 5 4 2x ST x /2 FEEBACK /2 FEEBACK 5 24 EF_SEL 6 24 EF_SEL SYNC SYNC A 8 22 A NC A SYNC LOCK PLL_EN NC A SYNC LOCK FE_SEL FE_SEL 0 PLL_EN SOP TOP VIEW PLCC TOP VIEW ABSOLUTE MAXIMUM ATINGS () Symbol ating Max Unit Supply Voltage to Ground 0.5 to +7 V C Input Voltage VIN 0.5 to +7 V AC Input Voltage (pulse width 20ns) 3 V Maximum Power issipation (TA = 85 C).2 W TSTG Storage Temperature ange 65 to +50 C. Stresses greater than those listed under ABSOLUTE MAXIMUM ATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = +25 C, f =.0MHz, VIN = 0V) SOP PLCC Parameter Typ. Max. Typ. Max. Unit CIN pf COUT pf 2

3 S597T LOW SKEW CMOS PLL CLOCK IVE WITH INTEGATE LOOP FILTE PIN ESCIPTION Pin Names I/O escription SYNC0 I eference clock input SYNC I eference clock input EF_SEL I eference clock select. When, selects SYNC. When 0, selects SYNC0. FE_SEL I VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency. FEEBACK I PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different output frequency relationships. See the Frequency Selection Table for more information. 0-4 O Clock outputs 5 O Clock output. Matched in frequency, but inverted with respect to. 2x O Clock output. Matched in phase, but frequency is double the frequency. /2 O Clock output. Matched in phase, but frequency is half the frequency. LOCK O PLL lock indication signal. indicates positive lock. 0 indicates that the PLL is not locked and outputs may not be synchronized to the inputs. ST I Asynchronous reset. esets all output registers. When 0, all outputs are held in a tri-stated condition. When, outputs are enabled (normal operation). PLL_EN I PLL enable. When, PLL is enabled (normal operation). When 0, PLL is disabled (for testing purposes). N C No Connection OUTPUT FEUENCY SPECIFICATIONS Industrial: TA = 40 C to +85 C, A/ = 5V ± 5% Symbol escription Units F2X Max Frequency, 2x output MHz F Max Frequency, 0-4, 5 outputs MHz F/2 Max Frequency, /2 output MHz 3

4 S597T LOW SKEW CMOS PLL CLOCK IVE WITH INTEGATE LOOP FILTE FEUENCY SELECTION TABLE SYNC (MHz) Output Used for (allowable range) Output Frequency elationships FE_SEL Feedback Min. Max /2 5 Outputs 2X /2 4 F2X / 4 SYNC SYNC X 2 SYNC X 2 SYNC X F2X / 2 SYNC / 2 SYNC SYNC SYNC X F2X / 2 SYNC / 2 SYNC SYNC SYNC X 2 2x 56 F2X () SYNC / 4 SYNC / 2 SYNC / 2 SYNC 0 /2 7 F2X / 8 SYNC SYNC X 2 SYNC X 2 SYNC X F2X / 4 SYNC / 2 SYNC SYNC SYNC X F2X / 4 SYNC / 2 SYNC SYNC SYNC X 2 0 2x 28 F2X / 2 SYNC / 4 SYNC / 2 SYNC / 2 SYNC. For the 32 speed grade, maximum input frequency is restricted to 00MHz. C ELECTICAL CHAACTEISTICS OVE OPEATING ANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = 40 C to +85 C, A/ = 5V ± 5% Symbol Parameter Test Conditions Min. Typ. Max. Unit VIH Input HIGH Voltage Level Guaranteed Logic HIGH level 2 V VIL Input LOW Voltage Level Guaranteed Logic LOW level 0.9 V VOH Output HIGH Voltage = Min., IOH = 24mA () 2.4 V = Min., IOH = 00μA 3 VOL Output LOW Voltage = Min., IOL = 24mA () 0.55 V = Min., IOL = 00μA 0.2 IOZ Output Leakage Current VOUT = or, = Max. ±5 μa IIN Input Leakage Current VIN = A or, A = Max. ±5 μa. IOL and IOH are 2mA and 2mA, respectively, for the LOCK output. POWE SUPPLY CHAACTEISTICS Symbol Parameter Test Conditions () Typ. Max. Unit ΔICC Input Power Supply Current per TTL Input HIGH (2) = Max., VIN = 3.4V ma ICC ynamic Power Supply Current = Max 0.4 ma/mhz NOTES:. For conditions shown as Min. or Max., use the appropriate values specified under C Electrical Characteristics. 2. This specification does not apply to the PLL_EN input. 4

5 S597T LOW SKEW CMOS PLL CLOCK IVE WITH INTEGATE LOOP FILTE INPUT TIMING EUIEMENTS Symbol escription Min. Max. Unit t, tf Maximum input rise and fall times, 0.8V to 2V 3 ns FI Input Clock Frequency, SYNC0, SYNC () 4 F2X MHz tpwc Input clock pulse, HIGH or LOW 2 ns H uty cycle, SYNC0, SYNC %. The FI specification is based on output feedback. See the Frequency Selection Table for more detail on allowable SYNC input frequencies for different feedback combinations. SWITCHING CHAACTEISTICS () Symbol Parameter Min. Max. Unit tsk Output Skew Between ising Edges, 0-4 and /2 () 350 ps tskf Output Skew Between Falling Edges, 0-4 () 350 ps tskall Output Skew, All Outputs () 500 ps tpw Pulse Width, 5, 2x outputs TCY/ TCY/ ns tpw Pulse Width, 0-4, /2 outputs () TCY/2 0.5 TCY/ ns tj Cycle-to-Cycle Jitter, 33MHz (3) 0.25 ns tp SYNC Input to Feedback elay, 28MHz ps tp SYNC Input to Feedback elay, 33MHz, 50Ω to.5v ps tlock SYNC to Phase Lock 0 ms tpzh Output Enable Time, ST LOW to HIGH (2) 0 7 ns tpzl tphz Output isable Time, ST HIGH to LOW (2) 0 6 ns tplz t, tf Output ise/fall Times, 0.8V to 2V ns NOTES:. Skew specifications apply under identical environments (loading, temperature,, device speed grade). 2. Measured in open loop mode PLL_EN = Jitter is characterized using an oscilloscope. Measurement is taken one cycle after jitter. Jitter is characterized but not tested. See FEUENCY SELECTION TABLE for information on proper FE_SEL level for specified input frequencies. 5

6 S597T LOW SKEW CMOS PLL CLOCK IVE WITH INTEGATE LOOP FILTE TEST LOA 60Ω 300Ω 7.0V OUTPUT OUTPUT 68Ω 20pF 30pF 300Ω TEST CICUIT TEST CICUIT 2 TEST CICUIT 2 is used for output enable/disable parameters. TEST CICUIT is used for all other timing parameters. PLL OPEATION The Phase Locked Loop (PLL) circuit included in the S597T provides for replication of incoming SYNC clock signals. Any manipulation of that signal, such as frequency multiplying or inversion is performed by digital logic following the PLL (see the block diagram). The key advantage of the PLL circuit is to provide an effective zero propagation delay between the output and input signals. In fact, adding delay circuits in the feedback path, propagation delay can even be negative! A simplified schematic of the S597T PLL circuit is shown below. SIMPLIFIE IAGAM OF S597T FEEBACK 2x /2 INPUT VCO /2 /2 PHASE ETECTO The phase difference between the output and the input frequencies feeds the VCO which drives the outputs. Whichever output is fed back, it will stabilize at the same frequency as the input. Hence, this is a true negative feedback closed loop system. In most applications, the output will optimally have zero phase shift with respect to the input. In fact, the internal loop filter on the S597T typically provides within 50ps of phase shift between input and output. If the user wishes to vary the phase difference (typically to compensate for backplane delays), this is most easily accomplished by adding delay circuits to the feedback path. The respective output used for feedback will be advanced by the amount of delay in the feedback path. All other outputs will retain their proper relationships to that output. 6

7 S597T LOW SKEW CMOS PLL CLOCK IVE WITH INTEGATE LOOP FILTE OEING INFOMATION S XXXX evice Type XX Speed X Package X Process Blank Industrial (-40 C to +85 C) G J JG -70T -00T -32T uarter Size Outline Package SOP - Green Plastic Leaded Chip Carrier PLCC - Green 70MHz Max. Frequency 00MHz Max. Frequency 32MHz Max. Frequency 597T Low Skew CMOS PLL Clock river with Integrated Loop Filter COPOATE HEAUATES for SALES: for Tech Support: 6024 Silver Creek Valley oad or logichelp@idt.com San Jose, CA 9538 fax: