CB-50 Development board for the Spark-100 Product Brief

Transcription

1 CB-50 Development board for the Spark-100 Version 1.0 Product Brief

2 Contents 1 Scope Overview Top view Bottom view Ordering options Detailed description Block diagram Power FPGA - Power level Configuration CB50 interfaces JTAG/Byte Blaster UART (Debug) port I2C Interface Ethernet Interfaces USB Ports Micro-SD interface VGA and Audio interfaces HPS extender connector HSMC Push Buttons and LEDs CB-50 Product brief 1.0

3 1 Scope The following document provides a description of the CB-50 evaluation board. Note that some of the components mentioned in the document are optional and will not be available in all variations of the CB Overview The CB-50 is a fully featured development and carrier board for ShiraTech s Spark-100 System on Modules (SOM). The CB-50 offers extensive connectivity to both HPS and FPGA along with an HSMC slot for supporting various expansion cards available from Altera. The board can be used by FPGA and software teams as a development platform offering all relevant peripherals for simulating the target product functionalities. The CB-50 is provided with a build in Software located on the internal emmc of the Spark module for quick development start up along with sample FPGA firmware for the available interfaces. The CB-50 has two flavors basic and full, the following list details the feature available for each option. Features: Supports SPARK-100 SX and SPARK-100 SE. One (Basic) or three (Full) GE interfaces. One USB OTG or two USB Host interfaces. RS-232 to USB convertor, Micro USB connector Micro-SD card slot VGA interface (24 Bits). Line-in, Line-out and Mic-in audio interface. Full HSMC interface supporting Altera compatible modules. 50 pins expansion connector including: o Two CAN interfaces, one digital and one analog. o Two I2C interfaces. o Two SPI Interfaces. o GPIOs USB Byte Blaster interface (Full). Battery supported RTC module (Full) JTAG interface. 12 volts input power. 3 CB-50 Product brief 1.0

4 2.1 Top view 2.2 Bottom view SD card slot 4 CB-50 Product brief 1.0

5 2.3 Ordering options The CB-50 has two ordering options: Full version CB-50-BB Basic configuration CB-50-B0 Feature Full Version Basic Version HSMC + + (1) USB OTG (2) x USB Host (2) + + Giga Ethernet (HPS) + + VGA + + Audio + + Debug, J Push Button & LED + + Giga Ethernet (FPGA) + - Integrated USB Blaster + - Real Time Clock + - Notes: 1) Some of the clock inputs to the HSMC module are generated by the clock generator of the SPARK The clock generator is available only on the SPARK-100 SX option. 2) USB OTG and the USB Host ports cannot operate simultaneously. 3) The CB-50 basic can be ordered with either SX or SE based module while the CB-50 full version can be ordered only with SX modules. 5 CB-50 Product brief 1.0

6 3 Detailed description 3.1 Block diagram JTAG uusb Byte Blaster JTAG BB Cold/Warm Reset HPS usd [0..3] 10/100/1000BT usd MAG PWR Select Push Button 0,1 USB OTG USB SW USB Host A USB Host B uusb Dual USB UART RS232 to USB FTDI uusb CAN 0 CAN PHY CAN 1 SPI 0 SPI 1 Debug I2C0_0 I2C0_3 I2C SW I2C0_2 Current Measurment RTC I2C0_1 Byte Blaster USB Push Button 2,3 Bank 5A Bank 4A I2S (Audio) 24 RGB (Video) Audio CODEC VGA D/A Line IN Line OUT MIC VGA Ser/Des 0 (GE) Ser/Des 3 (GE) Dual GE PHY MAG FPGA Bank 3A 3B 4A Differential Pairs Ser/Des 1, 2, 4, 5 I2C0_1 HSMC Clocks Figure 1 - CB-50 Block diagram 6 CB-50 Product brief 1.0

7 3.2 Power The CB-50 is powered by a 12 volts power supply. The power input is controlled by a mechanical switch (ON/OFF) and a power switch that controls the power ramp and limits the output current to 4A. The following figure describes the power architecture: Vin 12V 12V Board 5V Board CB-50 Module Power Switch TPS2592AL (4A) 5V 6A EN2360QI Power meter 5V SPARK 100 ON/OFF 5v Board 3.3V 0.6A EP5358HQI 3.3V Board 1.8V 0.6A EP5358HQI 1.8V Board 2.5V 0.6A EP5358HQI 1V 1A EP53A8LQI Vitesse VSC8552 (Dual-PHY) 3.3V 4A EN V HSMC CB-50 HSMC 12V HSMC Figure 1 CB-50 Power The TPS2592AL is TI's power switch that controls the CB-50 input power ramp and limits the current to 4A. The mechanical switch controls the power switch ON/OFF state (Chip Enable). The input 12 volt power is connected to Enpirion's 12V to 5V converter (EN2360QI) supporting up to 6A. The 5V output feeds all other DC to DC converters and its POK signal enables their outputs. The CB-50 power domains are: SPARK-100 domain drives the SPARK-100 power. This power is monitored by a power meter to measure the SPARK-100 power, and can be read by software. CB-50 domain is powered directly from the 5V power source, all other power derived from the 5V source using Enpirion's DC to DC converters (3.3V and 1.8V). This power domain includes the CB-50 peripherals. Giga Ethernet power domain includes Vitesse dual ports GE PHY. The 5V is converted to 2.5V and 1V levels required for the Vitesse operation. 7 CB-50 Product brief 1.0

8 HSMC power domain is used to power modules connected to the HSMC connector. The 12V power is connected directly to the power switch output and the 3.3V is derived from a DC to DC converter and can drive up to 4A. Note before connecting an HSMC module, it is recommended to check its power consumption and to see that the CB-50 can provide it FPGA - Power level Configuration When using the SPARK-100 on the CB-50 the IO power of banks 3B and 4A are set by the dip-switch (SW-2) located on the CB-50. The power level of banks 3B and 4A can be set according to the design requirements. Each bank in the FPGA has a VCCPD and a VCCIO that sets the banks interface power. Banks 3B and 4A share a single VCCPD (FPGA architecture) while each bank has its own VCCIO. This put limitation to the banks I/O power setting. The following table describes the various possibilities: VCCPD Bank 3B Bank 4A Set to 3.3V 3.3V only 3.3V only Set to 2.5V 1.5V, 2.5V or 1.8V 1.5V, 2.5V or 1.8V The power options are set by dip switches on the CB-50 board. There is a single switch that sets the VCCPD power for both banks and two switches that set the power of the VCCIO for each bank. Figure 3 describes a configuration where the VCCPD is set to 3.3V, in this case the VCCIO for both banks need to be configured to 3.3V (FPGA architecture). ON Programmable VCCPD Bank 3B, 4A 2.5V, 3.3V 0.6A MUST ON 3.3 V Programmable VCCIO Bank 3B V, 1.8V, 2.5V, 3.3V 0.6A Only 3.3 V ON MUST Programmable VCCIO Bank 4A 1.5V, 1.8V, 2.5V, 3.3V 0.6A Only 3.3 V Figure 3 - Bank 3B and 4A VCCPD is 3.3V 8 CB-50 Product brief 1.0

9 The following figures describe power schemes where the VCCPD is set to 2.5V. When the VCCPD is set to 2.5V, each I/O can be separately set to1.5v, 1.8V or 2.5V. Figure 4 describe a two configuration where the VCCPD is set to 2.5V. In the top Bank 3B's VCCIO is set to 2.5V and Bank 4A's VCCIO is set to 1.8V. In the bottom configuration Bank 3B's VCCIO is set to 1.8V and Bank 4A's VCCIO is set to 1.5V. ON Programmable VCCPD Bank 3B, 4A 2.5V, 3.3V 0.6A 2.5 V ON Programmable VCCIO Bank 3B 1.5V, 1.8V, 2.5V, 3.3V 0.6A 1.8 V Programmable VCCIO Bank 3B 1.5V, 1.8V, 2.5V, 3.3V 0.6A 1.5 V ON Programmable VCCIO Bank 3B 1.5V, 1.8V, 2.5V, 3.3V 0.6A 2.5 V ON Programmable VCCIO Bank 4A 1.5V, 1.8V, 2.5V, 3.3V 0.6A 1.8 V Figure 4 - Bank 3B and 4A VCCPD is 2.5V Configuring the power is done by a programmable DC-to-DC chip (1.8V, 2.5V and 3.3V) or switching between power sources (1.5V). The following figure describes the power switching. 9 CB-50 Product brief 1.0

10 DC to DC 3.3, 2.5, 1.8V Power Switch ON Programmable VCCIO Bank 3B 1.5V, 1.8V, 2.5V, 3.3V 0.6A VCCIO Bank 3B 1.5V FPGA ON Power Switch DC to DC 3.3, 2.5, 1.8V Power Switch ON Programmable VCCIO Bank 4A 1.5V, 1.8V, 2.5V, 3.3V 0.6A VCCIO Bank 4A 1.5V FPGA ON Power Switch Figure 5 - Bank 3B/4A Power Switching Bank3B and Bank4A can support a DDR3 interface assembled on the carrier board. The signals are available through the SMARC connector. Since the CB-50 doesn't support DDR3 interface on the FPGA those pins are shorten to GND. 10 CB-50 Product brief 1.0

11 3.3 CB50 interfaces The CB-20 offers a large variety of interfaces for supporting a large variety of applications. The following table provides the available interfaces and their mapping to the various interfaces and the internal ports of the processor. Interface name Processor interface Remarks Byte blaster J10 Byte blaster over USB USB OTG J-11 USB1 USB 2.0 Host/Device USB host port 1 J-13 USB1 USB 2.0 A Host Interface from USB HUB USB host port 2 J-13 USB1 USB 2.0 A Host Interface from USB HUB Audio interface 1 J-17 FPGA Line Out Audio interface 2 J-14 FPGA Line in Audio interface 3 J-16 FPGA MIC in Giga Ethernet port J-19 GMAC 0 From HPS Giga Ethernet port 1 J-20 FPGA From FPGA Giga Ethernet port 2 J-21 FPGA From FPGA VGA interface J-18 FPGA HSMC interface J-1 HPS Extender J-12 Various 50 pins 2.54 Header JTAG interface J-7 10 pins 2.54 Header Power inlet J-6 Power Jack, 12 Volt Table 1 External interfaces * The interfaces in blue are available only in the full version. The following paragraphs provide detailed description of each of the available interfaces. 11 CB-50 Product brief 1.0

12 3.3.1 JTAG/Byte Blaster The CB-50 enables the use of an integrated USB Blaster (Full version) or an external Byte Blaster (Full or Basic versions). To enable the JTAG or Byte Blaster interface on the CB-50, Dip-Switch SW3-2 on the Spark need to be set to "ON". The following figure describes the CB-50 JTAG connection to the SPARK-100. The integrated USB Blaster is emulated by Cypress MPU and an Altera CPLD device. The code for the MPU and CPLD is preconfigured in the CB-50. The connector used is Micro-USB connector. The JTAG connector is a 10 pins connector enables JTAG card testing or Byte Blaster programming. Note: An external USB byte Blaster can be ordered either from Shiratech or from a 3 rd party. CB-50 Module J1 TDO HPS TDI TDO Analog Switch TS3A5015 J7 Disable 2 1 JTAG_I/O Analog Switch TS3A5015 JTAG (CB-50) I/O (SMARC) FPGA TDI TDO SW 3,1 J10 uusb Cypress CY7C68013A MAXII EPM570GF 100 SW 3,2 Figure 6 - JTAG/Byte Blaster JTAG/Byte Blaster J7 specifications The JTAG connector is a 10(2x5) pins header with a 2.54 mm pitch with the following pin out: Signal Pin Pin Signal TCK 1 2 USB Disable TDI V TMS 5 6 Warm reset NC 7 8 NC TDO 9 10 GND USB Disable signal on pin 2 disables the integrated USB Byte Blaster operation when an external Byte Blaster cable is used. 12 CB-50 Product brief 1.0

13 DEBUG / Cont rol PO RT Micro USB Type A/B 7 6 SHD VBUS GND DM DP ID 3 AGND USB to RS GND 17 PAD TX Data RX Data UART (Debug) port The Spark-100 debug UART is connected to a Micro-USB Type-A/B connector through an RS-232 to USB convertor. It enables debugging the SOM using a standard Micro USB to USB cable (Provided with the CB-50). The user should run UART emulation over USB when connecting the PC to the carrier board. The CB-50 uses UART0 of the HPS for debug. 1V8 EARTH_USB J EARTH_USB LF VUSB_IN C32 C33 1V8 3V3 R55 R53 R56 100pF 100pF R57 U11 10 VCC 39R 7 USB_DM 39R 6 USB_DP 0R 9 Reset 1 VCCIO 0R 8 3V3OUT TXD 15 RXD 2 RTS 16 CTS 4 12 CBUS0 11 CBUS1 5 CBUS2 14 CBUS3 R61 0R R58 100K HPS_UART0_RX HPS_UART0_TX VUSB_IN R59 10k R60 4.7K C36 100nF FT230X QFN red D9 red D10 470R R54 470R R62 3V3 3V3 Figure 7 CB-50 Debug Option The USB to RS-232 convertor is powered by 3.3V (The USB 5V power is not in use). Its IO interfaces are compatible to 1.8V logic (See FTDI FT-230X data-sheet for more details). The device is preconfigured to support: Two LEDs indicate traffic streaming RX/TX, through the device(d10 and D9). VBUS sense, in case that the host shut its power down the chip gets into suspended mode I2C Interface The CB-50 supports four I2C interfaces. All the interfaces are connected to the SPARK-100 I2C0 interface trough an I2C multiplexer located on the SPARK-100 module. I2C0_0 (I2C_CAM) and I2C0_3 (I2C_LCD) are connected to the HPS extender. I2C0_3 (I2C_GP is connected to the HSMC connector. I2C0_1 (I2C_PM) is connected to the CB-50 peripherals, the current meter and the Real Time Clock. The following figure describes the I2C interfaces: 13 CB-50 Product brief 1.0

14 Module Carrier HPS I2C1 Internal I2C I/O Expander Internal IO1_[0..5] IO1_[0..5] I2C_CAM I2C0_0 Debug J 12 I2C_LCD I2C0_3 I2C0 I2C Expander I2C_GP I2C0_1 HSMC J 1 I2C_PM I2C0_ Current Measurement U 4 RTC U 8 Figure 8 CB-50 I2C Interface 14 CB-50 Product brief 1.0

15 3.3.4 Ethernet Interfaces The CB-50 supports a single Giga Ethernet interface (from the HPS) in its Basic version and three GE in the full version. The Giga Ethernet interfaces are connected to RJ-45 connectors with integrated magnetic. The following figure describes the GE interfaces connections. RGMII 1 Module CB-50 HPS 4 x TX 125 Mhz 4 x RX MDC/MDIO Micrel ksz9031 LEDS MAG J 19 FPGA SGMII (Ser/Des 0) SGMII (Ser/Des 3) MDC/MDIO Vitesse VSC8552 (Dual-PHY) MAG J 20 MAG J 21 Figure 9 - Giga Ethernet Interfaces HPS Giga Ethernet The Giga Ethernet interface is connected to the SoC HPS RGMII1 interface. It uses Micrel's KSZ9031 PHY. The GE port support two LEDs one for Link and the other for Activity FPGA Giga Ethernet (Full version only) There are two Giga Ethernet interfaces (Vitesse's VCS8552 dual GE PHY) connected to the FPGA's Ser/Des. One GE is connected to Ser/Des 0 and the other to Ser/Des 3. The interface protocol running on each Ser/Des is SGMII. There is a single MDC/MDIO interface connected from the FPGA to the external GE PHY. The MDC/MDIO pins are P117 and P118 at the SMARC connector. The FPGA pins are AG24 and AH24 respectively. Each GE interface supports two LEDs one for Link and the other for Activity. 15 CB-50 Product brief 1.0

16 Giga Ethernet J19, J20, J21 pin out 1 Pin Signal Description 1 TX1+ Transmit+ (support 100M) 2 TX1- Transmit- (Support 100M) 3 RX1+ Receive + (Support 100M) 4 TX2+ Transmit+ 5 TX2- Transmit- 6 RX1- Receive + (Support 100M) 7 RX2+ Receive 8 RX2- Receive Case Analog Ground USB Ports The CB-50 supports a single USB-OTG port OR two USB-Host ports. An internal USB switch selects between the two options. The switch is connected via a USB PHY device to USB1 interface of the HPS. The following figure describes the USB interfaces. HPS Data[0..7] Ctrl USB PHY OTG (USB3300) Vcc USB 10K I2C1 IO0_0 USB Switch (USB3740) Port Select USB HUB (USB2422) Module OTG PWR_EN PWR_OCR, VBUS, ID Host PWR_EN PWR_OCR Host PWR_EN PWR_OCR CB-50 USB0 OTG USB Power USB1 USB Power USB2 USB Power uusb J 11 5V 5V 5V Dual USB J 13 Figure 10 - USB Interfaces 16 CB-50 Product brief 1.0

17 Two USB-Host Interfaces The CB-50 default state is two USB Host interfaces. The USB interfaces are connected to the USB HUB on the SPARK-100 module. Each USB interface has its own power source which is controlled by a current limiter (Up to 0.5A). The power limiter controls are Power Enable and Over Current both connected to the HUB control pins USB Host J13 pin out Pin Signal Description A/B1 VBUS 5V out A/B2 DM Data A/B3 DP Data A/B4 GND Digital ground Case Analog Ground USB-OTG Interface The CB-50 USB-OTG interface is enabled by setting the USB port select pin to "0" on the Spark. In this mode the CB-50 Micro-USB connector is connected directly to the USB-OTG PHY. The USB port has its own power source which is controlled by a current limiter (0.5A). The power limiter controls are connected directly to the USB-OTG PHY. There are two additional control signals for OTG support: USB-ID sense if a Host or Device is connected to the USB port. USB-VBUS sense if a power source is connected to the USB interface. Note The CB-50 can support a single USB-OTG or two USB-Host ports. Bot options are not supported simultaneously. 17 CB-50 Product brief 1.0

18 OTG Interface J11 pin out Pin Signal Description 1 VBUS VBUS sense (USB PHY on SPARK-100) 2 DM Data - 3 DP Data + 4 ID ID signal (USB PHY on SPARK-100) 5 GND Digital ground Case Analog Ground Micro-SD interface The CB-50 supports a 4-bits Micro SD card. It is connected to the HPS SDMMC interface. The Micro-SD on the CB-50 and the emmc device on the SPARK-100 share the same SDMMC interface. Selecting between emmc and SD card is done by BSEL0 selector or by software via GPIO 44. The following figure describes the CB-50 SDMMC interface. HPS MMC D[0..3], Ctrl SDIO MUX (TXS02612) D[4..7] D[0..3], Ctrl emmc 4-8GB GPIO44 Select Module Carrier 10K D[0..3], Ctrl BSEL0 1K usd Card J CB-50 Product brief 1.0 Figure 11 - Micro-SD card At power up selecting between the SD card and the emmc is done by BSEL0 jumper on the CB-50. After power up the selection can be override by using GPIO 44 of the HPS.

19 Setting the control signal to "1" enable the SD card. Setting the control signal to "0" enable the emmc device Micro-SD Interface J22 The CB-50 uses Foxconn's micro-sd connector (WQ2182C-DES1-7F). Pin Signal Description 1 MCI0_DA2 Data 0 2 MCI0_DA3 Data 3 3 MCI0_CDA Command line 4 3.3V 3.3v power 5 MCI0_CK Clock. 6 GND Digital ground 7 MCI0_DA0 Data 0 8 MCI0_DA1 Data 1 9 GND Card inserted polarity (Low) 10 MCI0_CD Card detect 11 GND Digital ground 12 GND Digital ground 19 CB-50 Product brief 1.0

20 3.3.7 VGA and Audio interfaces The CB-50 supports a VGA and Audio interfaces. The VGA is based on Analog Devices AD7123 digital to analog converter. It converts 24 RGB bits to the VGA analog signals. The Audio interfaces are based on Analog Devices SSM2603 CODEC. It supports Line-in, Line-out and Mic-in. The following figure describes the CB-50 VGA and Audio interfaces. Module CB V 3.3V 3.3V J 15 FPGA 24 RGB Voltage 24 RGB (3.3V) AD7123 RGB Translator VGA VGA J 18 Bank 4A I2S I2C Audio CODEC SSM2603 Line-IN J 14 Line-OUT J 17 MIC-IN J 16 Figure 12 VGA and Audio Interface The VGA and Audio interfaces are connected to BANK4A of the FPGA. It can support both 1.8V and 3.3V IO voltage configuration (See SPARK-100 voltage configuration). The Audio device can support both power configurations while the VGA interface using a power level translator. The power level is set by J15 selector as 1.8V or 3.3V VGA interface - J18 pin out 20 CB-50 Product brief 1.0 Pin Signal Description 1 VGA_R Analog RED 2 VGA_G Analog GREEN 3 VGA_B Analog BLUE 4, 9,11,12,15 NC 5-8, 10 GND Digital GND 13 VGA_HS Horizontal synchronization signal 14 VGA_VS Vertical synchronization signal

21 Audio Interface J14, J16, J17 The CB-50 support stereo Line out J17, Line in J14 and Mic-in J16. The CB-50 uses SJ HPS extender connector The extender connector is a 50 pins header (J12, 2 x 25, 2.54mm pitch) that supports variety of signals that can be used to interface the SPARK-100. The following signals are supported: Two I2C interface (See I2C interface). Two SPI interfaces with a single chip select. Two FPGA GPIO (GPIO0 and GPIO37). Four HPS GPIn (GPI6, GPI7, GPI8 and GPI9). Five I2C IO expander signals from the SPARK-100. Two CAN interfaces, one analog (3.3V) and one digital (TTL 3.3V). Two clock inputs connected to CLK7N and CLK7P. One clock output connected to Bank5A clockout1 (TX_R22N). Two differential FPGA signal from Bank8A (TX_t4P and TX_T4N). 21 CB-50 Product brief 1.0

22 pin out: Signal Pin Pin Signal 5V 1 2 5V DEBUG_CLKOUT0 3 4 CLK7P GND 5 6 CLK7N IO1_1 7 8 GND IO1_ CAN0H IO1_ CAN0L IO1_ GND IO1_ CAN1_TX GND CAN1_RX SPI0_SS GND SPI0_MISO I2C_CAM_CK SPI0_MOSI I2C_CAM_DAT SPI0_CLK I2C_LCD_CK GND I2C_LCD_DAT SPI1_SS HPS_GPI8 SPI1_MISO HPS_GPI7 SPI1_MOSI HPS_GPI9 SPI1_CLK HPS_GPI6 FPGA_GPIO NC FPGA_GPIO NC NC NC NC NC NC NC TX_T4P NC TX_TPN NC Signal description: I2C Interface I2C_CAM_CK Expansion of I2C0 (See I2C interfaces) I2C_CAM_DAT Expansion of I2C0 (See I2C interfaces) I2C_LCD_CK Expansion of I2C0 (See I2C interfaces) I2C_LCD_DAT Expansion of I2C0 (See I2C interfaces) SPI0 and SPI1 Master Interface from HPS SPI0,1_SPLK SPI clock SPI0,1_MOSI SPI MOSI SPI0,1_MISO SPI MISO SPI0,1_SS0 SPI Chip Select 0 Clocks CLK7P Single differential pair or two single end clock inputs, connected to the FPGA CLKIN7 CLK7N Single differential pair or two single end clock inputs, connected to the FPGA CLKIN7 DEBUG_CLKOUT0 Single end clock outputs, connected to the FPGA BANK5A (Can be used as IO) TX_T4P Single differential pair or two single end clock outputs, connected to the FPGA BANK8A (Can be used as IO) 22 CB-50 Product brief 1.0

23 TX_TPN CAN0H CAN0L CAN1_TX CAN1_RX GPIO0 GPIO37 GPI6-GPI9 IO1_1 IO1 Single differential pair or two single end clock outputs, connected to the FPGA BANK8A (Can be used as IO) CAN Analog CAN interface (3.3V) Analog CAN interface (3.3V) Digital CAN interface (3.3V TTL), Can be used as IO Digital CAN interface (3.3V TTL), Can be used as IO General Purpose I/O Input/output connected to HPS. Input/output connected to HPS. Input only connected to HPS Input/output to I2C IO expander on the SPARK HSMC The CB-50 supports a standard HSMC connector based on Altera's specifications. The HSMC connector supports: Four transceiver pairs (Transmit and receive) connected to the FPGA's Transceivers. Seventeen differential pairs (Transmit and receive) connected to the FPGA Banks 3A, 3B and 4A. Four single end IO interface. Two differential Clock-In and Clock-Out signals. Single End Clock-In and Clock-Out. I2C interface. 12 volt and 5 volt power supplies. The following tables provides detailed description of the connector s pin out: 23 CB-50 Product brief 1.0

24 BANK1 FPGA CB-50 Pin Pin CB-50 FPGA NC 1 2 NC NC 3 4 NC NC 5 6 NC NC 7 8 NC NC 9 10 NC NC NC NC NC NC NC GXB1_TX_L5P, D2 XCVR TX5P XCVR RX5P GXB1_RX_L5P, F2 GXB1_TX_L5N,D1 XCVR TX5N XCVR RX5N GXB1_RX_L5N, F1 GXB1_TX_L4P, H2 XCVR TX4P XCVR RX4P GXB1_RX_L4P, K2 GXB1_TX_L4N, H1 XCVR TX4N XCVR RX4N GXB1_RX_L4N, K1 GXBTX_L2P, T2 XCVR TX2P XCVR RX2P GXB0_RX_L2P, V2 GXBTX_L2N, T1 XCVR TX2N XCVR RX2N GXB0_RX_L2N, V1 GXB0_TX_L1P, Y2 XCVR TX1P XCVR RX1P GXB0_RX_L1P, AB2 GXB0_TX_L1N, Y XCVR TX1N XCVR RX1N GXB0_RX_L1N, AB1 I2C_GP_DAT HSMC_SDA HSMC_SCL I2C_GP_CK NC NC NC NC TX_R22P (FPGA 5B,AB26) HSMC_CLKOUT CLKIN0 NC, Clock Generator 24 CB-50 Product brief 1.0

25 BANK2 FPGA CB-50 Pin PIN CB-50 FPGA TX_B65P (FPGA 4A, AG21) D D1 TX_B68P (FPGA 4A, AH21) TX_B73P (FPGA 4A, AG26) D D4 RZQ 2 (FPGA 5B, AB25) 3V V TX_B69P (FPGA 4A, AH23) TX0P RX0P RX_B74P (FPGA 4A, AE24) TX_B69N (FPGA 4A, AH22) TX0N RX0N RX_B74N (FPGA 4A AE23) 3V V TX_B48P (FPGA 4A, AG11) TX1P RX1P RX_B70P (FPGA 4A, AG23) TX_B48N (FPGA 4A, AH11) TX1N RX1N RX_B70N (FPGA 4A, AF23) 3V V TX_B45P (FPGA 4A, AG10) TX2P RX2P RX_B67P (FPGA 4A, AD23) TX_B45N (FPGA 4A, AH9) TX2N RX2N RX_B67N (FPGA 4A, AE22) 3V V TX_B44P (FPGA 4A, AG9) TX3P RX3P RX_B66P (FPGA 4A, AF22) TX_B44N (FPGA 4A, AH8) TX3N RX3N RX_B66N (FPGA 4A, AF21) 3V V TX_B41P (FPGA 4A, AG8) TX4P RX4P RX_B46P (FPGA 4A, AF15) TX_B41N (FPGA 4A, AH7) TX4N RX4N RX_B46N (FPGA 4A, AE15) 3V V TX_B40P (FPGA 3B, AH6) TX5P RX5P RX_B43P (FPGA 4A, U14) TX_B40N (FPGA 3B, AH5) TX5N RX5N RX+B43N (FPGA 4A, U13) 3V V TX_B37P (FPGA 3B, AG5) TX6P RX6P RX_B42P (FPGA 4A, AG13) TX_B37N (FPGA 3B, AH4) TX6N RX6N RX_B42N (FPGA 4A, AF13) 3V V TX_B36P (FPGA 3B, AH3) TX7P RX7P RX_B38P (FPGA 3B, AE12) TX_B36N (FPGA 3B, AH2) TX7N RX7N RX_B38N (FPGA 3B, AD12) 3V V GXBL0, V5 (Clock Generator) CLKOUT1p CLKIN1p CLK5P (FPGA 5B,W21) GXBL0, V4 (Clock Generator) CLKOUT1n CLKIN1n CLK5N (FPGA 5B, W20) 3V V 25 CB-50 Product brief 1.0

26 BANK3 FPGA CB-50 Pin PIN CB-50 FPGA TX_33P (FPGA 3B, AF7) TX8P RX8P RX_B35P (FPGA 3B, T13) TX_33N (FPGA 3B, AG6) TX8N RX8N RX_B35N (FPGA 3B, T12) 3V V TX_32P (FPGA 3B, AF5) TX9P RX9P RX_34P (FPGA 3B, AF11) TX_32N (FPGA 3B, AF6) TX9N RX9N RX34N (FPGA 3B, AF10) 3V V TX_B29P (FPGA 3B, AE8) TX10P RX10P RX_30P (PGA 3B, AD11) TX_B29N (FPGA 3B, AF9) TX10N RX10N RX_30N (FPGA 3B, AE11) 3V V TX_B28P (FPGA 3B, AE7) TX11P RX11P RX_B27P (FPGA 3B, T11) TX_B28N (FPGA 3B,AF8) TX11N RX11N RX_B27N (FPGA 3B, U11) 3V V TX_B25P (FPGA 3B, AE4) TX12P RX12P RX_B26P (PGA 3B, AD10) TX_B25N (FPGA 3B, AF4) TX12N RX12N RX_B26N (PGA 3B, AE9) 3V V TX_B8P (FPGA 3A, AD5) TX13P RX13P RX_B7P (FPGA 3A, Y11) TX_B8N (FPGA 3A, AE6) TX13N RX13N RX_B7N (FPGA 3A, AA11) 3V V TX_B6P (FPGA 3A, AC4) TX14P RX14P RX_B5P (FPGA 3A, U10) TX_B6N (FPGA 3A, AD4) TX14N RX14N RX_B5N (FPGA 3A, V10) 3V V TX_B4P (FPGA 3A, AA4) TX15P RX15P RX_B3P (FPGA 3A, U9) TX_B4N (FPGA 3A, AB4) TX15N RX15N RX_B3N (FPGA 3A,T8) 3V V TX_B2P (FPGA 3A, Y5) TX16P RX16P RX_B1P (FPGA 3A, W8) TX_B2N (FPGA 3A, Y4) TX16N RX16N RX_B1N (FPGA 3A, Y8) 3V V GXBL1, P8 (Clock Generator) CLKOUT2p CLKIN2p CLK6P (FPGA 8A, E11) GXBL1, N8 (Clock Generator) CLKOUT2n CLKIN2p CLK6N (FPGA 8A, D11) 3V V 26 CB-50 Product brief 1.0

27 3.4 Push Buttons and LEDs For debug the CB-50 supports 4 push buttons connected to both HPS and FPGA and two LEDs. The following tables provide details about their connectivity: Signal Description BP3 TX_B56P BANK4A IO BP4 TX_B68P BANK4A IO BP5 GPIO37 HPS GPIO BP6 GPIO0 HPS GPIO The two general purpose Les are connected as follows: LED Signal Description D7 IO1_6 IO expander on SPARK-100 D8 TX_B37P BANK4A IO 27 CB-50 Product brief 1.0