CB-52 Development board for the Spark-100 and Spark-102 Product Brief

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1 CB-52 Development board for the Spark-100 and Spark-102 Version 2.01 Product Brief

2 Document Revision History Revision Date Description Initial version Pin out was taken to another document, add power meter device name Fix 2 CB-52 Product brief 2.0

3 Contents 1 Scope Overview Ordering options Top view Bottom view Detailed description Block diagram Power SPARK-102 Power Metering SOM Configuration options CB52 interfaces UART (Debug) port -J I2C Interface Ethernet Interfaces USB Ports - J Micro-SD interface PCIe Interface LCD and Audio Interface - J Camera Interface - J Extension header -J HSMC - J Power inlet Jack J Micro-SD slot - J Push Buttons BP1, BP SMARC connector CB-52 Product brief 2.0

4 1 Scope The following document provides a description of the CB-52 evaluation board. Note that some of the components mentioned in the document are optional and will not be available in all variations of the CB Overview The CB-52 is a fully featured development and carrier board for ShiraTech s Spark-102. The CB-52 offers extensive connectivity to both HPS and FPGA along with an HSMC slot for supporting various expansion cards available from Altera. The board can be used by FPGA and software teams as a development platform offering all relevant peripherals for simulating the target product functionalities. The CB-52 is provided with a build in Software located on the internal emmc for quick development start up along with sample FPGA firmware for the available interfaces. Features: SMARC connector for SOM - SupportsSpark-100, SPARK-102 SE/SX and SPARK-102 with Industrial Ethernet support. Micro-SD card Built in interfaces o One 1000/100 Ethernet and two 10/100 Ethernet interfaces. o Two USB Host interfaces. o USB to RS-232 convertor for UART over USB emulation (DBUG). Built in connectors: o LCD & Audio connector - Four pairs LVDS interface (24 Bits), I2S audio interface. o Camera connector - Two lanes CSI interface. o HSMC connector - Supporting Altera compatible modules. o PCIe connector - Single PCIe lane on a 4 lanes interface(64 pins) o 20 pins expansion header: Single digital CAN interface. Two SPI Interfaces. FPGA's GPIOs 12 volts input power. 2.1 Ordering options The CB-52 has two flavor, the CB-52 which supports the Spark-102 and the CB-52A which supports the Spark CB-52 Product brief 2.0

5 2.2 Top view 5 CB-52 Product brief 2.0

6 2.3 Bottom view SD card slot 6 CB-52 Product brief 2.0

7 3 Detailed description 3.1 Block diagram uusb USB -> RS-232 UART Cold/Warm Reset SMARC SER 3 usd [0..3] 10/100/1000BT usd MAG BSEL, MSEL AFB 2 x 10/100BT MAG Push Buttons/LED USB 0 USB HUB USB Host A USB Host B Dual USB PCI 0 PCI CLK PCIe 1 Lane PCI Exp. 64 pins RFCLK0 I2S 0 LVDS 4 Lanes Touch Screen I2C Audio I2S LCD & Audio & VGA/HDMI CAM 0 CSI 2 Lanes Camera Differential Pairs I2C GP I2C0 1 Ser/Des 1, 2, 3, 4, 5 HSMC Clocks 12 V HPS/FPGA I/O Debug I2C PM I2C Current Measurment Figure 1 - CB-52 Block diagram 7 CB-52 Product brief 2.0

8 3.2 Power The CB-50 is powered by 12 volts power supply. The power input is controlled by a power switch that controls the power ramp and limits the output current to 4 Ampere. The following figure describes the power architecture. Vin 12V 12V Board 5V Board CB-52 Module Power Switch TPS (4A) 5V 4A AOZ1284P Power meter 5V SPARK 102 5v Board 3.3V 0.6A EP5358HQI 3.3V Board 1.8V 0.6A EP5358HQI 1.8V Board USB PWR AOZ1341 5V USB 3.3V 4A AOZ1284P 3.3V HSMC CB-52 HSMC 12V HSMC PCIe 8 CB-52 Product brief 2.0 Figure 1 CB-52 Power The power switch that controls the CB-52 input power is TPS by TI which ramp and limits the current to 4 Ampere. The input 12 volt power is connected to 12V to 5V converter by Alpha & Omega supporting up to 4 amperes. The 5V output feeds all other DC to DC. The DC to DC chips are enabled by the Carrier_PWR_ON signal from the carrier board (According the SMARC standard). The CB-52 power domains are: SPARK-102 domain (5V) drives the SPARK-102 power. This power is monitored by a power meter to measure the SPARK-102 power. CB-52 domain is powered directly from the 5V power source, all other power derived from the 5V source using Enpirion's DC to DC converters (3.3V and 1.8V). This power domain includes the CB-52 peripherals. HSMC power domain uses to power modules connected to the HSMC connector. The 12V power is connected directly to the power switch output and the 3.3V is derived from a DC to DC converter and can drive up to 4A. PCIe domain uses to power the PCIe cards. It is connected to a 12V and 3.3V power rails. Note When connecting an HSMC module and or a PCIe a power calculation is required.

9 3.2.1 SPARK-102 Power Metering The CB-52 can measure the current and power of the SOM by a digital current meter U-11. The device used is the EMC by Microchip. The power meter is connected to I2C1 (I2C_PM) of the Spark-102. The power is measured over a 0.01 Ohm resistor. The following figure describes the current meter: Figure 2 SPARK-102 Current Metering Since the power meter require a 3.3V signal level, a voltage translator is used to convert the HPS 1.8V I2C's signals to 3.3V. 9 CB-52 Product brief 2.0

10 3.3 SOM Configuration options The CB-52 sets the SPARK-102 behavior during power up. It sets the SPARK-102 booting pattern. The following figure describes how the CB-52 sets the SPARK-102 booting pattern (BSEL), the FW download (MSEL) and Bank 4A power select: CB-52 Module Vcc Vcc Vcc 1.5K 1.5K 1.5K J7 1 BSEL0 BSEL1 BSEL2 P123 P124 P125 BSEL0 BSEL1 BSEL2 HPS 1.5K 1.5K 1.5K J5 1 MSEL0 MSEL1 PSEL P104 P105 P106 Optional Optional MSEL0 MSEL1 MSEL2 MSEL3 FPGA MSEL4 Vcc BSEL0 SDIO MUX (TXS02612) emmc usd PSEL Bank 4A Power 1.8/2.5V Figure 3 CB-52 Botting Pattern The SPARK-102 core can boot from the following non-volatile memories. On-board FLASH using QSPI On-board emmc. Micro-SD on the carrier. QSPI on Carrier (TBD). 10 CB-52 Product brief 2.0

11 Selecting the boot options is done by using BSEL0, BSEL1 and BSEL2 selectors on J7 of the CB-52. The following table describes the booting options. BSEL[2..0] value Boot source Support 000 Reserved Not supported 001 FPGA (HPS-to-FPGA bridge) Supported both pins should be set '0' V NAND flash memory Not supported V NAND flash memory Not supported 100 Module emmc flash memory BSEL 0 closed 101 Carrier SD flash memory BSEL 0 opened V SPI or quad SPI flash memory Not supported V SPI or quad SPI flash memory Supported, all pins should be left open Table 1 - Boot Select Options The CB-52 enables four options to download the FW into the FPGA. These options are set by two of the MSEL bits (MSEL0 and MSEL1) on J5 of the CB-52. The following table describes the options: MSEL[4..0] value Download option Fast Parallel Fast Parallel/Security Fast Parallel/Compressed Fast Parallel/Security/Compressed Table 2 - Boot Select Options MSEL[4..2] are connected to GND on the SPARK-102. The CB-52 can control the power of the FPGA's Bank 4A. The signals PSEL can set the power to be 1.8V (Open) to 2.5V (Closed). Note - The selection of the Boot options and the FW download option is set at POR. 11 CB-52 Product brief 2.0

12 3.4 CB52 interfaces The CB-20 offers a large variety of interfaces for supporting a large variety of applications. The following table provides the available interfaces and their mapping to the various interfaces and the internal ports of the processor. Interface Processor interface Remarks Micro USB J13 HPS Debug port UART over USB with an internal converter 2xUSB host J-9 USB OTG An internal hub connect the SOC OTG port to two USB host ports 10/100/1000 Ethernet 10/100 Ethernet J-8 1G Ethernet port RJ-45 J-11, J-12 10/100 Ethernet port RJ-45, from the FPGA. Available only if the SOM has build in phys. PCI interface P1 PCI interfaces, connected to the FPGA LCD interface J-2 LVDS interface Connected to the FPGA Expansion header Camera interface J-6 Various GPIOs Can be used for connecting the HPS to external devices J-4 Connected to the FPGA HSMC interface J-1 Connected to the FPGA Power inlet J-10 5 Volt DC Micro SD slot J14 Connected to the HPS An internal multiplexer on the SOM select between the internal emmc and external SD Table 3 External interfaces The following paragraphs provide detailed description of each of the available interfaces UART (Debug) port -J13 The CB-52 internal debug UART is connected to a Micro-USB Type-A/B connector through an RS-232 to USB convertor. It enables debugging the SOM using a standard USB interface. The user should run UART emulation over USB when connecting the PC to the carrier board (See Getting Started Guide). The CB-52 uses UART0 of the SoC HPS interface for debug. The interface is available on the SMARC SER3 signals. 12 CB-52 Product brief 2.0

13 Figure 4 CB-52 Debug Option The USB to RS-232 convertor is powered by USB 5V (Powered by the USB interface). Its IO interfaces are compatible to 1.8V logic. It is configured as a USB device and its parameters can be configured by the USB interface (See FT-230X data-sheet). The device is preconfigured to support two led indicate traffic streaming RX/TX, through the device I2C Interface The CB-52 supports up to four I2C interfaces. Two of the interfaces, I2C_GP and I2C_PM are connected Module Carrier HPS I2C1 TEM Sensor RTC I2C_PM PWR Meter I2C0 EEPROM FPGA I2C_GP HSMC PCIe RXR6P/N I2C_LCD LCD&Audio TXT4P/N I2C_CAM Camera 13 CB-52 Product brief 2.0 Figure 6 - I2C interfaces

14 to the HPS. The two others, I2C_LCD and I2C_CAM can be emulated by the FPGA. I2C_GP (SPARK-102's I2C0) is connected to: o HSMC o PCIe I2C_PM (SPARK-102's I2C1) is connected to: o Power meter I2C_LCD (Can be emulated in FPGA) is connected to: o LCD & Audio connector. I2C_CAM (Can be emulated in FPGA) is connected to: o Camera connector (Multiplexed with HSMC CLKOUT2) Ethernet Interfaces The CB-52 supports a single Giga Ethernet interface and two Fast Ethernet interfaces. All Ethernet interfaces are available as an analog interface (PHY on SPARK-102) and are connected to an RJ-45 connector with integrated magnetic. The following figure describes the Ethernet interfaces connections. Module CB-52 HPS 4 x TX ETH1 125 MHz 4 x RX MDC/MDIO Micrel ksz9031 LEDS 8 Wires MAG J 8 RGMII 1 FPGA 4 x TX 25 MHz 4 x RX MDC/MDIO Micrel Ksz8081 FE1 LEDS 4 Wires MAG J 12 BANK 3A/3B MII 1 4 x TX 25 MHz 4 x RX Micrel Ksz8081 FE2 LEDS 4 Wires MAG J 11 MII 2 Figure 5 - Ethernet Interfaces 14 CB-52 Product brief 2.0

15 HPS 1G Ethernet -J8 The 1G Ethernet interface is connected to the SoC HPS RGMII1 interface. It uses Micrel's KSZ9031 PHY. There are two led support one for Link and the other for Activity FPGA Fast Ethernet - J11 and J12 There are two Fast Ethernet interfaces connected to the SPARK-102's FPGA using MII interface. The interfaces are connected to Banks 3A/3B (See the SPARK-102 HDS for details).the Fast Ethernet interfaces use the AFB signals in the SMARC connector. Each FE interface supports two leds one for Link and the other for Activity USB Ports - J9 The CB-52 supports two USB-Host ports. The following figure describes the USB interfaces. HPS Data[0..7] Ctrl USB PHY OTG (USB3300) Vcc Module OTG PWR_EN/OC# VBUS ID CB-52 USB0 OTG 5V GND USB HUB (USB2512B) Host PWR_EN PWR_OCR Host PWR_EN PWR_OCR USB1 USB Power USB2 USB Power 5V 5V Dual USB J 9 Figure 6 - USB Interfaces The CB-52 integrates two ports USB HUB which upstream is connected to the FPGA's HPS USB0. Since USB0 is an OTG, some of its signals are terminated on the CB-52 to enable it as a HOST: VBUS is connected to 5V (5V is available at the Host connector). ID is connected to GND (OTG is a Host) EN/OC3 is floating (Connected to a pull-up at the SPARK-102). The HUB is Microchip's USB2512B and it uses strap pins for configuration (It can't be programmed by SW). The HUB controls the power switch and monitors the current status for each of its ports Micro-SD interface The CB-52 supports a 4-bits Micro SD card. It is connected to the HPS SDMMC interface. The Micro-SD on the CB-52 and the emmc memory on the SPARK-102 share the same SD/MMC interface. Selecting between emmc and usd is done by BSEL0 selector. The following figure describes the CB-50 SD/MMC interface. 15 CB-52 Product brief 2.0

16 HPS MMC D[0..3], Ctrl SDIO MUX (TXS02612) D[4..7] D[0..3], Ctrl emmc 4-8GB Select SPARK-102 CB-52 10K D[0..3], Ctrl BSEL0 1K usd Card J 14 Figure 7 - Micro-Sd Card PCIe Interface The CB-52 integrates a four lanes PCIe connector (FCI, TLF - 64 pins). Only a single PCIe lane is connected to the SMARC connector and to the SPARK-102's FPGA. The following list describes the PCIe Interface: PCIe x 4 edge connector (Fit most of the PCIe cards) Single lane PCIe interface. I2C interface (I2C_GP) Supported control signals: o PCIe_RST# o PCIe_PRSNT# o PCIe_CKREQ# o WAKE# 12V and 3.3V power supply. The CB-52 integrates a PCIe clock generator (100 MHz). The clock drives the PCIe interface and the 16 CB-52 Product brief 2.0

FPGA's REFCLK0. The following figure describes the clock generator. The following figure describes the PCIe connector's signals: 3.4.

17 FPGA's REFCLK0. The following figure describes the clock generator. The following figure describes the PCIe connector's signals: LCD and Audio Interface - J2 The CB-52 supports an LCD and Audio interfaces using a 40 pins connector(molex Pico-Clasp, ). The supported signals are: Four pairs LVDS signals. Differential clock. I2C Interface (I2C_LCD emulated in the FPGA). Capacitive touch screen signals: o I2C_LCD o Touch Screen reset o Touch Screen Interrupt. o I2S audio interface (SMARC I2S0) and Audio clock (MCLK). LCD control signals: o LCD PWM o LCD BKLT Enable. GPIOs Note The LCD & Audio signals are emulated by the SPARK-102's FPGA. 17 CB-52 Product brief 2.0

18 J2 connector pin out : J2 FPGA CB-52 Pin Pin CB-52 FPGA 5V_LCD 1 2 5V_LCD RX_R8N (BANK 5A, V15) LVDS_BKLT_EN 3 4 LVDS_LCD_PWM RX_R8P (BANK 5A, V16) TX_R3P (BANK 5A, AE25) LVDS LVDS0+ TX_R1P (BANK 5A, AF26) TX_R3N (BANK 5A, AD26) LVDS1-7 8 LVDS0- TX_R1N (BANK 5A, AE26) GND 9 10 GND TX_R7P (BANK 5A, AA24) LVDS_CK LVDS2+ TX_R5P (BANK 5A, AC24) TX_R7N (BANK 5A, AA23) LVDS_CK LVDS2- TX_R5N (BANK 5A, AB23) GND GND RX_R6N (BANK 5A, W15) I2C_LCD_DAT LVDS3+ RX_R2P (BANK 5A, AA20) RX_R6P (BANK 5A, Y16) I2C_LCD_CK LVDS3- RX_R2N (BANK 5A, Y19) RX_R4P (BANK 5A, Y17) TS_I2C_RES GND RX_R4N (BANK 5A, Y18) TS_I2C_INT AUDIO_MCK RX_B42N (BANK 4A, AF13) HPS GPIO I2S0_LRCK RX_B46P (BANK 4A, AF15) NC I2S0_SDOUT RX_B46N (BANK 4A, AE15) TX_B53N (BANK 4A, AH14) I2S0_CK I2S0_SDIN TX_B53P (BANK 4A, AG15) NC V NC NC NC NC NC NC POWER_BTN# NC Camera Interface - J4 The CB-52 support a Camera interface using a 20 pins connector(molex Pico-Clasp, ). The supported signals are: Two lanes CSI and a differential clock. Camera clock (CAM_MCK). I2C interface (I2C_CAM) Camera reset signals. Note The Camera signals are emulated by the SPARK-102's FPGA. 18 CB-52 Product brief 2.0

19 J4 pin out: J4 FPGA CB-52 Pin Pin CB-52 FPGA 5V_CAM 1 2 5V_CAM RX_R23N (BANK 5B, W24) CSI0_D0-3 4 CSI0_D1- TX_R22N (BANK 5B, AA26) RX_R23P (BANK 5B, Y24) CSI0_D CSI0_D1+ TX_R22P (BANK 5B, AB26) GND 7 8 GND NC 9 10 CSI0_CK- RX_R21N (BANK 5B, W20) TX_R24N (BANK 5B, AB26) CAM_MCK CSI0_CK+ RX_R21P (BANK 5B, W21) GND GND RX_T4P (BANK 8A, E8) I2C_CAM_DAT CAM1_RST# RX_T1P (BANK 8A, D12) RX_T4N (BANK 8A, D8) I2C_CAM_CK CAM0_RST# RX_T1N (BANK 8A, C12) 3.3V V Extension header -J6 The debug connector is a 20 pins header (2 with rows with 2.54 pitch )that supports variety of signals that can be used to interface the SPARK-102. The following signals are supported: Two SPI interfaces with a single chip select. Single CAN interfaces, (digital TTL 3.3V). Two clock inputs connected to CLK0N and CLK1N. One FPGA signal (TX_B40N). Two of the signals, SPI0_SS0 and TX_B40N, are connected to a LED (D14 and D13). Signal Pin Pin Signal 5V 1 2 5V CAN0_TX 3 4 SPI0_SS0 CAN0_RX 5 6 SPI0_MISO NC 7 8 SPI0_MOSI NC 9 10 SPI0_CLK GND GND NC SPI1_SS0 CLK0N (FPGA) SPI1_MISO CLK1N (FPGA) SPI1_MOSI TX_B40N (BANK3B) SPI1_CLK 19 CB-52 Product brief 2.0

20 Signals description: SPI0 and SPI1 Master Interface from HPS SPI0,1_SPLK SPI clock SPI0,1_MOSI SPI MOSI SPI0,1_MISO SPI MISO SPI0,1_SS0 SPI Chip Select 0 Clocks CLK0N Single o single end clock inputs, connected to the FPGA CLKIN0N CLK1N Single o single end clock inputs, connected to the FPGA CLKIN1N CAN CAN0_TX Digital Can interface (3.3V TTL) CAN0_RX Digital Can interface (3.3V TTL) General Purpose I/O TX_B40N (BANK3B) Input/output connected to FPGA (1.8V) HSMC - J1 The CB-52 supports a standard HSMC connector based on Altera's specifications. The HSMC connector supports: Five transceiver pairs (Transmit and receive) connected to the FPGA's Transceivers. Seventeen differential pairs (Transmit and receive) connected to the FPGA Bank 4A. Four single end IO interface. Two differential Clock-In and Clock-Out signals. Single End Clock-In and Clock-Out. I2C interface. 12 volt and 5 volt power supplies. HSMC connector pin out BANK1 FPGA CB-52 Pin Pin CB-52 FPGA NC 1 2 NC NC 3 4 NC NC 5 6 NC NC 7 8 NC NC 9 10 XCVR RX5P REFCLK1LP NC XCVR RX5N REFCLK1LP GXB1_TX_L5P, D2 XCVR TX4P XCVR RX4P GXB1_RX_L5P, F2 GXB1_TX_L5N,D1 XCVR TX4N XCVR RX4N GXB1_RX_L5N, F1 GXB1_TX_L4P, H2 XCVR TX3P XCVR RX3P GXB1_RX_L3P, P2 GXB1_TX_L4N, H1 XCVR TX3N XCVR RX3N GXB1_RX_L3N, P1 20 CB-52 Product brief 2.0

21 GXB1_TX_L3P, M2 XCVR TX2P XCVR RX2P GXB1_RX_L4P, K2 GXB1_TX_L3N, M1 XCVR TX2N XCVR RX2N GXB1_RX_L4N, K1 GXBTX_L2P, T2 XCVR TX1P XCVR RX1P GXB0_RX_L2P, V2 GXBTX_L2N, T1 XCVR TX1N XCVR RX1N GXB0_RX_L2N, V1 GXB0_TX_L1P, Y2 XCVR TX0P XCVR RX01P GXB0_RX_L1P, AB2 GXB0_TX_L1N, Y1 XCVR TX0N XCVR RX0N GXB0_RX_L1N, AB1 I2C_GP_DAT HSMC_SDA HSMC_SCL I2C_GP_CK NC NC NC NC TX_B49P (FPGA 4A,AH12) CLKOUT CLKIN0 TX_B57P (FPGA 4A,AF18) BANK2 FPGA CB-52 Pin PIN CB-52 FPGA TX_B76N (FPGA 4A, AH26) D D1 TX_B73P (FPGA 4A, AG26) TX_B68P (FPGA 4A, AH21) D D3 TX_B65P (FPGA 4A, AG21) 3V V TX_B80P (FPGA 4A, AF27) TX0P RX0P RX_B78P (FPGA 4A, AF25) TX_B80N (FPGA 4A, AF28) TX0N RX0N RX_B78N (FPGA 4A AG25) 3V V TX_B77P (FPGA 4A, AG28) TX1P RX1P RX_B75P (FPGA 4A, AC22) TX_B77N (FPGA 4A, AH27) TX1N RX1N RX_B75N (FPGA 4A AC23) 3V V TX_B72P (FPGA 4A, AG24) TX2P RX2P RX_B74P (FPGA 4A, AE24) TX_B72N (FPGA 4A, AH24) TX2N RX2N RX_B74N (FPGA 4A AE23) 3V V TX_B69P (FPGA 4A, AH23) TX3P RX3P RX_B70P (FPGA 4A, AG23) TX_B69N (FPGA 4A, AH22) TX3N RX3N RX_B70N (FPGA 4A, AF23) 3V V TX_B64P (FPGA 4A, AF20) TX4P RX4P RX_B67P (FPGA 4A, AD23) TX_B64N (FPGA 4A, AG20) TX4N RX4N RX_B67N (FPGA 4A, AE22) 3V V TX_B61P (FPGA 4A, AG19) TX5P RX5P RX_B66P (FPGA 4A, AF22) TX_B61N (FPGA 4A, AH19) TX5N RX5N RX_B66N (FPGA 4A, AF21) 3V V TX_B60P (FPGA 4A, AG18) TX6P RX6P RX_B62P (FPGA 4A, AE20) TX_B61N (FPGA 4A, AH18) TX6N RX6N RX_B62N (FPGA 4A, AD20) 3V V TX_B56P (FPGA 4A, AH17) TX7P RX7P RX_B59P (FPGA 4A, AA19) TX_B56N (FPGA 4A, AH16) TX7N RX7N RX_B59N (FPGA 4A, AA18) 3V V TX_R22P (FPGA 5B, AB26) CLKOUT1p CLKIN1p CLK2P (FPGA 4A,AA13) 21 CB-52 Product brief 2.0

TX_R22N (FPGA 5B, AA26) CLKOUT1n 97 98 CLKIN1n CLK2N (FPGA 4A,Y13) 3V3 99

11 Power inlet Jack J10 The DC jack enables powering the CB-52 using a

22 TX_R22N (FPGA 5B, AA26) CLKOUT1n CLKIN1n CLK2N (FPGA 4A,Y13) 3V V Power inlet Jack J10 The DC jack enables powering the CB-52 using a standard power adaptor Micro-SD slot - J14 The CB-52 uses Foxconn's micro-sd connector (WQ2182C-DES1-7F). 22 CB-52 Product brief 2.0

23 Pin Signal Description 1 MCI0_DA2 Data 0 2 MCI0_DA3 Data 3 3 MCI0_CDA Command line 4 3.3V 3.3v power 5 MCI0_CK Clock. 6 GND Digital ground 7 MCI0_DA0 Data 0 8 MCI0_DA1 Data 1 9 GND Card inserted polarity (Low) 10 MCI0_CD Card detect 11 GND Digital ground 12 GND Digital ground 3.5 Push Buttons BP1, BP2 The CB-52 supports 2 push buttons. Pin BP1 BP2 Warm Reset Cold reset (POR) Description 3.6 SMARC connector The SMARC connector is defined in the following document. Note The CB-52 pins allocation is based on the SPARK-102 equipped with Cyclone V SX with 110KLEs. 23 CB-52 Product brief 2.0

CB-50 Development board for the Spark-100 Product Brief

CB-50 Development board for the Spark-100 Version 1.0 Product Brief Contents 1 Scope... 3 2 Overview... 3 2.1 Top view... 4 2.2 Bottom view... 4 2.3 Ordering options... 5 3 Detailed description... 6 3.1