SEESAW: Set Enhanced Superpage Aware caching
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1 SEESAW: Set Enhanced Superpage Aware caching Set Associativity Mayank Parasar, Abhishek Bhattacharjee Ω, Tushar Krishna School of Electrical and Computer Engineering Georgia Institute of Technology Ω Department of Computer Science Rutgers University
2 Outline 2 Motivation SEESAW: Concept SEESAW: Micro-architecture Evaluation Methodology Results Conclusion
3 L1 Cache Characteristics 3 Fast lookup High hit-rate Energy Efficiency
4 Virtually Indexed Physically Tagged [VIPT] 4 Cache VA VPN Page Offset Set index block offset v tag Data block TLB set-1 PA PPN Page Offset set-n Cache = HIT/MISS
5 Virtually Indexed Physically Tagged [VIPT] Cache 5 VA VPN Page Offset TLB Set index block offset v tag VIPT Caches necessitate: (set-index + block-offset) <= Page-offset Data block set-1 PA PPN Page Offset Cache set-n = HIT/MISS
6 Impact of Associativity on Access Latency and Energy of cache 6 Cache Access Latency Cache Access Energy
7 Effect of associativity on MPKI of cache 7 High Associativity hurts latency and energy without commensurately improving hit rate
8 Revisiting L1 Cache Characteristics for VIPT Cache 8 Fast lookup Virtual memory! High hit-rate Energy Efficiency Virtual memory!
9 Opportunity: Superpage 9 Is it possible to relax constrains of Traditional VIPT cache? Yes How? Offset-bits: 12 Offset-bits: 21 Offset-bits: 30 4-KB Baseline Page 2-MB 1-GB More page-offset bits for superpage! Super Page HW and OS Support for Superpages in modern processors
10 Prevalence of superpages in modern OSes under memory fragmentation 10 Ran on 32-core; Sandybridge; 32 GB RAM Memhog causes memory fragmentation; higher %age indicates higher fragmentation
11 Outline 11 Motivation SEESAW: Concept SEESAW: Micro-architecture Evaluation Methodology Results Conclusion
12 SEESAW: Concept Set:1 Set:2 et:3 v tag Data block super-page Base-page Set:1 Set:2 Set:3 Set:4 Set:5 Set:6 Set:7 Set:8 Set:9 v tag Data block 12 Faster Energy-Efficient Less-sets More-associativity More-sets Less-associativity
13 Outline 13 Motivation SEESAW: Concept SEESAW: Micro-architecture Evaluation Methodology Results Conclusion
14 SEESAW: Micro-architecture 14 A VPN Partition bit Translation Filter Table (TFT) Superpage offset Basepage Offset Set index block offset set-1 v tag Data block Partition decoder v tag Decodes partition index from partition bit Data block set-1 TLB Predicts whether page is superpage A PPN Basepage Offset set-n Partition-0 Cache Partition-1 set-n
15 SEESAW: Micro-architecture 15 Superpage offset A VPN Basepage Offset Partition bit Translation Filter Table (TFT) Set index block offset set-1 v tag Data block Partition decoder v tag Data block set-1 TLB A PPN Basepage Offset set-n Partition-0 Cache Partition-1 set-n
16 SEESAW: Superpage access 16 Superpage offset A VPN Basepage Offset Partition bit Translation Filter Table (TFT) Set index block offset set-1 v tag Super Page Data block Partition decoder v tag Data block set-1 TLB A PPN Basepage Offset set-n Partition-0 Cache Partition-1 set-n = HIT/MISS
17 SEESAW: Basepage access 17 A VPN Basepage Offset Partition index Translation Filter Table (TFT) Set index block offset set-1 v tag Not a Super Page Data block Partition decoder v tag Data block set-1 TLB A PPN Basepage Offset set-n Partition-0 Cache Partition-1 = HIT/MISS set-n
18 18 SEESAW: TFT and Partition Decoder Translation Filter Table (TFT) Partition decoder Tag: VA[63:21] Super page? Translation Filter Table Ø TFT Lookup Ø Direct mapped Ø False negative due to size Ø TFT Update Ø VA misprediction Ø 2MB L1-TLB fill Ø 2MB L1-TLB Invalidation Partition Decoder Ø For 32kB Cache Ø For 64kB Cache
19 SEESAW: Cache line insertion policy A VPN Partition bit Translation Filter Table (TFT) Baseline Page Offset Set index block offset set-1 v tag Data block Partition decoder v Which partition should cacheline be inserted? tag Data block TLB 19 set-1 A PPN set-n Baseline Page Offset Partition-0 Cache Partition-1 set-n
20 20 SEESAW: Cache line insertion policy 4way-8way Superpage miss: victim within the partition Basepage miss: victim within the set 4way Uses LRU within the associated partition Avoid installing the same line twice Saves energy
21 21 SEESAW: System Level Optimization Cache coherence Cache coherence lookups use physical address Snoopy provide higher energy benefits over Directory based coherence Page table modifications Superpage splintered into multiple basepages Multiple basepages promoted to superpages
22 Outline 22 Motivation SEESAW: Concept SEESAW: Micro-architecture Evaluation Methodology Results Conclusion
23 SEESAW: Simulated system 23
24 24 SEESAW: Workloads Spec Parsec Cloudsuite Tunkrank Biobench Mummer Tiger MongoDB Server Workload graph500 Nutch Hadoop Social-event web service Olia Key value store Redis
25 Outline 25 Motivation SEESAW: Concept SEESAW: Micro-architecture Evaluation Methodology Results Conclusion
26 SEESAW: Performance improvement 26 SEESAW observes 3-10% better runtime over baseline
27 27 SEESAW: Performance improvement Out-of-order CPU in-order CPU ~10% performance improvement for 64kB cache in OoO CPUs
28 28 SEESAW: Energy savings 10-20% more energy savings over CPUs using baseline VIPT caches! Approx. one-third of energy savings from coherence
29 SEESAW: TFT analysis and Way-Prediction 29 TFT Analysis SEESAW + Way-prediction 16-entry TFT drives miss-rate under 10% SEESAW+WP shows symbiotic behavior
30 Outline 30 Motivation SEESAW: Concept SEESAW: Micro-architecture Evaluation Methodology Results Conclusion
31 Revisiting L1 Cache Characteristic 31 Fast lookup High hit-rate Energy Efficiency
32 SEESAW: Conclusion L1 caches are optimized for latency VIPT imposes indirect restriction on number of sets in a L1 cache, increasing associativity There is non-linear relation between associativity and access latency/energy of the L1 cache Superpages are often used in modern OSes SEESAW provides low-associative access to superpages, providing both latency and energy benefits Up to 10 % performance improvement and 20 % energy reduction in modern workloads SEESAW has extremely low-overhead and is readily implementable Set Associativity 32
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