Refresh-Aware DDR3 Barrel Memory Controller with Deterministic Functionality

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1 Refresh-Aware DDR3 Barrel Memory Controller with Deterministic Functionality Abir M zah Department of Computer and System Engineering ENSTA-Paristech, 828 Blvd Marechaux, Palaiseau, France abir.mzah@ensta-paristech.fr Bruno Monsuez Department of Computer and System Engineering ENSTA-Paristech, 828 Blvd Marechaux, Palaiseau, France bruno.monsuez@ensta-paristech.fr ABSTRACT With the increasing bandwidth demand in system technologies, several generations of memory have been optimized in order to guarantee higher QoS and better performance. Dynamic memory has various advantages in terms of frequency and bandwidth but the periodic refresh operation remains its principle weakness which reduces the chance of its use in reliable hardware real time systems. In spite of the refreshment important role to prevent data loss, this operation decreases predictability and bandwidth by about 3% in dynamic memories. We propose a memory controller which guarantees the refreshment of our DDR3 memory during the write operation. We choose to write in predefined address following a barrel shifter technique. This idea represents the key solution to visit all the rows within the maximum required refresh time. This technique is an original solution to preserve memory write, read and refresh reliability. General Terms Performance, Design, Reliability, Security, Verification. Keywords DDR3, Refresh, barrel, reliability, predictability 1. INTRODUCTION Ensuring efficient communication between processors and memories is a critical task to guarantee an optimized system design. The Dynamic Random Access Memory (DRAM) with its different Double Data Rate Synchronous Random Access Memory (DDR SDRAM) generations offers high performance and bandwidth. In fact, the third DDR family called DDR3, runs at a frequency margin of 400 MHz to 1066 MHz, which is the double of DDR2 [1]. The ability to transfer double data rate represents one major contribution of DDR3 compared to its direct earlier generation DDR2. Power consumption reduction is considered as a major gain when moving to DDR3. In fact, the voltage is reduced to 1.5 v vs 1.8 v for DDR2. This fact reduces 17% of the memory power demand [2]. Another new generation has recently emerged which is DDR4. It has twice Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from Permissions@acm.org. ODES '14, February , Orlando, FL, USA Copyright 2014 ACM /14/02 $ the number of banks compared to DDR3. DDR4 memory offers sixteen banks, while we have only eight in the case of DDR3. Other advantages can also be mentioned, like the reduction of power consumption and the use of an error detecting code which is Cyclic Redundancy Check (CRC) applied only during the write operation. Our work is included in an industrial project which aims to design a deterministic switch with 10 ports ( 8 ports x 1Gbits/s bandwidth, 2 ports x 10Gbits/s bandwidth). In order to avoid packet conflicts in this switch, we choose to adopt the starvation technique which, means that we should always route the packets through the switch before receiving a new one. The maximum bandwidth when we receive data from all the ports is equal to 30 Gbits/s. That is why; we need to perform a data transfer between multiprocessors system on chip components with a bandwidth of 30 Gbits/s for the read and the write operations. This operation must be completely predictable and reliable. In this work, we only use the protocol TCP/IP which defines the frame with an ID of 16 bits. That is why; we know previously that we have possible frames. All the frames are messages with a length between and 8KB. In order to respect a 30 Gbits/s data bandwidth for the read and for the write operations we define two strict constraints. Firstly, we should be able to perform simultaneously a read and a write operation each about 15 ns. Secondly, a Write or a Read operation will always treat packets of during each operation. Each frame will be divided into packets of. For the extreme case where we receive a continuous data stream, the memory should be able to write every eight clock cycles at a frequency of 533MHz. These choices will guarantee the same behavior at each write or read access. In fact, write and read operation on a DDR memory needs a delay of time to be completed. When a write operation is progressing on a bank of a memory, we cannot access to it until the actual operation is finished. But as we have already detailed we should ensure a parallel read operation during an ongoing write. Even though it is possible to apply an interleaving memory access to the different banks from the same chip memory, it is impossible to send two different commands to the same memory at the same clock edge. That is why we need more than one DDR chip memory to offer simultaneous read and write operation. We propose to define a data frame thanks to its unique key or ID. That is why a read or a write operation needs to only provide the key of the needed frame. A mapping between the key and the physical address can be defined with hash table technique. Thanks to these elements, we have performed an early analysis in order to choose between DDR3 or DDR4 memory [3][4].With reference to the specification documents, we can verify that bandwidth and latency can be respected by both models. Even though DDR4 includes sixteen banks, it is important to notice that we cannot access to more than four banks during a tfaw (Four Activate Window) time. In order to guarantee parallel read/write operations progressing, we need to access few separate banks from

2 different chip memories. That is why eight banks in a chip memory would be enough to satisfy our project needs. For reliability, we have already chosen to apply a CRC during the read and the write operations. With these elements, we propose to use DDR3, which is largely enough for our project. Migration to DDR4 can be easily performed later with future harder constraints. By using DDR3 memory, we are sure that we have enough capacity to store our data variables, but on the other hand, we must deal with the main disadvantage of this technique, which is the refreshment operation. A DRAM has a bit cell structure based on one transistor and one capacitor. The bit data is stored in the capacitor and can be gradually lost unless a refresh command is applied periodically to recharge all the capacitors [5]. That is why the memory refresh command must be applied periodically, which delays the main functions of read and write. In spite of this, the memory can receive up to 9 refresh commands before starting a refresh cycle, which makes this operation completely unpredictable[3]. The main contribution of this work is to propose a safe DDR3 memory driver where predictability and reliability are guaranteed during write, read and refresh operations. Performing implicit memory refreshment during the write operation represents the original idea of this paper. Based on the possibility to perform a parallel access to the different memory banks, we propose to design memory architecture with an interleaving access (write, read, write ). This solution will be detailed in the coming sections. The paper is organized as follow: we present in section 2 the related work. A detailed description of the DDR3 SDRAM will be the subject of section 3. In section 4, we present the memory design based on 8 DDR3 chips. The memory controller with barrel address mechanism is the main idea of section 5. The last sections are reserved for a discussion and a conclusion of this work. 2. RELATED WORK A DDR3 memory controller should ensure the different main memory functions, which are: initialization, calibration, activation, write, read, refresh and precharge. This module affects directly the performance of DDR3 memory access. Different works have proposed solutions for this [1] [2] [3] [4]. Aqueel et al [5] have proposed a design of a DDR3 SDRAM controller. They have designed a pipelined architecture which guarantees an address request each 15 clock cycles. This module was tested with a DDR3 memory model. Even though authors have presented the implementation results on an FPGA, the refresh impact and the reliability information are not meaningfully detailed. In work [3], authors have designed a DDR3 controller respecting the general (Finite State Machine) FSM functionality. They have divided the design into controller module, signal module and data path module. We notice that the authors did not give enough information about the needed delay time for activating and precharging the different rows. This work was tested with a memory model and several test cases. With a similar approach we can neither have a clear idea about the dysfunctional part of this IP nor to be sure about the latency evaluation. In [2], Guoteng et al, have designed a DDR3 memory controller based on heuristic methods for memory access scheduling. They propose to divide the memory access requests into eight groups, where elements within the same group are proper to a single memory bank. Priority and memory access between the different groups are managed by a memory access scheduling module. In order to prevent the FIFO starvation of each bank, authors have applied anti-starvation counter which may change the priority order when it reaches a threshold value fixed by the authors. We estimate that there is a need to evaluate in depth the conflicts of memory access risk using this method especially when several counters reach the threshold value at the same time. In other works, the memory controller was included in AXI Design Core [1] [4]. Authors have proposed in [1], a memory controller that is joined to a checker module. This controller should compare the obtained result after a read/write operation to the expected one stored in the local data. Even though authors have applied an exhaustive functional verification, they do not present a complete design reliability study. The latency of the controller memory in [1] is between 10 and 35 clocks. This big difference between the minimum and the maximum latency values is a direct result of the row activation and deactivation time. In these cited works, we can notice that the refresh operation does not represent an important constraint during the DRAM controller design. Proposed solutions have only to deal with refresh time scheduling. Some works have proposed solutions for predictable SDRAM controllers [6] [7]. Authors in [6] have highlighted the unpredictable nature of the refresh operation. In fact, they consider that the asynchronous behavior of the refresh and write/read operation is the main cause of this unpredictability. Based on this conclusion, they propose to ensure refresh operation using two methods: pure software and hardware/software refresh scheme. The proposed SDRAM controller in [7] is a hardware solution for memory scheduling. In these two works the refresh operation is applied separately, which is not the case of our work where we propose to combine this task with the write command, which avoids delaying operations or stacking the memory. 3. DDR3 SDRAM PROPERTIES After a preliminary analysis, we propose to run our memory at a frequency of 533 MHz. We choose the reference DDR3-1066, which offers a frequency between MHz. It is possible to have higher frequency for the DDR3 memory by choosing another reference but there is no real need to increase memory performance because other design IPs cannot deal with this high frequency. We present the typical DDR3 memory behavior. After the initialization and the calibration steps, the memory remains in the idle state until receiving an activate command. A write or a read operation on a deactivated row must be preceded by an activate command. Read and write access is burst-oriented. A continuous data transfer is performed starting from a column address position and during a burst length. We propose to only use BL8 burst, which needs a burst length period of 4 clock periods. In Table 1, we present the different properties of our DDR3 memory. When we write two bursts (BL8) on a deactivated row, we need at least 35 clock periods (see Figure 1) to be able to activate another one on the same bank. Table 1. DDR3 Timing Properties Variable Definition Value CL CAS READ latency 7 ck CWL CAS Write latency 5 ck AL=CL-1 Additive Latency 6 ck trp PRECHARGE command period 7 ck trcd ACTIVATE to internal READ or WRITE 7 ck delay time tccd CAS#-to-CAS# command delay twtr Delay from start of WRITE to internal READ twr Write recovery time 8 ck trfc REFRESH-to-ACTIVATE or REFRESH 59 ck command period burstlength Length of the burst Periode (T) Clock period ns

3 Reading data from a deactivated row needs 27 clock periods (see Figure 2) to perform the row activation, the data transfer and the row precharge. In this work, write and read operations are exclusively performed by double bursts. We present in Figure 1 an example of a write-write operation. In order to respect the memory constraints, we need at least 28 clock periods to be able to read just written data (from Active to possible Precharge (Pre) (see Figure 1)). To be able to receive each eight clock periods, we propose to write 128 bits (2 bursts) on 4 banks at the same time, which means that we need 35 clock periods to activate, write the stream data of, and to precharge the activated row. In figure 2, we present the readread operation of two data bursts. We need 14 clock periods to activate the row memory and to receive the first data bit. Write and read operations are always performed like the illustrations in Figure 1 and Figure 2. Memory refresh is an important operation for DRAM families. A DDR3 memory should be refreshed each 64ms in order to ensure data stability. Refresh operation is a simple row activation and deactivation ensuring data stability. It is possible to send a refresh order to the whole memory each 64ms but it is also possible to send a refresh command for a row each trefi (Maximum average periodic refresh). In this case, the memory refresh is distributed over the time. When receiving a Refresh command Ref, an internal memory counter increments the row address to the next one trefi(maximum average periodic refresh) = During the refresh time, which is equal to trfc (REFRESH command period), the memory is considered in the mode Don t care. In fact, a read or a write operation should be delayed by trfc. The total refresh time needed for the entire memory is equal to 1.812µs for each 64ms. This means that the bandwidth overhead is equal to 2.83%. An efficient design should take in consideration the refresh constraint. Despite the bandwidth overhead cost, this operation can decrease the deterministic behavior of the memory. DDR3 can receive up to nine Refresh commands before starting a real refresh cycle. With such functionality the delay time of the read write operations cannot be predictable. Based on this conclusion, we propose memory design architecture based on a barrel row memory access which will be detailed in section 5. This proposed methodology ensures the memory refresh during the write operation. 4. THE HARDWARE MEMORY DESIGN In Figure 3, we present, the memory architecture used in this paper. We propose to use eight DDR3 memory chips from two different ranks. Chips from the same rank share command and address signals while each one has a separate 8-bits data signal. We propose to perform simultaneously a write and a read operation on both ranks. When a write operation is progressing on a rank, a read function is progressing on the other one which is illustrated in Figure 4. One main objective of this work is to design a memory with a read and write bandwidth of at least 30 Gbit/s. At T=0ck, when we receive, the minimum object length, this package will be stored in the input Buffer (Buffer_IN_1) and each chip from rank 0 will write 12 or two bursts of 64 bits. This operation is illustrated in Figure 1. At T=8ck (15 ns) a new message of is written to the same bloc memories (Rank 0). Each chip memory can perform this write operation on a different bank within the eight available ones. We notice that during the period (0 ck to 36 ck), four write operations are progressing simultaneously on four different Act Write Write tras(min)=20ck Pre Act 35 AL=6 ck CWL=5 ck 1 ck AL=6 ck CWL=5 ck Burst 64 bits Burst 64 bits twr=8 ck trp=7ck Figure 1. Write operation (2 bursts) on the same row ActRead Read tras(min)=20ck trc=27ck Pre 20 trp=7 ck Act 27 AL=6 ck CL=7 ck 1ck AL=6 ck CL=7 ck Burst 64 bits Burst 64 bits Figure 2. Read operation (2 bursts) on the same row

4 banks of each chip memory in rank0. We can verify that there is no conflict in the memory pins. At 36 ck, the first read command can be sent to the bank 0. Thanks to this delay time, we are sure that the previous writing operation is finished correctly. The opposite behavior is applied on the other chips from Rank 1. When a write operation is progressing on Rank 0 a read one is applied on Rank 1. Thanks to this architecture, we have a bandwidth of 30 Gbit/s for the write and the read operations. We want to precise that our bandwidth computation memory has already included the refresh operation without any bandwidth loss. The original idea of this work is to ensure the refresh memory during the write operation. This idea will be detailed in the next section. 5. BARREL MEMORY CONTROLLER ALGORITHM With reference to the refresh operation detailed in the previous sections, we should ensure a row memory refresh each 64 ms. The original idea of this work is to guarantee visiting all the rows within this delay of time, which is in reality an implicit refreshment. We start by some rule specifications. We propose that a write operation is always similar to the functionality described in Figure 1. Each write command will exactly take 35 clock periods in order to activate a new row, to write two bursts on it and finally to precharge it. A read operation takes exactly 27 clock periods (see figure 2). This time is sufficient to activate the needed row, to transfer the two data bursts and finally to deactivate the used row. This choice guarantees that all the rows are deactivated after each read or write operation but it is also the key to having deterministic memory functionality. It is evident that we cannot in reality control the read operation as we cannot predict the future address. A user can keep reading data from the same row during a long time. That is why we cannot guarantee visiting all the row memories with read operations. The write operation offers more freedom and flexibility. In fact we can decide where to write the received data without having any constraints. In our case the list of the variables is defined initially. We use a table to match the key object and the corresponding address. The processor should only provide the command and the object key. In the case of the read operation, we should match the key to the corresponding address with reference to the (key, address) table. For a write operation we can choose the address memory then we update the key object address in the table. That is why, we choose to apply a writing mechanism ensuring implicit memory refreshment. 5.1 Merging Write and Refresh operations We have already detailed in Section 3 that in order to refresh all the memory, we need to send a refresh command to a new row each 1.812µs. We propose to merge the write and the refresh operations to obtain this result. In fact, we can verify in Figure 4 that we send a Write command to the same memory bank exactly each 72 clock periods which is equal to 0.135µs. We propose to write to a new row each 72 clock periods. Starting from row 0 and reaching the last memory row 16384, the write operation is moving from a row to the next one each 0.135µs. We start by writing on the same range of columns in all the rows. We then move horizontally to the next range columns, this is presented in Figure 5. The writing address is following a barrel shifter algorithm. In fact, we write on the same row each 2.211ms which is considerably shorter than the maximum delay refresh time which is equal to 64 ms. Thanks to the write operation the memory refresh is performed automatically and implicitly. During the write period, if data is available, the write operation is performed, otherwise a simple row activation and deactivation is applied. Thanks to this mechanism we can use the DRAM memory without losing memory bandwidth for refresh operation. The most important advantage of this technique is the possibility to have deterministic memory functionality, which is not the case when we use Refresh commands. When we send a Ref to the memory, we can not exactly know when the refresh operation will happen Write Conflict Management Thanks to the barrel shifter technique, we can know the address of Memory Design Buffer_OUT_1 Rank 0 Mux Chip 0 Chip 1 Chip 2 Chip Demux Buffer_IN_1 Buffer_OUT_2 DDR 3 Chip memory Rank 1 Chip 4 Chip 5 Chip 6 Chip 7 Buffer_IN_2 Figure 3. High level Memory Design (Each chip has data width vector, we can send 16 bits to a single chip each clock period (8bits * 2 edges(high, low), we can send 16 * 4 = 64 bits each clock period to 4 chips, during a burst time ( 4ck) we can send 256 bits to the four chips, during two bursts we can send to the 4 chips from the same rank ( Figure 1 x 4))

5 Write operation ( see Fig 1) Read operation ( see Fig 2) Memory pin occupation : data transfer through memory pins T0 T4 T8 T12 T16 T20 T24 T28 T32 T36 T40 T44 T48 T52 T56 T60 T64 T68 T72 T80 T Chip Chip Chip Figure 4.. Memory behavior the coming write operation in advance. At the first use of a free memory there is no problem of data conflict but after filling some memory places we must prevent such conflicts by verifying if the coming address memory was free in order to prepare the future write operation. If the next address is free, only the write operation will be performed, but if we detect a coming conflict, a read and a write operation will be applied. In order to move data from the coming address location, we should anticipate enough time to read it. This read data is pushed in a FIFO to be written to a new free address later. As we can receive data from two different sources (data bus and the FIFO) we propose to ensure an interleaving data reception, which is illustrated in Figure 6. When we have data from a source we keep writing from it until receiving new data from the other one. Row Write barrel operation Row 1 Row 0 Memory width 2 bursts width 12 Figure 5. Barrel writing operation Datafifo/ Data from Bus Data from Bus 0 1 Datafifo Figure 6. Datain interleaving sources Data from Bus/ datafifo We describe the write operation by the Finite State Machine presented in Figure 7, Table 2 details the different possible transitions. When a write command is sent (CMD Write =1), we should be sure that the coming address is free. In order to be able to read and to move data previously, we need to verify the availability of For example, if we know at t=t0 in Figure 4 that the coming address in bank 1 of chips [4..7] is full we will send a read command to this location at least at t=t4. Read data will be stored in the FIFO to be written later in another memory location. If at t=t0 we discover that the memory location (@+1) from bank 1 of chips [1..3] is full, it is clear that we don t have enough time to read data from this location. That is why the memory availability should be checked early which permits an eventual read operation. All the possible cases are presented in Table 2. If there is no write command, we will keep waiting in the idle state. We are sure that we cannot move from an operation to another one without passing through the idle state. In fact, there is a minimum of tccd (Cas-to- Cas command Delay) time which is equal to four clock periods to have two successive commands. If there is no available data and if the memory is not free (T5), the algorithm will move from state idle to state (Ref & Rd) in order to send a read command

6 to the location and to refresh the actual row by simple activate and precharge commands. If we receive data and we check that the is free, the active state will move from idle to the state Wr in order to perform a simple write operation at the actual memory address. When data is available but the is not free (T7), we should perform a write operation at the actual address (@) and a read operation of the memory address (@+5). This functionality is the subject of state (Wr & Rd). Data read during states (Ref & Rd) and (Wr & Rd) is stored in the FIFO to be written later on a new free address. Finally, if there is no data to write and no coming conflict, the algorithm will move from the state idle to the Ref where only refresh operation is performed. 5.2 Read operation Thanks to the interleaving Write/Read commands of our architecture, we can alternately write and read on the same memory bank. When we send a Read command to the memory, we should verify first of all, if the data address is located in the FIFO or if it is in the memory (see Figure 8). If the data has a memory address, we will read it directly but if it was located in the FIFO we will keep waiting until receiving it, which can take at most the FIFO depth delay of time. During the writing operation data locations are updated according to the (key, address) table. Ref & Rd T5 Ref Not T5 T6 Not T6 Idle T7 T1 or T2 or T3 or T4 Not T7 T8 Wr & Rd Not T8 Wr Ref & Rd : Refresh & Read(@+5) Ref : Refresh Wr & Rd : Write(@) & Read(@+5) Wr : Write(@+5) Figure 7. FSM Write operation Table 2. Write Lookup Table Transitions CMD= Is Data free write available T T T T T T T T CMD Idle 6. DISCUSSION CMD = Read of ID = FIFO of ID in Mem Check (ID,@) of ID = Mem Figure 8. FSM Read operation The main objective of our DDR3 memory architecture is to ensure reliability and predictability with respect to the bandwidth demand of 30 Gbits/s for the write and for the read operations. Different choices were taken in order to guarantee these characteristics. The predefined write/read order time slot is a smart method to know precisely the memory access organization and to improve predictability and the Worst Case Execution Time (WCET) estimation. Predictability: By merging refresh and write operations, we are ensuring data storing without needing to use the Refresh command which affects the memory determinism. In fact, when we send a Refresh command we cannot be sure that this one will be applied immediately or delayed for later. Thanks to the barrel write operation, we can refresh data regularly with a predefined order. The choice of precharging a row after each use increases the memory reliability. With such technique we can be sure that all the rows are deactivated after a memory access which gives us the exact needed time to perform the read/write operation. WCET evaluation : Write operation: Because we guarantee a predefined memory address for the write operation, there is no risk of conflict. That is why the Worst Case Execution Time is equal to the value of 35 clock cycles (see Figure 1) which is about ns. After this delay we are sure that the write operation is finished and the row is precharged. Read operation: For the read operation we have two cases: data is located in the memory or in the FIFO. When data is written on the memory the WCET to receive the first data bit is equal to 14 clock cycles. This operation needs 27 clock periods to read the complete data and to deactivate the used row. The worst case for the read operation is to read a data which is just written in the FIFO. In this case the WCET for the read operation is equal to the FIFO depth + 27ck ( read delay presented in Figure 2). For a standard memory use with a classical refresh operation, the WCET is equal to the sum of the write operation delay time and a total refresh time which is defined in Section 3. For example the WCET of the write operation is equal to 35*ck+ total Refresh time = ns µs = µs. We can clearly remark the important impact of our method on the WCET for the write operation, which is reduced to about 3% compared to the WCET of a classical memory driver. 7. CONCLUSION We presented in this work a safe DDR3 memory architecture based on the interleaving (Write/Read) access and on the predictability of refresh operation. With this design, write and read operations are performed simultaneously on different chips. We proposed in this work to use a write technique ensuring indirect memory refreshment. Thanks to a barrel shifter algorithm all the memory rows are refreshed during the write time slot. When the coming address is not free, we

7 should read it and then move it to another address. This memory architecture avoids the memory refresh unpredictability. It is now possible to exactly compute the Worst Case Execution Time (WCET) for each operation without eventual refresh interruption. This value is equal to 35 clock cycles for the write and to ( Fifo depth + 27 ) clock cycles for the read command. Thanks to this technique, the WCET is reduced to 3% for the write access compared to a classical memory design. The memory is now refreshed each ms while the maximum delay refresh time is equal to 64 ms. This rate increases data integrity without reducing the hardware reliability or memory bandwidth. It is clear that the switching activity is increased due to the high frequency of the memory refresh. In the future work we propose to provide the implementation results and to complete power consumption evaluation for this memory controller. 8. REFERENCES [1] D. Darshana et A. K. Sahu, «Implementation of AXI Design core with DDR3 memory controller for SoC,» International Journal of Computer Technology and Electronics Engineering (IJCTEE), vol. 1, n13, [2] P. Guoteng, L. Li, O. Guodong, D. Qiang et Xie Lunguo, «Design and Implementation of a DDR3-based Memory Controller,» Intelligent System Design and Engineering Applications (ISDEA), pp , [3] A. Shabana et K. Kavita, «Design and FPGA Implementation of DDR3 SDRAM Controller for High Performance,» International Journal of Computer Science & Information Technolo, vol. 3, n 14, p. 101, [4] R. K. Vijaykumar, Karunavathi et V. Prakash, «Design of Low Power Double Data Rate 3 Memory Controller with AXI compliant,» International Journal of Engineering and Advanced Technology (IJEAT), vol. 1, n 15, [5] S. Aqueel et K. Khare, «A High Performance DDR3 SDRAM Controller,» International Journal of Electrical and Electronics Engineering (IJEEE), vol. 1, n 11, [6] B.Bhat et F.Mueller, «Making DRAM Refresh Predictable,» nd Euromicro Conference on, pp , 6-9 July [7] B. Akesson, K. Goossens et M. Ringhofer, «Predator: a predictable sdram memory controller,» Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, pp , [8] X. Yang, S. Sezer, J. McCanny et D. Burns, «DDR3 based lookup circuit for high-performance network processing,» IEEE International SOC Conference, pp , [9] Altera, «External Memory Interface Handbook, Volume 2: Design Guidelines,» November [10] JEDEC Solid State Technology Association, «DDR4 SDRAM,» JESD79-4, September [11] Micron, «DDR3 SDRAM Component Data Sheet,» 2009.