Infineon HYB39S128160CT M SDRAM Circuit Analysis

Transcription

1 September 8, 2004 Infineon HYB39S128160CT M SDRAM Circuit Analysis Table of Contents Introduction... Page 1 List of Figures... Page 2 Device Summary Sheet... Page 13 Chip Description... Page 16 Top Level Diagram...Tab 1 Data Path...Tab 2 Address Path...Tab 3 Clocks...Tab 4 Voltage Generators...Tab 5 Row Redundancy...Tab 6 Column Redundancy...Tab 7 Test Mode...Tab 8 Mode Register...Tab 9 Self Refresh...Tab 10 Signal Naming Conventions and Symbol Definitions...Tab 11 Signal Cross-Reference List...Tab 12 For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please contact Sales at Chipworks. Rev. F8.0

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3 Infineon HYB39S128160CT-7.5 2Mx16x4 SDRAM Page 2 List of Figures Package Markings Package X-Ray Pin Configuration Die Markings Die Photograph Annotated Die Photograph Die Architecture Tri-State Driver Definition Tri-State Buffer Definition Symbol Definition Symbol Definition Symbol Definition Symbol Definition Symbol Definition Symbol Definition Symbol Definition Symbol Definition Exclusive-NOR Definition Exclusive-NOR Definition Exclusive-NOR Definition Exclusive-OR Definition Exclusive-OR Definition LATCH-1 Definition LATCH-2 Definition LATCH-3 Definition LATCH-4 Definition MUX-1 Definition MUX-2 Definition MUX-3 Definition MUX-4 Definition

4 Infineon HYB39S128160CT-7.5 2Mx16x4 SDRAM Page MUX-5 Definition MUX-6 Definition CELL-1 Definition CELL-2 Definition Simplified Pipeline Architecture DBSA and Write Driver Architecture Block Decoding Address Bitmap Top Level Diagram Data Path Memory Cell Access Cells and Sense Amplifiers Data Bus Access Data Bus Sense Amplifiers Data Bus Write Driver Quadrant I/O Multiplexer Quadrant Input Demultiplexer Quadrant Output Multiplexer Data Output Switches Data Output Registers Data Output Buffers Data Input Path Data Input Buffer Data Input Latch Data Input Switches X4 Input Switches X8 Input Switches X16 Input Switches Multibit Test Comparator Read Data Line Latches Multibit Test Comparator I

5 Infineon HYB39S128160CT-7.5 2Mx16x4 SDRAM Page Multibit Test Comparator II Address Path Address Input Address Input Buffers Bank Address Buffers Input Buffer (Definition) Address Multiplexer Bank Address Multiplexer Row Address Path Row Address Latch Block Select Block Decoder X-Block Select Sense Clock Drivers Load Unlink Generator Bitline Precharge Generator Row Block Select Row Decoders Row Predecoders Row Factor Driver Master Row Decoder Row Drivers Column Address Path Column Address Multiplexer Column Address Counter Column Address Counter Cell Column Address Counter Cell Column Address Counter Cell Column Address Counter Cell Column Address Counter Cell Column Address Counter Cell Column Address Latch

6 Infineon HYB39S128160CT-7.5 2Mx16x4 SDRAM Page Column Predecoder Column Predecoder Column Predecoder Column Predecoder Column Decoder Data Address Path Data Path Predecoders Data Path Decoders Data Output Switches Controls Data Output Switches Registers Data Output Switches Decoders Data Input Switches Decoders Refresh Counter Refresh Counter Cell Clocks Control Input Buffers {CLK} Buffer Internal Clock Generator {CKE} Buffer {CKE} Register {RAS~} Buffer {CAS~} Buffer {WE~} Buffer {CS~} Buffer {DQM} Buffer DQM Register Buffer Precharge Level Shifters Command Decoder Command Decoder I Command Decoder II Active Cycle Control Active Cycle Initialize

7 Infineon HYB39S128160CT-7.5 2Mx16x4 SDRAM Page Bank Activate Active Cycle Monitor Bank Activate Selection Row Address Load Row Clocks Row Clocks I Block Decoder Enable Row Clock III Row Clocks IV Row Clocks V Sense Monitor Row Predecoder Precharge Column Clocks Bank Selection Column Address Clock Generator Programmable Y Clock Delay Column Predecoder Enable DBSA & Write Driver Enable Data Mask Latches Data Mask for Read/Write Input Multiplexer Clocks Output Multiplexer Clocks Burst & R/W Clocks Burst Counter Reset Burst Length Counter Burst Counter Cell Burst End Latch Read/Write Latches R/W Latch R/W Latch Burst Clocks Read Clock Delayed Data Bus Sense Amplifer Emulator

8 Infineon HYB39S128160CT-7.5 2Mx16x4 SDRAM Page Data Output Read Clocks Pipeline Clocks Latency Counter I Latency Counter Flip Flop Data Output Registers Control Flip Flop Definition A Flip Flop Definition B Flip Flop Definition C Flip Flop Definition D Data Output Switches Clocks Flip Flop Definition E Flip Flop Definition F Latency Counter II Flip Flop Definition G Flip Flop Definition H Data Output Buffer Enable Data Output Path Control Data Output Control Circuitry Voltage Generators VBB Generator VBB Detector VBB Oscillator VBB Clocks VBB Pump Internal VCC Generator Internal VCC Generator I Internal VCC Generator II Internal VCC Regulator Internal VCC Control Sense Voltage Generator Sense Voltage Generator I Sense Voltage Regulator

9 Infineon HYB39S128160CT-7.5 2Mx16x4 SDRAM Page Sense Voltage Control VCP Generator VBLP Generator VBLP Generator I Signal Margin Voltage Generator Signal Margin Decoders VPP Generator VPP Oscillator I VPP Oscillator II VPP Clocks I VPP Clocks II VPP Pump VPP Power-Up Pump VPP Reference Generator VPP Reference Generator I VPP Reference Generator II VPP Regulator VPP Comparator VPP Detector Voltage Reference Generator Bandgap Voltage Generator Programmable Reference Generator Buffer Reference Voltage Generator Bias Voltage Comparator Power-Up Power-Up I Power-Up II Power-Up Sequencer Redundancy Power-Up Redundancy Sequencer Power-Up Level Shifter

10 Infineon HYB39S128160CT-7.5 2Mx16x4 SDRAM Page Row Redundancy Row Redundancy Programming Redundant Row Enable Circuit Redundant Row Predecoders Redundant Master Row Decoder Redundant Row Factor Predecoders Redundant Row Factor Decoder Redundant Wordline Drivers Normal Row Disable Row Redundancy Test Column Redundancy Redundant Column Programming Redundant Column Select RYMFIN~ Latch Column Redundancy Decoder Redundant Column Predecoder Redundant Column Driver Normal Column Disable Test Modes Test Mode Decoders Test Register Set Test Mode Reset Programmable Fuses Programmable Fuses I Programmable Fuses II Programmable Fuses III Test Mode Registers Test Mode Register Test Mode Register Test Mode Register 3

11 Infineon HYB39S128160CT-7.5 2Mx16x4 SDRAM Page Test Mode Register Test Mode Register Test Mode Registers Test Mode Register Second Stage Test Mode Registers Second Stage Test Mode Registers I Second Stage Test Mode Registers II Second Stage Test Mode Registers III Test Bank Address Generator Self Test Engine Pin Test Sequencer Flip Flop I Flip Flop II Test Mode Address Load Register Pin Test Address Latch Test Address Latch Test Mode Data Pattern Generator Test Mode Multiplexers I Test Mode Multiplexer II Test Mode Address Scrambler I Test Mode Address Scrambler II Test Latches Test Mode Latches I Test Mode Latches II Test Mode Latches III Test Mode Address Output Test Mode Address Output Multiplexers Test Mode Address Output Driver Test Mode Control Test Mode Control Test Mode Control Test Mode Control Test Mode Control 4

12 Infineon HYB39S128160CT-7.5 2Mx16x4 SDRAM Page Test Mode Control Test Mode Control Test Mode Control Test Mode Data Input Path Test Mode Data Input Latch Test Mode Address Scrambler Test Mode 4:1 Multiplexers External VCP, VREF4 and VSP Test Mode Self Refresh Timer Output Test Configuration Option Signature Circuit Test Mode Circuitry Mode Register Mode Register Set Mode Register Cells Burst Length Decoder Self Refresh Self Refresh Timer Self Refresh Timer Cell Self Refresh Pulse Generator Self Refresh Oscillator Self Refresh Latch Self Refresh Control A.1.0 Symbol Conventions - 1 A.1.1 Symbol Conventions - 2 A.1.2 Symbol Conventions - 3 A.2.0 Symbol Definitions - 1 A.2.1 Symbol Definitions - 2 A.2.2 Symbol Definitions - 3 A.2.3 Symbol Definitions - 4 A.2.4 Symbol Definitions - 5

13 Infineon HYB39S128160CT-7.5 2Mx16x4 SDRAM Page 12 A.2.5 Symbol Definitions - 6 A.2.6 Symbol Definitions - 7 A.3.0 Logic Gate Size Notation A.4.0 Transistor Size Notation A.5.0 Capacitor Size Notation