AMDC 2017 Liviona Multi-Core in Automotive Powertrain and Next Steps Towards Parallelization

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1 Bitte decken Sie die schraffierte Fläche mit einem Bild ab. Please cover the shaded area with a picture. (24,4 x 11,0 cm) AMDC 2017 Liviona Multi-Core in Automotive Powertrain and Ralph Mader, 25. April Powertrain Division

2 Next Steps Towards Parallelization Powertrain Application Multi-Core Approach Today Challenges Next Generation Example Implementation Outlook 2

3 Powertrain Application Where is Multi-Core in Use? Domain Controller Combustion Engine Transmission Control HV Inverter DC/DC Converter 3

4 Interior Chassis Powertrain Powertrain Application Challenges: Complex Mechatronic with Hard Real-Time Two times bases, hard deadlines, complex control systems, strict sequences Soft Real- Time Hard Real- Time timedriven eventdriven timedriven event + angledriven Combustion Engine Transmission/ Electric Motor EBS ADAS/Safety Body Control Battery Control Airbag Body EBS DCT EVC EMS Runables Tasks Interrupts 4

5 RoHR [kj/ crk] Noise [db(a)] PM [g/h] Powertrain Application Experience: High Precision Example Injection Pattern Impact of accuracy control for dwell and minimum fuel mass to emissions Optimal Missed by 50 µs crank angle [ ] RoHR Noise NOx [g/h] Emission at n= 1500 min -1, p mi = 4,2 bar, HR50= 8 KW, EGR=35% 5

6 Next Steps Towards Parallelization Powertrain Application Multi-Core Approach Today Challenges Next Generation Example Implementation Outlook 6

7 Multi-Core Approach Today Micro Controller Architecture 2.5M Flash 200MHz 4-8MFlash 300MHz Core 0 + local RAM Core 1 + local RAM Core 0 + local RAM Core 1 + local RAM Core 2 + local RAM Crossbar Crossbar Peripherals System RAM Program Flash Peripherals System RAM Program Flash All used controllers have sufficient shared ram memory for code and data Software architecture has to be scalable for different numbers of cores 7

8 IF s Multi-Core Approach Today Static Architecture OEM-ASW AR based Continental- ASW AR based OEM-ASW Non AUTOSAR Continental- ASW Non AUTOSAR Legacy Engine Drivers (CDD) Multi Core PDA Layer RTE (RIPS) OS System Services Memory Stack Communication Stack Legacy IF IO HW abstraction Powersar CDD s Microcontroller Abstraction - Drivers Multi-Core Microcontroller Architecture has to support different types of software AUTOSAR and Non AUTOSAR from different sources! 8

9 Multi-Core Approach Today e.g. Infineon AURIX TC27x Rules for assignment Core allocation frame As much freedom as possible for core allocation Fixed allocation only where really necessary A0: High Safety SW A0* ASW + High Safety (close link to Drivers) A1 ASW mainly angle sync A2 ASW mainly time sync A1-Ax: used for mainly for low safety ASW RTE/OS IO and Service Interfaces RTE/OS IO and Service Interfaces RTE/OS IO and Service Interfaces Startup/Shutdown IO Driver Kernels >= ASIL B IO Driver Kernels <= ASIL A* IO Driver Kernels < =ASIL A* ASW, BSW, RTE and OS have to be prepared for Multi Core, Event Chains have to be identified and specified! 9

10 Powertrain Application The Problem Core Core A0 A0 Core A0 Core A1 Core A2 A highly cohesive system How to implement the inter core communication in an efficient way? 10

11 Multi-Core Approach Today Data consistency Consistency need Requirements Buffer Implementation Consistency requirement available Execution model shows risk of concurrent access Software is protection ready Task R 1 R 2 R 3 Task individual buffer R 4 R 5 R N Buffer will be established Global Data RAM Fill buffer Flush buffer Concept bases on the specification of explicit needs for data consistency on module level. This ensures a good reuse across projects! 11

12 Run1 Run2 Run3 Run4 Partition 0 Run5 Run6 Partition 1 Multi-Core Approach Today RIPS Example: Implicit Communication Rte_IRead IOC Channel IOC Channel Task_A1 Task_A2 Task_A3 Task_B1 Task_B2 OsApplicationA OsApplication B Core 0 Core 1 RTE Loosely coupled application RIPs Access to data (By connector RTE- Generator) (By RTE- Generator) RTE Implementation PlugIn (By Domain Specific Tool) Task individual buffer Task R 1 R 2 R 3 R 4 R 5 Global Data RAM R N Fill buffer Flush buffer Engine application return RTE RTE Task 1 Task 2 Task 3 Task 1 Task 2 Task 3 * Brake application Ring Buffer Conti RIPs concept allows alternative buffer behavior transparent for the AUTOSAR SW Component 12

13 Multi-Core Approach Today Distribution by tasks and runnable sequences Timing and Data flow model including Runtime of Runnables (GLIWA T1) Dataflow Task model Deadlines Model of Consistency mechanism Multi Dimensional Optimization For best Scheduling, Load, Dataflow Optimum selection according to metrics Implementation by Project Architect Deriving core affinity rules 13

14 Multi-Core Approach Today Scheduling For legacy code Chained System-Event => Sequential execution Task_A0_10ms i + Calculation order kept + Easy data consistency - Long Response time Task_A1_10ms Task_A2_10ms For parallel code Parallelized System-Event => Concurrent execution Task_A0_1ms Task_A1_1ms + Short Response time Task_A2_1ms - Task order not ensured - Data interactions 14

15 Multi-Core Approach Today Integration of software with respect to dynamic behavior Runtime Data Runnables Interrupts Tasks Call frequency Dynamic integration needs System Event and Phase Data Consistency Sequencing Core Affinity SW structural info call tree data accesses data types Analysis Design and Optimization tool Sequencing with 3 rd Party SW Scheduling simulation Core distribution Model Integration Tool RunIn Dynamic Integration RTE Generator (Event to task mapping) PowerSAR Multi- Core Layer (Buffer and Data Access Modification code) Model/Code Generation 15

16 Multi-Core Approach Today Example Application Result of Optimization with TA Optimizer on 4 Cyl. SDI with VVLI CPU-Load Over Engine Speed - Before CPU-Load Over Engine Speed - After A0 A1 A A0 A1 A AURIX TC27x 3x200MHz 16

17 Next Steps Towards Parallelization Powertrain Application Multi-Core Approach Today Challenges Next Generation Example Implementation Outlook 17

18 Challenges Next Generation Micro Controller Architecture Map 1 st Generation ECU14 2 or 3 cores 2 nd Generation ECU17 3 to 6 cores 3 rd Generation ECU22 Many Core Homogenous Heterogeneous 3 Cores 2 Cores Since ECU14 Multi Core is the Market Standard. For ECU17 Platform only Multi Core controllers are in the portfolio Question is, what comes next?? 18

19 Challenges Next Generation Limitation in terms of parallelism Today: 60% Parallelism Target: 80% Parallelism 2ms 2ms 2ms 1.5ms 1.5ms 1.5ms 1.5ms 4ms 10ms 4ms Theoretical performance increase from 3 to 4 cores: 1.67 to % Amdahls Law No. of cores P 1 P 0.9 P 0.8 P 0.7 P 0.6 P 0.5 P 0.4 P 0.3 P 0.2 Functions to be designed for parallelism!! 19

20 Challenges Next Generation The Problem 10ms Sequence Bottom up approach when analyzing the code Corse grain Fine grain intrinsic for ( i = 0; i < NoOfCylinder; { } i++ ) /* do some small calculation */ 20

21 Powertrain Application Search For The Parallelism Top Down Analyze the Problem to be solved. Design for parallel execution. Speed Up Parallelisation for speed up Bottom Up Analyze the existing code. Propose parallelization based on data flow. Loops are often to short to allow efficient parallelization. Speed Up 21

22 Next Steps Towards Parallelization Powertrain Application Multi-Core Approach Today Challenges Next Generation Example Implementation Outlook 22

23 Example Implementation Dependencies in State Transitions 23

24 Example Implementation Core Synchronous State Transitions A2 A1 A2 A1 Task A Task C Task B Task D Transition Transition Task F Task D 1 State Transition triggered 2 Wait until all currently executed tasks are finished 3 State Transition performed e.g. turn on ignition A0 A0 Task E Transition 4 State Transition done. System is released. Time Speed Up During Transition Nearly 3 24

25 Example Implementation Dependencies in Recurrently Executed Software R11 R21 R31 R12 R23 R33 R34 25

26 Example Implementation Logical Execution Time (LET) Approach LET 1 LET 2 LET 3 A2 R31 R33 R34 A1 R21 R23 A0 R11 R12 Speed Up Significant and Combination of Parallel and Sequential Execution Possible Time 26

27 Next Steps Towards Parallelization Powertrain Application Multi-Core Approach Today Challenges Next Generation Example Implementation Outlook 27

28 Outlook Involvement in Present Funded Research Projects Architecture description for parallel execution Embedded real-time pattern catalogue Multi-Core and Many-Core Dynamic scheduling approaches in mixed critical systems Gefördert durch die Bayerische Forschungsstiftung Seamless Multi-Core oriented development approach Multi-Core methods and tools Analytical methods to determine degree of parallelism in applications Hardware support of scheduling mechanisms Time determinism Gefördert vom Bundesministerium für Bildung und Forschung Förderkennzeichen 01IS16025T Still some work to be done to make parallel design easy applicable in this domain 28

29 Discussion Questions? 29

30 Thank you for your attention! 30