PREEvision at Porsche (Update 2018)

Transcription

1

2 PREEvision at Porsche (Update 2018) Markus Kühl EEY2 2/26

3 Agenda 1 2 Overview (Porsche Update 2018) Continuous Integration and Design Traceability by combining logical and software architecture Use of Logical Porsche From functional concepts to signal communication requirements 3 From Logical to Software Architecture Enabling Autosar Development for highly integrated ECUs 4 Summary & Outlook 3/26

4 Where we came from (see VeCo 2014 presentation) Use cases of Porsche Modeling tool for highly specialized E/E Architecture tasks, e.g. Development of Functional Architectures for Porsche specific functions Analysis of resulting impacts on networking, interfaces and devices Network Topology Development Process Documentation of feature-function oriented wiring harnesses Compatibility Analysis (e.g. ECU interfaces vs. K-Matrix) Feature Oriented Release Management (e.g. ECU used by feature) 4/26

5 Porsche in 2018 Rollout as modeling tool to Porsche Development Departments for logical (functional) architecture design purposes in a new E/E Architecture generation Software Architecture Development Tool (Autosar) for High Performance Cluster ECU PREEvision is now highly integrated into our function-oriented development process 5/26

6 Todays Presentation Focus Layer Architecture as of PREEvision 9.0 Requirements Feature List LA Freeze Logical Architecture Software Architecture Release SWA Technical Architecture Communication Layer & API 6/26

7 From Feature to Logical Architecture 7/26

8 Identification of Logical Function Blocks Identification of function blocks is a manual process done with help of deeper investigations (paper or tool + simulation based using SysML diagrams upcoming in PREEvision 9.0ff) Draft Concept of a car feature Logical Function Block as core items of a car feature Car Feature under Development M Function Block1 Function Block2 Hierarchy Sub Function Block 1-n Function Block Owner 1 Function Block Owner 2 Function Block Owner 1 Feature Owner x 8/26 Feature List

9 Identification of Logical Function Blocks Referenced function blocks or services Car Feature under Development Logical Function Block as stakeholder functions or services Clamp Control Energy Manager Service Smart Actuator Function Block Function Block1 Function Block2 Hierarchy Sub FunctionBlock 1-n HMI Subfunction Connect Backend Subfunction 9/26

10 2. Logical Architecture by Example On-board Service Logical Hierarchy Logical Functional Block (Concept C) Logical Function Block (Compute Layer) Backend Service 10/26 Logical Functional Block (Sens/Act Layer) Physical Values (Sens/Act)

11 Interface Specification 11/26

12 2. Technical Architecture (Mapping of Logical Functions -> Topology) Offboard Computational Layer Offboard System x Offboard System y M Connect Backend Subfunction Connectivity Unit Performance Layer Performance Computer 1 M Function Block1 Function Block1 Performance Computer 2 M Performance Computer 3 Clamp Control Energy Manager Service Performance Computer 4 Smart Device Smart Device & Actuator Layer M Smart Device Smart Actuator Function Block Smart Device 12/26

13 Communication Analysis Offboard Computational Layer Offboard System x Offboard System y M Connect Backend Subfunction Connectivity Unit Performance Layer & Actuator Layer Performance Computer 1 Signal Communication M Smart Device Smart Device Function Block1 Function Block1 M Service & Classic Communication Smart Actuator Function Block Performance Computer 2 Performance Computer 3 Smart Device Performance Computer 4 within PREEvision are exported to SBT / Busnet. M Clamp Control Energy Manager Service Signal Voting Process and Communcation Design are Smart Device done in an external tool chain today (SBT/Busnet). Function Blocks and Interface Specification finally approved Voting State and final Communication Matrix are synced back to PREEvision 13/26

14 How to derive Software Architecture from Logical Architecture Logical Architecture is in our approach focused on the development of an end-2-end architecture of all car functions to be integrated. Activity chains therefore are used to model a certain car function from data acquisition (e.g. sensor, computed data from 3 rd party car function or backend systems) to one or more final logical block (e.g. HMI, other function blocks) Besides certain common design processes (e.g. communication matrix & Service API design, analysis processes like functional safety, timing path) we make use of LA function blocks that are mapped to one electronic control unit (e.g. Performance Computer) to generate core parts of the Software Architecture for the device under development. Patterns used to generate & synchronize SWA from LA: Single Function Block conversion to single Atomic Software Component (SWC) Multiple Function Block conversion merged to one Atomic SWC One Function Block conversion to two Atomic SWC Additional Autosar SWA aspects are manually modeled in SWA layer or generated via metrics (e.g. Internal Behavior, Service Needs, Diagnostic Data) 14/26

15 LA > SWA Conversion Pattern by Example external logical function block Logical Function Block Logical Function Block (Compute (Compute Layer) ECU1) Logical Functional Block (discrete ECU1) external logical funtion block Step 1: Execute model consistency check Logical Functional Block ECU1 Sens/Act Layer) Step 2: Identify logical function blocks for conversion, create Atomic SWC for each conversion Step 3: Transfer ports from logical function blocks to SWC (creation of technical interfaces) Step 4: Convert external ECU communication into Composition Delegation Ports Step 5: Connect compatible interfaces 15/26

16 LA > SWA Conversion Pattern by Example M 16/26

17 LA > SWA Conversion Pattern by Example M M 17/26

18 LA > SWA Conversion Pattern by Example M 18/26

19 LA>SWA Block Merge Conversion (Step 2, after Model Check Step 1) LA Layer n:1 SWA Layer 1:1 19/26

20 LA>SWA Block Merge Conversion (Step 3) LA Layer A SWA Layer A 20/26

21 LA>SWA Block Merge Conversion (Step 4 Assembly Connector + Structure) External Communication = Delegation Port (tagged) Discrete IO = Delegation Port (tagged) + 21/26

22 How things come together t Feature List Logical Architecture Technical Architecture Com & API Software Architecture FB Feature x Feature AM Freeze 1 AM2 AM3 CM Freeze 1 CM2 CM3 Com + API FB FB FB Function Blocks 22/26 SWA Freeze 1 SWA2 SWA3 SWA4

23 Concurrent Development & Continuous Integration LA>SWA Continuous LA Development ongoing LA Freeze 1.e LA Freeze 1.i LA Freeze 2.e LA Freeze 2.i External Interface Freeze Internal Interface Freeze External Interface Freeze Internal Interface Freeze Logical Architecture Dev. LA Block(s) 1st Reuse Check-In External Interface Approval (SBT) & Comm Dev. LA Block(s) 2nd Reuse Check-In Internal Interface COM Release 1 SWA Modeling LA>SWA Conversion Product Line ECU1 [Freeze 1] ARXML SysDesc ARXML ECU Ex Release Bundle Product Line Reuse + Branch LA Block(s) Approval (SBT) & Comm Dev. LA Block(s) 1st Reuse 2nd Reuse LA>SWA Check-In Check-In Conversion External Internal Interface Interface Product Line ECU1 [Freeze 2] Communcation & ServiceAPI Dev. Software Architecture Dev. 23/26 Product Line ECU1 [Freeze 1 NI]

24 Approval Process Lifecycle for Logical Function Blocks [Edit] -> all Under Development Function Owner Domain Architect EE Architect [Edit] -> Domain Architect, EE Architect Development Finished Domain Architect Domain Architect EE Architect [Edit] -> Domain Architect, EE Architect In Approval (Domain Architect) LA>SWA Internal Interface Freeze Function Owner Domain Architect EE Architect EE Architect EE Architect Domain Architect EE Architect approved (Domain Architect) LA>SWA External Interface Freeze Released (EE Architecture) [Edit] -> EE Architect EE Architect In Approval (EE Architecture) [Edit] -> EE Architect EE Architect [Edit] -> EE Architect 24/26 Transition: Roles able to switch Lifecycle State [Block/Port Edit] -> Roles allowed to edit function blocks, ports and interfaces

25 Summary & Outlook Successfully introduced function oriented development process on top PREEvision utilizing Logical Architecture concepts Communication interfaces (signals..) specified in PREEvision, but approval process and communication design is still carried out in an external tool chain Autosar Design Process for one of our Performance ECUs in close loop with development of logical architecture Next steps: Optimize Autosar Design flow with introduction of Explorer based Editors Introduce SysML notation / methods especially in early design phases (PV9.0ff) Formalization of function block & interface approval process within PREEvision (Vote & Review) Integration of approval process for communication interfaces in existing tool chain Implementation of Viewer Web-Apps for quick model access 25/26

26 Thanks for you attention! 26/26