FASTER DAQ Network May 16th 2018 Clermont-Ferrant
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1 FASTER DAQ Network May 16th 2018 Clermont-Ferrant Carniol Benjamin, Chaventré Thiérry, Cussol Daniel, Etasse David, Fontbonne Cathy, Fontbonne Jean-Marc, Harang Julien, Hommet Jean, Langlois Jérome, Poincheval Jérome 1
2 FASTER-V2 1. FASTER OVERVIEW 2. FASTER REAL TIME ALGORITHMS 3. FASTER SOFTWARE 4. MASTER BOARD FASTER-V3 1. MMC (FASTER_V2) 2. CLOCK 3. PROTOCOL 4. PROCESSOR MANY CORES 5. CONCLUSION DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 2
3 Offline Analysis Real Time Algorithms RHB buntu repository Modular Electronic Based on Root DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 3
4 STANDALONE SYSTEM MULTI-CHANNEL SYSTEM 1 VITA 57 slot, 1 FPGA (C5 140 LE) 1 Gb/s Ethernet FPGA firmware loading by Ethernet 2 VITA 57 slots, AMC.2 full size module, 3 FPGA(s) (C5 140 LE) 1 and 10 Gb/s Ethernet 10 MHz Clock synchronization DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 4
5 STANDALONE SYSTEM MULTI-CHANNEL SYSTEM 4 FADC (125MHz@14bits) 2 FADC (500MHz@12bits) DDC316 from TI ISEG BPS-Serie - 4W FMC project (CERN) ±1V, ±2V, ±5V, ±10V input range ±1V input range 32 channels ± 500 V to ± 6 KV 5 I/O ports 25 MHz Bandwidth ±1V input adjustable Offset I-TO-V conversion front end 200 MHz Bandwidth 100 MHz Bandwidth 3pC to 12 pc (full scale) Integration time range from 10us to 10 ms LVTTL DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 5
6 FASTER-V2 1. FASTER OVERVIEW 2. FASTER REAL TIME ALGORITHMS 3. FASTER SOFTWARE 4. MASTER BOARD FASTER-V3 1. MMC (FASTER_V2) 2. CLOCK 3. PROTOCOL 4. PROCESSOR MANY CORES 5. CONCLUSION DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 6
7 FASTER-CRRC4 FASTER-TRAPEZ-TDC Time resolution VS signal amplitude FASTER-QDC-TDC HR FASTER-RF FASTER-SCALER FASTER-SAMPLER FASTER-ELECTROMETER FASTER_HV 60 Co Demon detector, CARAS board, FASTER-QDC-TDC HR HPGe detector, MOSAHR board, FASTER_ADC DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 7
8 FASTER-V2 1. FASTER OVERVIEW 2. FASTER REAL TIME ALGORITHMS 3. FASTER SOFTWARE 4. MASTER BOARD FASTER-V3 1. MMC (FASTER_V2) 2. CLOCK 3. PROTOCOL 4. PROCESSOR MANY CORES 5. CONCLUSION DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 8
9 Offline Analysis Ubuntu (production)-> (Dev) LTS 64 bits ADA and Python Software trigger (multiplicity or Boolean trigger) 5.10^6 measurement/s per computer (~100 MB/s) Faster repository on LPC Server sudo apt_get install fasterv2 Update the software and the FIRMWARE at the same time Offline analysis package List of available packages fasterv2, fasterac, rhb, faster-rhb-xxx-demo (xxx=qdc, crrc4, trapez, rf, ) buntu repository DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 9
10 FASTER-V2 1. FASTER OVERVIEW 2. FASTER REAL TIME ALGORITHMS 3. FASTER SOFTWARE 4. MASTER BOARD FASTER-V3 1. MMC (FASTER_V2) 2. CLOCK 3. PROTOCOL 4. PROCESSOR MANY CORES 5. CONCLUSION DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 10
11 Time sort function Introspection data DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 11
12 MASTER - Cyclone MB DDR3-1 Gbe - 12 unsorted data streaming -> 1 sorted data streaming DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 12
13 FASTER-V2 1. FASTER OVERVIEW 2. FASTER REAL TIME ALGORITHMS 3. FASTER SOFTWARE 4. MASTER BOARD FASTER-V3 1. MMC (FASTER_V2) 2. CLOCK 3. PROTOCOL 4. PROCESSOR MANY CORES 5. CONCLUSION DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 13
14 MMC IN2P3 - Damien TOURRES (LPSC) - ATMEGA128 GASPARD-TRACE Meeting 2018, Alternative BEE option, David Etasse 14
15 FASTER-V2 1. FASTER OVERVIEW 2. FASTER REAL TIME ALGORITHMS 3. FASTER SOFTWARE 4. MASTER BOARD FASTER-V3 1. MMC (FASTER_V2) 2. CLOCK 3. PROTOCOL 4. PROCESSOR MANY CORES 5. CONCLUSION DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 15
16 T0 20 MHz Common signal T0 CALIBRATION INHIBIT 10 MHz Clock T0 20 MHz Register Common signal 10 MHz Clock Common signal White Rabbit DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 16
17 FASTER-V2 1. FASTER OVERVIEW 2. FASTER REAL TIME ALGORITHMS 3. FASTER SOFTWARE 4. MASTER BOARD FASTER-V3 1. MMC (FASTER_V2) 2. CLOCK 3. PROTOCOL 4. PROCESSOR MANY CORES 5. CONCLUSION DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 17
18 FASTER-V2 Slow Control -> ETHERNET -> UDP/IP -> FASTER PROTOCOL DATA -> ETHERNET -> UDP/IP -> FASTER PROTOCOL FASTER-V3 Slow Control -> ETHERNET -> UDP/IP -> IPBUS PROTOCOL DATA -> ETHERNET ->????? DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 18
19 FASTER-V2 1. FASTER OVERVIEW 2. FASTER REAL TIME ALGORITHMS 3. FASTER SOFTWARE 4. MASTER BOARD FASTER-V3 1. MMC (FASTER_V2) 2. CLOCK 3. PROTOCOL 4. PROCESSOR MANY CORES 5. CONCLUSION DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 19
20 KALRAY MPPA COOLIDGE - 600/900/1200 MHz frequency modes - 5 or 10 Compute Cluster - 4 MB -> 1 Cluster (20/40 MB) - 16 CPU cores 64 bits -> 1 Cluster - 80 or 160 CPU cores - 3 or 6 TFLOPS - 2 * 100 Gbe (x->10gbe, y->1gbe, w-> 40Gbe) - 2 * 8 lane PCIe Gen W / 5-30 W DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 20
21 Time sort function Introspection data DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 21
22 Introspection data DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 22
23 DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 23
24 FASTER-V2 1. FASTER OVERVIEW 2. FASTER REAL TIME ALGORITHMS 3. FASTER SOFTWARE 4. MASTER BOARD FASTER-V3 1. MMC (FASTER_V2) 2. CLOCK 3. PROTOCOL 4. PROCESSOR MANY CORES 5. CONCLUSION DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 24
25 FASTER is a digital modular acquisition system from the electronic front end to the histogram builder software developped at LPC. FASTER is very easy to install, to use with great performances. FASTER is able to perform the main nuclear functions with a set of hardware very reduced. FASTER is wireless. FASTER is designed to handle medium size experiment (from one to few hundred channels). FASTER is used in 10 Countries (More 60 FASTER systems has been manufacturing) FASTER-v3 will be designed to handle large size experiment (from one to few thousand channels). FASTER-v3 will be able to manage many TFLOPS in a small system. FASTER-v3 will be compatible with a DAQGEN system DAQ Network May 16th 2018, Clermont-Ferrant, David Etasse 25
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