Xilinx 7 Series FPGA Power Benchmark Design Summary
|
|
|
- Dinah Leonard
- 5 years ago
- Views:
Transcription
1 Xilinx 7 Series FPGA Power Benchmark Design Summary June 1 Copyright 1 1 Xilinx Xilinx
2 Application-centric Benchmarking Process 1G Packet Processor OTN Muxponder ASIC Emulation Wireless Radio & Satellite Modem Edge QAM AVB Switcher Military Radio Mobil Backhaul FPGA resource counts, toggle rates, clock speeds Xilinx Power Estimator (XPE) version 1 MAX condition used to estimate worst-case static power XPE Competitor s Estimator Early Power Estimator (EPE) versions 1 MAX condition used to estimate worst-case static power
3 s Interlaken Traffic Management Interlaken s Power Benchmark: Traffic Manager in 1G Line Card Virtex-7 X69T FPGA x Interlaken SDRAM Interlaken 3 5 NPU Backplane Interface Environment Tj = 1 C Process Virtex -7 X69T -LE Stratix V 5SGXA7 I-Grade 6K 8 x 3-bit 5-16 Mb/s Interlaken Gb/s LC/LEs 3K 167K Kb DSP Blocks PLLs 8 Core Freq 5 MHz *Design results sourced from Xilinx Power Estimator (XPE) version 1 and Altera Early Power Estimator (EPE) version 1 Page 3
4 s 1G EFEC OTU- Framer 1GE Mapper s Power Benchmark: 1GE over OTU Transponder Virtex-7 X69T FPGA 1G OUT- Optical Module OTL1 1X1118G CAUI 1G OUT- Optical Module x Overhead Processing 1GE Clients Overhead bus Environment Tj = 1 C Process Virtex -7 X69T -LE Stratix V 5SGXA7 I-Grade 6K LVCMOS 5-5 Mb/s GT Gb/s GT Gb/s LC / LEs Core Freq 39K 5K 9,36 Kb 35, 175 MHz *Design results sourced from Xilinx Power Estimator (XPE) version 1 and Altera Early Power Estimator (EPE) version 1 Page
5 Power Benchmark: ASIC Prototyping Virtex-7 FPGA T 6 x Virtex -7 T -LE Stratix V EEB (x) I-Grade x 95K Environment Process Tj = 1 C LC / LEs 1,K 3 6-bit Mb/s LVDS 8-1 Mb/s Core Freq 765 K 1,6 Kb MHz *Design results sourced from Xilinx Power Estimator (XPE) version 1 and Altera Early Power Estimator (EPE) version 1 Page 5
6 Channel Encoder QAM DeMod MIMO Decoder OFDM Demod Layer 1/ API DUC / DDC Channel Encoder QAM DeMod MIMO Modulator OFDM Modulator Power Benchmark: Wireless WCDMA / LTE Picocell Kintex-7 35T FPGA x GbE 6 MB 6 MB DAC 1 1 PCIe ADC MicroBlaze Processor Kintex -7 35T -1I Stratix V 5SGXA -I K 6 MB 3 x 16-bit Mb/s GT - Gb/s GT Gb/s GT Gb/s *Design results sourced from Xilinx Power Estimator (XPE) version 1 and Altera Early Power Estimator (EPE) version 1 Environment Process Tj = 1 C LC / LEs K 15K 1,56 Kb DSP Blocks 3 PCIe Blocks 1 Core Freq 37 MHz Page 6
7 1G Network Interface s 1 Gig EMAC FIFO J83 Annex A/B/C Modulator FIFO RRC Filter Digital Up Converter Dense Edge QAM Modulator Kintex-7 35T FPGA x RF DAC IF 6 Gigasample 1-bit DAC Kintex -7 35T -LE Stratix V 5SGXEA -3I 36K External External Memory Memory LVDS Mb/s LVCMOS 1-15 MHz x 8-bit 55-8 Mb/s GT Gb/s 18 Channels RF Port #1 Environment Process Tj = 1 C LC / LEs 18K 157K 1, Kb DSP Blocks 61 Core Freq 38, 576,156, 19, MHz *Design results sourced from Xilinx Power Estimator (XPE) version 1 and Altera Early Power Estimator (EPE) version 1 Page 7
8 SD / HD / 3G Receive Interface Frame Buffer Control / Frame Sync Chroma Keyer Mixes, Wipes, Effects SD / HD / 3G Transmit Interface Power Benchmark: AVB Switcher Kintex-7 35T FPGA 16 11x SDRAM SD/HD/3G Inputs 1 8 SD/HD/3G Outputs Kintex -7 35T -LE (9V) Arria V 5AGXB3 I-Grade 36K 3 x 7-bit 5-8 Mb/s GT Gb/s Environment Tj = 1 C LC / LEs Process 3K 188K 1,8 Kb DSP Blocks 5 Core Freq 185 MHz *Design results sourced from Xilinx Power Estimator (XPE) version 1 and Altera Early Power Estimator (EPE) version 1 Page 8
9 SD / HD / 3G Receive Interface Frame Buffer Control / Frame Sync Chroma Keyer Mixes, Wipes, Effects SD / HD / 3G Transmit Interface AVB Switcher (-channel) Artix-7 1T FPGA DDR /3 SDRAM 5 13x SD/HD/3G Inputs * SD/HD/3G Outputs * Control Interface *Note: SD/HD/3G inputs and outputs share GTs 1 Artix -7 1T -LE (9V) Cyclone V 5CGXC7 C-Grade 19K 1 x 6-bit 11-8 Mb/s GT - 97 Gb/s Environment Process Tj = 85 C LC / LEs 75K 7K,5 Kb DSP Blocks 15 PLL 1 Phaser Block 1 Core Freq 185, MHz *Design results sourced from Xilinx Power Estimator (XPE) version 1 and Altera Early Power Estimator (EPE) version 1 Page 9
10 s s Power Benchmark: Single Channel Mobile Backhaul Artix-7 T FPGA x Control Plane Processor Ethernet Switch Traffic Management, Packet Processing Timing Synchronization Modem SRAM 3 Environment Process 1 Tj = 1ºC Artix -7 T I-Grade Arria V 5AGXA5 I-Grade 19K LC / LEs 13K Interfaces s GTs Rate Flip Flops 81K 1 x 3-bit 7-8 Mb/s 5,76 Kb LVDS pairs 18-8 Mb/s DSP Blocks 35 SEIO 15-1 Mb/s PLL Switch ports - 1 Gb/s Core Freq 5, MHz *Design results sourced from Xilinx Power Estimator (XPE) version 1 and Altera Early Power Estimator (EPE) version 1 Page 1
11 Power Benchmark: Satellite Modem Artix-7 1T FPGA 1 1 1x 1x Environment Process Artix -7 1T -LE (9V) Cyclone V 5CGEA7 I-grade 15K Tj = 85 C LC/LEs 85 K 5 K 3 Kb DSP Blocks 16 PLLs 1x 3-bit DDR 69-5 Mb/s Core Freq 3, 65, 15 MHz *Design results sourced from Xilinx Power Estimator (XPE) version 1 and Altera Early Power Estimator (EPE) version 1 Page 11
12 Military Network Protocol Platform Data Aggregator Artix-7 T FPGA 7 13x Artix -7 T -LE Arria V 5AGXA5 C-Grade 19K x 36-bit RLDRAMs 1-5 Mb/s GT Gb/s GT Gb/s GT Gb/s Environment Process Tj = 85 C LC / LEs 63K Flip Flops 58K 36 Kb DSP Blocks PCIe Blocks 1 Core Freq 15 MHz *Design results sourced from Xilinx Power Estimator (XPE) version 1 and Altera Early Power Estimator (EPE) version 1 Page 1
Field Programmable Gate Array (FPGA) Devices
Field Programmable Gate Array (FPGA) Devices 1 Contents Altera FPGAs and CPLDs CPLDs FPGAs with embedded processors ACEX FPGAs Cyclone I,II FPGAs APEX FPGAs Stratix FPGAs Stratix II,III FPGAs Xilinx FPGAs
Industry s Highest Bandwidth FPGA Enables World s First Single-FPGA Solution for 400G Communications Line Cards
White Paper: Virtex-7 Family WP385 (v1.0) November 17, 2010 Industry s Highest Bandwidth FPGA Enables Wld s First Single-FPGA Solution f 400G Communications Line Cards By: Greg Lara To address the insatiable
Simplifying FPGA Design for SDR with a Network on Chip Architecture
Simplifying FPGA Design for SDR with a Network on Chip Architecture Matt Ettus Ettus Research GRCon13 Outline 1 Introduction 2 RF NoC 3 Status and Conclusions USRP FPGA Capability Gen
High Capacity and High Performance 20nm FPGAs. Steve Young, Dinesh Gaitonde August Copyright 2014 Xilinx
High Capacity and High Performance 20nm FPGAs Steve Young, Dinesh Gaitonde August 2014 Not a Complete Product Overview Page 2 Outline Page 3 Petabytes per month Increasing Bandwidth Global IP Traffic Growth
Adapter Modules for FlexRIO
Adapter Modules for FlexRIO Ravichandran Raghavan Technical Marketing Engineer National Instruments FlexRIO LabVIEW FPGA-Enabled Instrumentation 2 NI FlexRIO System Architecture PXI/PXIe NI FlexRIO Adapter
Ettus Research Update
Ettus Research Update Matt Ettus Ettus Research GRCon13 Outline 1 Introduction 2 Recent New Products 3 Third Generation Introduction Who am I? Core GNU Radio contributor since 2001 Designed
EITF35: Introduction to Structured VLSI Design
EITF35: Introduction to Structured VLSI Design Introduction to FPGA design Rakesh Gangarajaiah Rakesh.gangarajaiah@eit.lth.se Slides from Chenxin Zhang and Steffan Malkowsky WWW.FPGA What is FPGA? Field
The WINLAB Cognitive Radio Platform
The WINLAB Cognitive Radio Platform IAB Meeting, Fall 2007 Rutgers, The State University of New Jersey Ivan Seskar Software Defined Radio/ Cognitive Radio Terminology Software Defined Radio (SDR) is any
Basic FPGA Architectures. Actel FPGAs. PLD Technologies: Antifuse. 3 Digital Systems Implementation Programmable Logic Devices
3 Digital Systems Implementation Programmable Logic Devices Basic FPGA Architectures Why Programmable Logic Devices (PLDs)? Low cost, low risk way of implementing digital circuits as application specific
I.6 40G LDPC Encoder/Decoder IP Core Specifccaton
I.6 40G LDPC Encoder/Decoder IP Core Specifccaton I.6 40G LDPC Encoder/Decoder IP Core Relecase Informcaton Fecatures Delivercables IP Core Structure I.6 40G LDPC Encoder/Decoder IP Core Relecase Informcaton
Silicon Labs. Timing Solutions for Xilinx FPGAs. Timing Simplified
Silicon Labs Timing Solutions for Xilinx FPGAs Timing Simplified Silicon Labs offers a broad portfolio of frequency flexible timing products that enable hardware designers to simplify clock generation,
New Initiatives and Technologies Brighten Embedded Software Radio
New Initiatives and Technologies Brighten Embedded Software Radio Embedded Tech Trends January 2018 Rodger Hosking Pentek, Inc. Sensor Open System Architecture (SOSA) Consortium of Air Force, Navy, Army,
SoC Platforms and CPU Cores
SoC Platforms and CPU Cores COE838: Systems on Chip Design http://www.ee.ryerson.ca/~courses/coe838/ Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering Ryerson University
COSMOS Architecture and Key Technologies. June 1 st, 2018 COSMOS Team
COSMOS Architecture and Key Technologies June 1 st, 2018 COSMOS Team COSMOS: System Architecture (2) System design based on three levels of SDR radio node (S,M,L) with M,L connected via fiber to optical
Signal Conversion in a Modular Open Standard Form Factor. CASPER Workshop August 2017 Saeed Karamooz, VadaTech
Signal Conversion in a Modular Open Standard Form Factor CASPER Workshop August 2017 Saeed Karamooz, VadaTech At VadaTech we are technology leaders First-to-market silicon Continuous innovation Open systems
Components of a MicroTCA System
Micro TCA Overview0 Platform, chassis, backplane, and shelf manager specification, being developed through PICMG Allows AMC modules to plug directly into a backplane Fills the performance/cost gap between
EFEC20 IP Core. Features
EFEC20 IP Core DS-1034-1.2 Data Sheet The Altera 20% Enhanced Forward Error Correction (EFEC20) IP core includes a highperformance encoder and decoder for Optical Transport Network (OTN) FEC applications.
Quartus II Software Version 12.0 Device Support Release Notes
Quartus II Software Version 12.0 Device Support Release Notes RN-01074 This document provides late-breaking information about device support in the Altera Quartus II software version 12.0. For information
40-Gbps and 100-Gbps Ethernet in Altera Devices
40-Gbps and 100-Gbps Ethernet in Altera Devices Transceiver Portfolio Workshops 2009 Agenda 40/100 GbE standards 40/100 GbE IP in Altera devices Stratix IV GT FPGA features and advantages Altera standards
DC-DC Converters. Non-Isolated. No galvanic isolation. Distributed power architecture. Very high effi ciency. Battery powered devices
DC-DC Converters Non-Isolated Applications Distributed power architecture Battery powered devices Industrial Medical Communications Computing Features No galvanic isolation Very high effi ciency Very fast
DC-DC Converters. Non-Isolated. No galvanic isolation. Distributed power architecture. Very high effi ciency. Battery powered devices
DC-DC Converters Non-Isolated Applications Distributed power architecture Battery powered devices Industrial Medical Communications Computing Features No galvanic isolation Very high effi ciency Very fast
Early Models in Silicon with SystemC synthesis
Early Models in Silicon with SystemC synthesis Agility Compiler summary C-based design & synthesis for SystemC Pure, standard compliant SystemC/ C++ Most widely used C-synthesis technology Structural SystemC
How to validate your FPGA design using realworld
How to validate your FPGA design using realworld stimuli Daniel Clapham National Instruments ni.com Agenda Typical FPGA Design NIs approach to FPGA Brief intro into platform based approach RIO architecture
QuiXilica V5 Architecture
QuiXilica V5 Architecture: The High Performance Sensor I/O Processing Solution for the Latest Generation and Beyond Andrew Reddig President, CTO TEK Microsystems, Inc. Military sensor data processing applications
1. Overview for the Arria V Device Family
1. Overview for the Arria V Device Family December 2011 AV51001-1.2 AV51001-1.2 Built on the 28-nm low-power process technology, Arria V devices offer the lowest power and lowest system cost for mainstream
Understanding Peak Floating-Point Performance Claims
white paper FPGA Understanding Peak ing-point Performance Claims Learn how to calculate and compare the peak floating-point capabilities of digital signal processors (DSPs), graphics processing units (GPUs),
The Ultimate System Integration Platform. VIRTEX-5 FPGAs
The Ultimate System Integration Platform VIRTEX-5 FPGAs THE WORLD S FIRST 5nm FPGA One Family Multiple Platforms The Virtex -5 family of FPGAs offers a choice of four new platforms, each delivering an
Reduce Your System Power Consumption with Altera FPGAs Altera Corporation Public
Reduce Your System Power Consumption with Altera FPGAs Agenda Benefits of lower power in systems Stratix III power technology Cyclone III power Quartus II power optimization and estimation tools Summary
Altera Product Overview. Altera Product Overview
Altera Product Overview Tim Colleran Vice President, Product Marketing Altera Product Overview High Density + High Bandwidth I/O Programmable ASSP with CDR High-Speed Product Term Embedded Processor High
Transient Buffer Wideband (TBW) Preliminary Design Ver. 0.1
Transient Buffer Wideband (TBW) Preliminary Design Ver. 0.1 Steve Ellingson November 11, 2007 Contents 1 Summary 2 2 Design Concept 2 3 FPGA Implementation 3 4 Extending Capture Length 3 5 Issues to Address
Reed-Solomon Encoder/Decoder IP core Specifccaton
Reed-Solomon Encoder/Decoder IP core Specifccaton Reed-Solomon Encoder/Decoder IP core Relecase Informcaton Fecatures Delivercables IP Core Structure Port Mcap Reed-Solomon Encoder/Decoder IP core Relecase
Nutaq. PicoSDR FPGA-based, MIMO-Enabled, tunable RF SDR solutions PRODUCT SHEET I MONTREAL I NEW YORK I. nutaq. .com QUEBEC
Nutaq PicoSDR FPGA-based, MIMO-Enabled, tunable RF SDR solutions PRODUCT SHEET QUEBEC I MONTREAL I NEW YORK I nutaq.com Nutaq PicoSDR Includes Nutaq OFDM Reference Design Up to 4 independent TRX, synchronized
Performance Overhead with High Level Waveform Development
Performance Overhead with High Level Waveform Development Stefan Nagel, Michael Schwall, Friedrich K. Jondral 2010 European Reconfigurable Radio Technologies Workshop June 23-25, 2010 Mainz, Germany Communications
Cyclone III LS FPGAs Altera Corporation Public
Cyclone III LS FPGAs Introducing Cyclone III LS Devices Low power 200K LE for under 0.25 Watt TSMC 60-nm low-power (LP) process Quartus II software power-aware design flow Broadcast Industrial Military
Product Overview. Programmable Network Cards Network Appliances FPGA IP Cores
2018 Product Overview Programmable Network Cards Network Appliances FPGA IP Cores PCI Express Cards PMC/XMC Cards The V1151/V1152 The V5051/V5052 High Density XMC Network Solutions Powerful PCIe Network
Nutaq. PicoSDR FPGA-based, MIMO-Enabled, tunable RF SDR solutions PRODUCT SHEET I MONTREAL I NEW YORK I. nutaq. .com QUEBEC
Nutaq PicoSDR FPGA-based, MIMO-Enabled, tunable RF SDR solutions PRODUCT SHEET QUEBEC I MONTREAL I NEW YORK I nutaq.com Nutaq PicoSDR Includes Nutaq OFDM Reference Design Up to 4 independent TRX, synchronized
S2C K7 Prodigy Logic Module Series
S2C K7 Prodigy Logic Module Series Low-Cost Fifth Generation Rapid FPGA-based Prototyping Hardware The S2C K7 Prodigy Logic Module is equipped with one Xilinx Kintex-7 XC7K410T or XC7K325T FPGA device
Interlaken IP datasheet
Key words:interlaken, MAC, PCS, SERDES Abstract:Interlaken MAC/PCS implementation per Interlaken protocol v1.2 All rights reserved Table of Contents 1. Introduction...4 2. Specification...4 3. Architecture...4
4. TriMatrix Embedded Memory Blocks in HardCopy IV Devices
January 2011 HIV51004-2.2 4. TriMatrix Embedded Memory Blocks in HardCopy IV Devices HIV51004-2.2 This chapter describes TriMatrix memory blocks, modes, features, and design considerations in HardCopy
FPGA VHDL Design Flow AES128 Implementation
Sakinder Ali FPGA VHDL Design Flow AES128 Implementation Field Programmable Gate Array Basic idea: two-dimensional array of logic blocks and flip-flops with a means for the user to configure: 1. The interconnection
8. Migrating Stratix II Device Resources to HardCopy II Devices
8. Migrating Stratix II Device Resources to HardCopy II Devices H51024-1.3 Introduction Altera HardCopy II devices and Stratix II devices are both manufactured on a 1.2-V, 90-nm process technology and
The Benefits of FPGA-Enabled Instruments in RF and Communications Test. Johan Olsson National Instruments Sweden AB
The Benefits of FPGA-Enabled Instruments in RF and Communications Test Johan Olsson National Instruments Sweden AB 1 Agenda Introduction to FPGAs in test New FPGA-enabled test applications FPGA for test
H.264 AVC 4k Decoder V.1.0, 2014
SOC H.264 AVC 4k Video Decoder Datasheet System-On-Chip (SOC) Technologies 1. Key Features 1. Profile: High profile 2. Resolution: 4k (3840x2160) 3. Frame Rate: up to 60fps 4. Chroma Format: 4:2:0 or 4:2:2
Strategies for Deploying RFSoC Technology for SIGINT, DRFM and Radar Applications. Rodger Hosking Pentek, Inc. WInnForum Webinar November 8, 2018
Strategies for Deploying RFSoC Technology for SIGINT, DRFM and Radar Applications Rodger Hosking Pentek, Inc. WInnForum Webinar November 8, 2018 1 Topics Xilinx RFSoC Overview Impact of Latency on Applications
1. Overview for the Arria II Device Family
1. Overview for the Arria II Device Family July 2012 AIIGX51001-4.4 AIIGX51001-4.4 The Arria II device family is designed specifically for ease-of-use. The cost-optimized, 40-nm device family architecture
Embedded Tech Trends 2014 New EW architectures based on tight coupling of FPGA and CPU processing
Embedded Tech Trends 2014 New EW architectures based on tight coupling of and CPU processing 1 Sensors to Parallel Processing to Wide-Area Networks RF Sampling behind antenna LVDS capture Processing DMA
Interfacing FPGAs with High Speed Memory Devices
Interfacing FPGAs with High Speed Memory Devices 2002 Agenda Memory Requirements Memory System Bandwidth Do I Need External Memory? Altera External Memory Interface Support Memory Interface Challenges
10 Gigabit Ethernet 10GBase-R PCS Core. 1 Introduction. Product Brief Version August 2004
1 Introduction Initially, 10 Gigabit Ethernet (10 GbE) is used by network managers to provide high-speed, local backbone interconnection between large-capacity switches, as it enables Internet Service
Copyright 2017 Xilinx.
All Programmable Automotive SoC Comparison XA Zynq UltraScale+ MPSoC ZU2/3EG, ZU4/5EV Devices XA Zynq -7000 SoC Z-7010/7020/7030 Devices Application Processor Real-Time Processor Quad-core ARM Cortex -A53
SOFTWARE DEFINED RADIO
SOFTWARE DEFINED RADIO USR SDR WORKSHOP, SEPTEMBER 2017 PROF. MARCELO SEGURA SESSION 1: SDR PLATFORMS 1 PARAMETER TO BE CONSIDER 2 Bandwidth: bigger band better analysis possibilities. Spurious free BW:
Quartus II Software Version 10.0 Device Support Release Notes
Quartus II Software Version 10.0 Device Support Release Notes July 2010 RN-01055 This document provides late-breaking information about device support in the 10.0 version of the Altera Quartus II software.
New! New! New! New! New!
New! New! New! New! New! Model 5950 Features Supports Xilinx Zynq UltraScale+ RFSoC FPGAs 18 GB of DDR4 SDRAM On-board GPS receiver PCI Express (Gen. 1, 2 and 3) interface up to x8 LVDS connections to
Intel Arria 10 Device Overview
A10-OVERVIEW 2017.09.20 Subscribe Send Feedback Contents Contents... 3 Key Advantages of Intel Arria 10 Devices... 4 Summary of Intel Arria 10 Features...4 Intel Arria 10 Device Variants and Packages...7
One Size Does Not Fit All
One Size Does Not Fit All What do you do when system performance demands threaten to increase power consumption and cost? What happens if you ve got the power you need but not the performance? Wouldn t
10 Gigabit Ethernet 10GBase-W PHY. 1 Introduction. Product Brief Version May 2005
1 Introduction Initially, 10 Gigabit Ethernet is used by network managers to provide high-speed, local backbone interconnection between large-capacity switches, as it enables Internet Service Providers
XMC-FPGA05F. Programmable Xilinx Virtex -5 FPGA PMC/XMC with Quad Fiber-optics. Data Sheet
Data Sheet XMC-FPGA05F Programmable Xilinx Virtex -5 FPGA PMC/XMC with Quad s Applications Remote Sensor Interface Data Recorders Distributed Processing Interconnect Protocol Converter Data Encryption
High-Tech-Marketing. Selecting an FPGA. By Paul Dillien
High-Tech-Marketing Selecting an FPGA By Paul Dillien The Market In 2011 the total PLD market was $4.97B The FPGA portion was worth $4.1B 2 FPGA Applications The dominant applications have always been
Pushing Performance and Integration with the UltraScale+ Portfolio
White Paper: UltraScale+ Portfolio WP471 (v1.0) November 24, 2015 Introducing the UltraScale+ Portfolio Pushing Performance and Integration with the UltraScale+ Portfolio By: Nick Mehta The Xilinx UltraScale+
Qsys and IP Core Integration
Qsys and IP Core Integration Stephen A. Edwards (after David Lariviere) Columbia University Spring 2016 IP Cores Altera s IP Core Integration Tools Connecting IP Cores IP Cores Cyclone V SoC: A Mix of
XMC Products. High-Performance XMC FPGAs, XMC 10gB Ethernet, and XMC Carrier Cards. XMC FPGAs. FPGA Extension I/O Modules.
E M B E D D E D C O M P U T I N G & I / O S O L U T I O N S XMC Products XMC FPGAs FPGA Extension I/O Modules XMC 10gB Ethernet XMC Carrier Cards XMC Software Support High-Performance XMC FPGAs, XMC 10gB
RiceNIC. Prototyping Network Interfaces. Jeffrey Shafer Scott Rixner
RiceNIC Prototyping Network Interfaces Jeffrey Shafer Scott Rixner RiceNIC Overview Gigabit Ethernet Network Interface Card RiceNIC - Prototyping Network Interfaces 2 RiceNIC Overview Reconfigurable and
Quartus II Software Version 10.0 SP1 Device Support
Quartus II Software Version 10.0 SP1 Device Support RN-01057 Release Notes This document provides late-breaking information about device support in the 10.0 SP1 version of the Altera Quartus II software.
GTC 2017 Green Flash Persistent Kernel : Real-Time, Low-Latency and HighPerformance Computation on Pascal. Julien BERNARD
Green Flash Persistent Kernel : Real-Time, Low-Latency and HighPerformance Computation on Pascal Julien BERNARD Project #671662 funded by European Commission under program H2020-EU.1.2.2 coordinated in
Xynergy It really makes the difference!
Xynergy It really makes the difference! STM32F217 meets XILINX Spartan-6 Why Xynergy? Very easy: There is a clear Synergy achieved by combining the last generation of the most popular ARM Cortex-M3 implementation
Implementing Video and Image Processing Designs Using FPGAs. Click to add subtitle
Implementing Video and Image Processing Designs Using FPGAs Click to add subtitle Agenda Key trends in video and image processing Video and Image Processing Suite Model-based design for video processing
Gate Estimate. Practical (60% util)* (1000's) Max (100% util)* (1000's)
The Product Brief October 07 Ver. 1.3 Group DN9000K10PCIe-4GL XilinxVirtex-5 Based ASIC Prototyping Engine, 4-lane PCI Express (Genesys Logic PHYs) Features PCI Express (4-lane) logic prototyping system
M100 GigE Series. Multi-Camera Vision Controller. Easy cabling with PoE. Multiple inspections available thanks to 6 GigE Vision ports and 4 USB3 ports
M100 GigE Series Easy cabling with PoE Multiple inspections available thanks to 6 GigE Vision ports and 4 USB3 ports Maximized acquisition performance through 6 GigE independent channels Common features
FPGA system development What you need to think about. Frédéric Leens, CEO
FPGA system development What you need to think about Frédéric Leens, CEO About Byte Paradigm 2005 : Founded by 3 ASIC-SoC-FPGA engineers as a Design Center for high-end FPGA and board design. 2007 : GP
Digital Blocks Semiconductor IP
Digital Blocks Semiconductor IP -UHD General Description The Digital Blocks -UHD LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Interconnect
Versal: AI Engine & Programming Environment
Engineering Director, Xilinx Silicon Architecture Group Versal: Engine & Programming Environment Presented By Ambrose Finnerty Xilinx DSP Technical Marketing Manager October 16, 2018 MEMORY MEMORY MEMORY
Intelop. *As new IP blocks become available, please contact the factory for the latest updated info.
A FPGA based development platform as part of an EDK is available to target intelop provided IPs or other standard IPs. The platform with Virtex-4 FX12 Evaluation Kit provides a complete hardware environment
M100 GigE Series. Multi-Camera Vision Controller. Easy cabling with PoE. Multiple inspections available thanks to 6 GigE Vision ports and 4 USB3 ports
M100 GigE Series Easy cabling with PoE Multiple inspections available thanks to 6 GigE Vision ports and 4 USB3 ports Maximized acquisition performance through 6 GigE independent channels Common features
5051 & 5052 PCIe Card Overview
5051 & 5052 PCIe Card Overview About New Wave New Wave DV provides high performance network interface cards, system level products, FPGA IP cores, and custom engineering for: High-bandwidth low-latency
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices November 2005, ver. 3.1 Application Note 325 Introduction Reduced latency DRAM II (RLDRAM II) is a DRAM-based point-to-point memory device
High Performance Memory in FPGAs
High Performance Memory in FPGAs Industry Trends and Customer Challenges Packet Processing & Transport > 400G OTN Software Defined Networks Video Over IP Network Function Virtualization Wireless LTE Advanced
High-Performance Memory Interfaces Made Easy
High-Performance Memory Interfaces Made Easy Xilinx 90nm Design Seminar Series: Part IV Xilinx - #1 in 90 nm We Asked Our Customers: What are your challenges? Shorter design time, faster obsolescence More
Quartus Prime Standard Edition Software and Device Support Release Notes Version 15.1
2015.11.02 Quartus Prime Standard Edition Software and Device Support Release Notes Version 15.1 RN-01080-15.1.0 Subscribe This document provides late-breaking information about the Altera Quartus Prime
High Performance Embedded Applications. Raja Pillai Applications Engineering Specialist
High Performance Embedded Applications Raja Pillai Applications Engineering Specialist Agenda What is High Performance Embedded? NI s History in HPE FlexRIO Overview System architecture Adapter modules
Economic Feasibility of 400G Ethernet MAC/PCS/FEC/PMA
Economic Feasibility of 400G Ethernet MAC/PCS/FEC/PMA Mike Peng Li, Gregg Baeckler, Martin Langhammer, Divya Vijayaraghavan, Paul Scheidt, Curt Wortman Altera Corporation For IEEE 400G SG Jan, 2014 1 Context
Third Genera+on USRP Devices and the RF Network- On- Chip. Leif Johansson Market Development RF, Comm and SDR
Third Genera+on USRP Devices and the RF Network- On- Chip Leif Johansson Market Development RF, Comm and SDR About Ettus Research Leader in soeware defined radio and signals intelligence Maker of USRP
A HT3 Platform for Rapid Prototyping and High Performance Reconfigurable Computing
A HT3 Platform for Rapid Prototyping and High Performance Reconfigurable Computing Second International Workshop on HyperTransport Research and Application (WHTRA 2011) University of Heidelberg Computer
Zynq-7000 All Programmable SoC Product Overview
Zynq-7000 All Programmable SoC Product Overview The SW, HW and IO Programmable Platform August 2012 Copyright 2012 2009 Xilinx Introducing the Zynq -7000 All Programmable SoC Breakthrough Processing Platform
UltraScale Architecture: Highest Device Utilization, Performance, and Scalability
White Paper: UltraScale FPGAs WP455 (v1.2) October 29, 2015 UltraScale Architecture: Highest Device Utilization, Performance, and Scalability By: Nick Mehta High-performance architecture and extensive
1. Stratix IV Device Family Overview
1. Stratix IV Device Family Overview SIV51001-3.0 Altera Stratix IV FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without
AMC517 Kintex-7 FPGA Carrier for FMC, AMC
AMC Kintex-7 FPGA Carrier KEY FEATURES AMC FPGA carrier for FMC per VITA-57 Xilinx Kintex-7 410T FPGA in FFG-900 package with optional P2040 Supported by DAQ Series data acquisition software AMC Ports
Flexible Architecture Research Machine (FARM)
Flexible Architecture Research Machine (FARM) RAMP Retreat June 25, 2009 Jared Casper, Tayo Oguntebi, Sungpack Hong, Nathan Bronson Christos Kozyrakis, Kunle Olukotun Motivation Why CPUs + FPGAs make sense
Quartus II Software and Device Support Release Notes Version 12.1 SP1
Quartus II Software and Device Support Release Notes Version 12.1 SP1 RN-01080-12.1SP1.2 Release Notes This document provides late-breaking information about the Altera Quartus II software version 12.1
Simplify System Complexity
1 2 Simplify System Complexity With the new high-performance CompactRIO controller Arun Veeramani Senior Program Manager National Instruments NI CompactRIO The Worlds Only Software Designed Controller
White Paper The Need for a High-Bandwidth Memory Architecture in Programmable Logic Devices
Introduction White Paper The Need for a High-Bandwidth Memory Architecture in Programmable Logic Devices One of the challenges faced by engineers designing communications equipment is that memory devices
Digital Blocks Semiconductor IP
Digital Blocks Semiconductor IP General Description The Digital Blocks LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Interconnect to a 4K and
Leveraging the Intel HyperFlex FPGA Architecture in Intel Stratix 10 Devices to Achieve Maximum Power Reduction
white paper FPGA Leveraging the Intel HyperFlex FPGA Architecture in Intel Stratix 1 s to Achieve Maximum Reduction devices leverage the innovative Intel HyperFlex FPGA architecture to achieve power savings
6. I/O Features for HardCopy IV Devices
6. I/O Features for HardCopy IV Devices March 2012 HIV51006-2.3 HIV51006-2.3 This chapter describes the I/O standards, features, termination schemes, and performance supported in HardCopy IV devices. All
OTU2 I.9 FEC IP Core (IP-OTU2EFECI9) Data Sheet
OTU2 I.9 FEC IP Core (IP-OTU2EFECI9) Data Sheet Revision 0.02 Release Date 2015-02-11 Document number . All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and ARRIA words
Digital Integrated Circuits
Digital Integrated Circuits Lecture 9 Jaeyong Chung Robust Systems Laboratory Incheon National University DIGITAL DESIGN FLOW Chung EPC6055 2 FPGA vs. ASIC FPGA (A programmable Logic Device) Faster time-to-market
Reconfigurable VLSI Communication Processor Architectures
Reconfigurable VLSI Communication Processor Architectures Joseph R. Cavallaro Center for Multimedia Communication www.cmc.rice.edu Department of Electrical and Computer Engineering Rice University, Houston
Virtex-II Architecture. Virtex II technical, Design Solutions. Active Interconnect Technology (continued)
Virtex-II Architecture SONET / SDH Virtex II technical, Design Solutions PCI-X PCI DCM Distri RAM 18Kb BRAM Multiplier LVDS FIFO Shift Registers BLVDS SDRAM QDR SRAM Backplane Rev 4 March 4th. 2002 J-L
Zynq AP SoC Family
Programmable Logic (PL) Processing System (PS) Zynq -7000 AP SoC Family Cost-Optimized Devices Mid-Range Devices Device Name Z-7007S Z-7012S Z-7014S Z-7010 Z-7015 Z-7020 Z-7030 Z-7035 Z-7045 Z-7100 Part
Arria V GX Transceiver Starter Kit
Page 1 of 4 Arria V GX Transceiver Starter Kit from Altera Ordering Information Transceiver Starter Kit Contents Starter Board Photo Related Links The Altera Arria V GX Transceiver Starter Kit provides
XMC-RFSOC-A. XMC Module Xilinx Zynq UltraScale+ RFSOC. Overview. Key Features. Typical Applications. Advanced Information Subject To Change
Advanced Information Subject To Change XMC-RFSOC-A XMC Module Xilinx Zynq UltraScale+ RFSOC Overview PanaTeQ s XMC-RFSOC-A is a XMC module based on the Zynq UltraScale+ RFSoC device from Xilinx. The Zynq
New Software-Designed Instruments
1 New Software-Designed Instruments Nicholas Haripersad Field Applications Engineer National Instruments South Africa Agenda What Is a Software-Designed Instrument? Why Software-Designed Instrumentation?