SM59R09A5 與 W77E58 應用差異說明一 適用產品 :SM59R09A5

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1 SM59R09A5 與 W77E58 應用差異說明一 適用產品 :SM59R09A5 二 應用範圍 : 針對 SM59R09A5 SM59R09A3 與 W77E58 之應用差異, 僅需對特殊功能暫存器定義做小幅度修改即可. 三 功能說明 :SM59R09A5 SM59R09A3 與 W77E58 各個 MCU 規格比較 ( 表 1): Feature SM59R09A5 SM59R09A3 W77E58 工作電壓 (V) 2.7~ ~ ~5.5 I DD (Power Down) 3.5uA at VDD=5.0V 3.5uA at VDD=5.0V 50uA at V DD =5.5V System clock(mhz) 1T:up to 25 (1T,2T can change on fly) 1T:up to 25 (1T,2T can change on fly) 4-T:up to 40 內部 RC 震盪器有 ( 最大 24MHz) 有 ( 最大 24MHz) 有 ( 約 2~4MHz) Program Flash ( byte) 36K 36K 32K RAM( byte) Interrupt WDT 有有有 16-bit Dual DPTR 有 有 有 Timer UART EEPROM 有 有 無 ICP/ISP/IAP 有 有 無 PCA 有 (4 路 ), 中斷向量有 (4 路 ), 中斷向量 0x2BH 0x2BH 無 PWM 有 (4 路,10 位 ), 有 (4 路,10 位 ), 中斷向量 0x43H 中斷向量 0x43H 無 MDU 有 有 無 ADC 有 有 無 SPI interface 有 有 無 IIC interface 有 有 無 KBI interface 有 有 無 Port 4.4~4.7(40-pin PDIP) &four I/O type 有 有 無 內置復位 有 ( 可調復位時間 ) 有 ( 可調復位時間 ) 無 低壓復位 有 有 無 即時時鐘 (RTC) 有 無 無 OP & Compartor 有 無 無 ISSFA Ver. A 2010/06

2 四 特殊功能暫存器比較表 : SM59R09A5( 表 2): Hex\Bin X000 X001 X010 X011 X100 X101 X110 X111 Bin/Hex F8 IICS IICCTL IICA1 IICA2 IICRWD IICS2 Cmp0CON Cmp1CON FF F0 B SPIC1 SPIC2 SPITXD SPIRXD SPIS OpPin TAKEY F7 E8 P4 MD0 MD1 MD2 MD3 MD4 MD5 ARCON EF E0 ACC ISPFAH ISPFAL ISPFD ISPFC LVC SWRES E7 D8 P5 P3M0 P3M1 P4M0 P4M1 P5M0 P5M1 DF D0 PSW CCEN2 P0M0 P0M1 P1M0 P1M1 P2M0 P2M1 D7 C8 T2CON CCCON CRCL CRCH TL2 TH2 PWMMDH PWMMDL CF C0 IRCON CCEN CCL1 CCH1 CCL2 CCH2 CCL3 CCH3 C7 B8 IEN1 IP1 S0RELH S1RELH PWMD0H PWMD0L PWMD1H PWMD1L BF B0 P3 PWMD2H PWMD2L PWMD3H PWMD3L PWMC WDTC WDTK B7 A8 IEN0 IP0 S0RELL ADCC1 ADCC2 ADCDH ADCDL ADCCS AF A0 P2 A7 98 S0CON S0BUF IEN2 S1CON S1BUF S1RELL RTCADDR RTCDATA 9F 90 P1 AUX AUX2 KBLS KBE KBF KBD IRCON TCON TMOD TL0 TL1 TH0 TH1 IFCON 8F 80 P0 SP DPL DPH DPL1 DPH1 RCON PCON 87 SM59R09A3( 表 3): Hex\Bin X000 X001 X010 X011 X100 X101 X110 X111 Bin/Hex F8 IICS IICCTL IICA1 IICA2 IICRWD IICS2 FF F0 B SPIC1 SPIC2 SPITXD SPIRXD SPIS TAKEY F7 E8 P4 MD0 MD1 MD2 MD3 MD4 MD5 ARCON EF E0 ACC ISPFAH ISPFAL ISPFD ISPFC LVC SWRES E7 D8 P5 P3M0 P3M1 P4M0 P4M1 P5M0 P5M1 DF D0 PSW CCEN2 P0M0 P0M1 P1M0 P1M1 P2M0 P2M1 D7 C8 T2CON CCCON CRCL CRCH TL2 TH2 PWMMDH PWMMDL CF C0 IRCON CCEN CCL1 CCH1 CCL2 CCH2 CCL3 CCH3 C7 B8 IEN1 IP1 S0RELH S1RELH PWMD0H PWMD0L PWMD1H PWMD1L BF B0 P3 PWMD2H PWMD2L PWMD3H PWMD3L PWMC WDTC WDTK B7 A8 IEN0 IP0 S0RELL ADCC1 ADCC2 ADCDH ADCDL ADCCS AF A0 P2 A7 98 S0CON S0BUF IEN2 S1CON S1BUF S1RELL 9F 90 P1 AUX AUX2 KBLS KBE KBF KBD TCON TMOD TL0 TL1 TH0 TH1 IFCON 8F 80 P0 SP DPL DPH DPL1 DPH1 RCON PCON 87 ISSFA Ver. A 2010/06

3 W77E58( 表 3): Hex\Bin X000 X001 X010 X011 X100 X101 X110 X111 Bin/Hex F8 EIP FF F0 B F7 E8 EIE EF E0 ACC E7 D8 WDCON DF D0 PSW D7 C8 T2CON T2MOD RCAP2L RCAP2H TL2 TH2 CF C0 SCON1 SBUF1 ROMMAP PMR STATUS TA C7 B8 IP SADEN SADEN1 BF B0 P3 B7 A8 IE SADDR SADDR1 AF A0 P2 P4 A7 98 S0CON S0BUF 9F 90 P1 EXIF TCON TMOD TL0 TL1 TH0 TH1 CKCON 8F 80 P0 SP DPL DPH DPL1 DPH1 DPS PCON 87 五 特殊功能差異說明 : 特殊功能 SM59R09A5/SM59R09A3 Addr. W77E58 Addr. 雙數據指針於 AUX.DPS 設定 91H.0 於 DPS.DPS 設定 86H.0 P4 8 Bits 可位元定址 E8H 4 Bits 不可位元定址 A6H 看門狗 - TAKEY F7H IE1.EWDI(WDT interrupt enable, E8H.4 1. 時脈源不同 2. 預分頻不同 WDTC WDTK 1. 時脈源由內部 250KHz 產生, 溢出時 B6H B7H interrupt vector at 0x63H) CKCON WDCON 8EH D8H 3. 設定及清除 間固定 1. 時脈源由外部晶振產生, 溢出時 計時方式不 2. 由 WDTC[3:0] 設定, 預分頻由 間不固定 同 1~32768 分 16 階 : 2. 由 CKCON[7:6] 設定, 預分頻 4 Period = 1.02 m sec ~ sec 3. 須先設定 KEY(TAKEY) 後, 才可對 階, 產生中斷信號後 512 時脈產生重置信號 WDTC 設定 ; 清除 WDT 於 WDTK 寫 WD1:WD0 Interrupt Reset ISSFA Ver. A 2010/06

4 入 0x55 参考附件一 沒有 KEY 的設計, 可直接改 WDCON 及 CKCON 輔助記憶體 有 2048 Bytes 有 1024 Bytes Embedded IFCON.EMEN 8FH.1 PMR.DEM0 C4H.0 RAM =1, 禁能 =1, 致能 =0, 致能 (default) =0, 禁能 (default) 中斷致能及優先 共提供 15/13 組中斷源及 4 階中斷優先 共提供 12 組中斷源及 2 階中斷優先權 權設定不同 權設定 設定 IEN0 A8H IE A8H IEN1 B8H EIE E8H IEN2 9AH IP B8H IP A9H EIP F8H IP1 B9H EIF 91H 参考附件二 雙串口 IEN0.ES0(UART0 interrupt enable, A8H.4 IE.ES(UART0 interrupt enable, A8H.4 (Dual UART) interrupt vector at 0x23H) IEN2.ES1(UART1 interrupt enable, 9AH.0 interrupt vector at 0x23H) IE.ES1(UART1 interrupt enable, A8H.6 interrupt vector at 0x83H) interrupt vector at 0x3BH) PCON.SMOD 87H.7 PCON.SMOD 87H.7 AUX.P4UR1 91H.4 SCON 98H =0, UART1 at P1. SBUF 99H =1, UART1 at P4 SCON1 C0H TxD1 change from P1.3 to P4.3 SBUF1 C1H RxD1 change from P1.2 to P4.2 SADDR1 AAH S0CON 98H SADEN1 BAH ISSFA Ver. A 2010/06

5 S0BUF 99H STATUS C5H S0RELL AAH WDCON D8H S0RELH BAH S1CON 9BH S1RELL 9DH S1RELH BBH S1BUF 9CH 参考附件三 計時器 2 IEN0.ET2(Timer2 interrupt enable, A8H.5 IE.ET2(Timer 2 interrupt enable, A8H.5 (Timer 2) interrupt vector at 0x2BH) T2CON C8H interrupt vector at 0x2BH) T2CON C8H CRCL CAH T2MOD C9H CRCH CBH RCAP2L CAH TL2 CCH RCAP2H CBH TH2 CDH TL2 CCH 参考附件四 TH2 CDH ISSFA Ver. A 2010/06

6 附件一 : 看門狗設定不同說明 1. SM59R09A5/SM59R09A3 與 W77E58 看門狗功能比較 : SM59R09A5/SM59R09A3 W77E58 時鐘源 內部獨立之 250KHz RC 震盪器, 復位時間固定 與外部晶振共用, 復位時間不固定 復位階數 分 16 階, 方便使用 分 4 階 復位時間 1.02 m sec ~ sec 需依公式計算復位時間 2. SM59R09A5/SM59R09A3 與 W77E58 看門狗特殊功能暫存器比較 : 特殊功能暫存器名稱 SM59R09A5/SM59R09A3 名稱及位址 W77E58 名稱及位址 看門狗功能設定 WDTC (0xB6H) WDCON (0xD8H);CKCON(0X8EH) 看門狗功能重置 WDTK (0xB7H) WDCON (0xD8H) 功能致能暫存器保護 TAKEY (0xF7H) 於此暫存器連續填入 0x55H, 0xAAH 及 0x5AH 以啟動功能 無 3. SM59R09A5/SM59R09A3 與 W77E58 看門狗之特殊功能暫存器說明 : a. SM59R09A5/SM59R09A3 看門狗功能使用之暫存器說明 : Mnemonic: WDTC Address: B6h WDTF - WDTE - WDTM [3:0] 04H WDTF: Watchdog timer reset flag. When MCU is reset by watchdog, WDTF flag will be set to one by hardware. This flag clear by software or external reset or power on reset. WDTE: Control bit used to enable Watchdog timer. The WDTE bit can be used only if WDTEN is 0. If the WDTEN bit is 0, then WDT can be disabled / enabled by the WDTE bit. 0: Disable WDT. 1: Enable WDT. The WDTE bit is not used if WDTEN is 1. That is, if the WDTEN bit is 1, WDT is always disabled no matter what the WDTE bit status is. The WDTE bit can be read and written. WDTM [3:0]: WDT clock source divider bit. Please see below table to reference the WDT time-out period. ISSFA Ver. A 2010/06

7 Mnemonic: WDTK Address: B7h WDTK[7:0] 00h WDTK: Watchdog timer refresh key. A programmer must write 0x55 into WDTK register, and then the watchdog timer will be cleared to zero. Mnemonic: TAKEY Address: F7h TAKEY [7:0] 00H 範例程式 : 於使用看門狗功能時需先使用 ISP 或 ICP 方式啟動看門狗功能, 再於程式中再次啟動看門狗, 看門狗功能才能正常使用 MOV TAKEY, #55h MOV TAKEY, #0AAh MOV TAKEY, #5Ah ; 啟動 WDTC 寫入功能. MOV WDTC, #28h ; 設定看門狗復位時間為 毫秒, 並啟動看門狗功能... MOV WDTK, #55h ; 清除看門狗計數器. WDTM [3:0] Divider (250 KHz RC oscillator in) Time 250KHz ms ms ms ms ms (default) ms ms ms ms ms s s s s s s ISSFA Ver. A 2010/06

8 b. W77E58 看門狗功能使用之暫存器說明 : Mnemonic: WDCON Address: D8h SMOD_1 POR - - WDIF WTRF EWT RWT 0x0x0xx0B SMOD_1: This bit Doubles the Serial Port 1 baud rate in mode 1,2 and 3 when set to 1 POR: Power-on reset flag. Hardware will set this flag on a power up condition. This flag can be read or written by software. A write by software is the only way to clear this bit once it is set. WDIF: Watchdog Timer Interrupt Flag. If the watchdog interrupt is enabled, hardware will set this bit to indicate that the watchdog interrupt has occurred. If the interrupt is not enabled, then this bit indicates that the time-out period has elapsed. This bit must be cleared by software. WTRF: Watchdog Timer Reset Flag. Hardware will set this bit when the watchdog timer causes a reset. Software can read it but must clear it manually. A power-fail reset will also clear the bit. This bit helps software in determining the cause of a reset. If EWT = 0, the watchdog timer will have no affect on this bit. EWT: Enable Watchdog timer Reset. Setting this bit will enable the Watchdog timer Reset function. RWT: Reset Watchdog Timer. This bit helps in putting the watchdog timer into a know state. It also helps in resetting the watchdog timer before a time-out occurs. Failing to set the RWT before time-out will cause an interrupt, if EWDI (EIE.4) is set and 512 clocks after that a watchdog timer reset will be generated if EWT is set. This bit is self-clearing by hardware. The WDCON SFR is set to a 0x0x0xx0b on an external reset. WTRF is set to a 1 on a Watchdog timer reset, but to a 0 on power on/down resets. WTRF is not altered by an external reset. POR is set to 1 by a power-on reset. EWT is set to 0 on a Power-on reset and unaffected by other resets. All the bits in this SFR have unrestricted read access. POR, EWT, WDIF and RWT require Timed Access procedure to write. The remaining bits have unrestricted write accesses. Mnemonic: CKCON Address: 8Eh WD1 WD0 T2M T1M T0M MD2 MD1 MD0 04H WD1-0: Watchdog timer mode select bits: These bits determine the time-out period for the watchdog timer. In all four time-out options the reset time-out is 512 clocks more than the interrupt timeout period. WD1 WD0 Interrupt time-out Reset time-out T2M: Timer 2 clock select: When T2M is set to 1, timer 2 uses a divide by 4 clock, and when set to 0 it uses a divide by 12 clock. T1M: Timer 1 clock select: When T1M is set to 1, timer 1 uses a divide by 4 clock, and when set to 0 it uses a divide by 12 clock. T0M: Timer 0 clock select: When T0M is set to 1, timer 0 uses a divide by 4 clock, and when ISSFA Ver. A 2010/06

9 set to 0 it uses a divide by 12 clock. MD2-0: Stretch MOVX select bits: These three bits are used to select the stretch value for the MOVX instruction. Using a variable MOVX length enables the user to access slower external memory devices or peripherals without the need for external circuits. The RD or WR strobe will be stretched by the selected interval. When accessing the on-chip SRAM, the MOVX instruction is always in 2 machine cycles regardless of the stretch setting. By default, the stretch has value of 1. If the user needs faster accessing, then a stretch value of 0 should be selected. MD2 MD1 MD0 Stretch value MOVX duration machine cycles machine cycles (Default) machine cycles machine cycles machine cycles machine cycles machine cycles machine cycles Time-out values for the watchdog timer WD1 WD0 Watchdog Interval Number of Clocks MHz 25MHz ms ms 5.24 ms ms ms ms ms ms ms ms ms ms The Watchdog timer will de disabled by a power-on/fail reset. The Watchdog timer reset does not disable the watchdog timer, but will restart it. In general, software should restart the timer to put it into a known state. The default Watchdog time-out is 2 17 clocks, which is the shortest time-out period. The EWT, WDIF and RWT bits are protected by the Timed Access procedure. This prevents software from accidentally enabling or disabling the watchdog timer. More importantly, it makes it highly improbable that errant code can enable or disable the watchdog timer. ISSFA Ver. A 2010/06

10 附件二 : 中斷致能及優先權設定不同說明 1. SM59R09A5/SM59R09A3 與 W77E58 中斷功能比較 : 新茂 SM59R09A5 提供 15 組中斷源 SM59R09A3 提供 13 組中斷源,W77E58 只有 12 組 新茂提供 4 階中斷優先權設定,W77E58 只有 2 階 中斷源旗標 SM59R09A5 之中斷向量 SM59R09A3 之中斷向量 W77E58 之中斷向量 IE0 External interrupt 0 0x03H 0x03H 0x03H TF0 Timer 0 interrupt 0x0BH 0x0BH 0x0BH IE1 External interrupt 1 0x13H 0x13H 0x13H TF1 Timer 1 interrupt 0x1BH 0x1BH 0x1BH RI0/TI0 Serial channel 0 interrupt 0x23H 0x23H 0x23H TF2/EXF2 Timer 2 interrupt 0x2BH 0x2BH 0x2BH PWMIF PWM interrupt 0x43H 0x43H 無 SPIIF SPI interrupt 0x4BH 0x4BH 無 ADCIF A/D converter interrupt 0x53H 0x53H 無 KBIIF keyboard Interface interrupt 0x5BH 0x5BH 無 LVIIF Low Voltage Interrupt 0x63H 0x63H 無 IICIF IIC interrupt 0x6BH 0x6BH 無 RI1/TI1 Serial channel 1 interrupt 0x83H 0x83H 0x3BH RTC/ALARM interrupt 008Bh 無 無 Comparator interrupt 0093h 無無 PCA Same as TF2 Same as TF2 無 IE2 External interrupt 2 無無 0x43H IE3 External interrupt 3 無無 0x4BH IE4 External interrupt 4 無無 0x53H IE5 External interrupt 5 無無 0x5BH Watchdog Timer 無無 0x63H 2. SM59R09A5/SM59R09A3 與 W77E58 中斷特殊功能暫存器比較 : 特殊功能暫存器名稱 SM59R09A5/SM59R09A3 名稱及位址 W77E58 名稱及位址 中斷致能 0 IEN0 (0xA8H) IE (0xA8H) 中斷致能 1 IEN1 (0xB8H) EIE(0xE8H) 中斷致能 2 IEN2 (0x9AH) 無 中斷優先設定 0 IP0 (0xA9H) IP (0xB8H) 中斷優先設定 1 IP1 (0xB9H) EIP(0xF8H) ISSFA Ver. A 2010/06

11 3. SM59R09A5/SM59R09A3 與 W77E58 中斷之特殊功能暫存器說明 : a. SM59R09A5/SM59R09A3 中斷功能使用之暫存器說明 : Mnemonic: IEN0 Address: A8h EA - ET2 ES0 ET1 EX1 ET0 EX0 00h EA: EA=0 Disable all interrupt. EA=1 Enable all interrupt. ET2: ET2=0 Disable Timer 2 overflow or external reload interrupt. ET2=1 Enable Timer 2 overflow or external reload interrupt. ES0: ES0=0 Disable Serial channel 0 interrupt. ES0=1 Enable Serial channel 0 interrupt. ET1: ET1=0 Disable Timer 1 overflow interrupt. ET1=1 Enable Timer 1 overflow interrupt. EX1: EX1=0 Disable external interrupt 1. EX1=1 Enable external interrupt 1. ET0: ET0=0 Disable Timer 0 overflow interrupt. ET0=1 Enable Timer 0 overflow interrupt. EX0: EX0=0 Disable external interrupt 0. EX0=1 Enable external interrupt 0. Mnemonic: IEN1 Address: B8h EXEN2 - IEIIC IELVI IEKBI IEADC IESPI IEPWM 00h EXEN2: Timer 2 reload interrupt enable. EXEN2 = 0 Disable Timer 2 external reload interrupt. EXEN2 = 1 Enable Timer 2 external reload interrupt. IEIIC: IIC interrupt enable. IEIICS = 0 Disable IIC interrupt. IEIICS = 1 Enable IIC interrupt. IELVI: LVI interrupt enable. IELVI = 0 Disable LVI interrupt. IELVI = 1 Enable LVI interrupt. IEKBI: KBI interrupt enable. IEKBI = 0 Disable KBI interrupt. IEKBI = 1 Enable KBI interrupt. IEADC: A/D converter interrupt enable IEADC = 0 Disable ADC interrupt. IEADC = 1 Enable ADC interrupt. IESPI: SPI interrupt enable. IESPI = 0 Disable SPI interrupt. IESPI = 1 Enable SPI interrupt. IEPWM: PWM interrupt enable. IEPWM = 0 Disable PWM interrupt. IEPWM = 1 Enable PWM interrupt. ISSFA Ver. A 2010/06

12 Mnemonic: IEN2 Address: 9Ah ECmpI ERTC ES1 00h ECmpI: (only SM59R09A5 have) ECmpI =0 Disable Comparator interrupt. ECmpI =1 Enable Comparator interrupt (include comparator_0 and comparator_1). ERTC: (only SM59R09A5 have) ERTC =0 Disable RTC interrupt. ERTC =1 Enable RTC interrupt (include Periodical and Alarm Int). ES1: ES1=0 Disable Serial channel 1 interrupt. ES1=1 Enable Serial channel 1 interrupt. Mnemonic: IP0 Address: A9h - - IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0 00h Mnemonic: IP1 Address: B9h - - IP1.5 IP1.4 IP1.3 IP1.2 IP1.1 IP1.0 00h SM59R09A5/SM59R09A3 Priority levels IP1.x IP0.x Priority Level 0 0 Level0 (lowest) 0 1 Level1 1 0 Level2 1 1 Level3 (highest) SM59R09A5/SM59R09A3 Groups of priority Bit Group IP1.0, IP0.0 External interrupt 0 Serial channel 1 interrupt PWM interrupt IP1.1, IP0.1 Timer 0 interrupt RTC/ALARM interrupt (only SM59R09A5 have) SPI interrupt IP1.2, IP0.2 External interrupt 1 Comparator interrupt (only SM59R09A5 have) ADC interrupt IP1.3, IP0.3 Timer 1 interrupt - KBI interrupt IP1.4, IP0.4 Serial channel 0 interrupt - LVI interrupt IP1.5, IP0.5 Timer 2 interrupt - IIC interrupt ISSFA Ver. A 2010/06

13 SM59R09A5/SM59R09A3 Polling sequence Interrupt source External interrupt 0 Serial channel 1 interrupt PWM interrupt Timer 0 interrupt RTC/ALARM interrupt (only SM59R09A5 have) SPI interrupt External interrupt 1 Comparator interrupt (only SM59R09A5 have) ADC interrupt Timer 1 interrupt KBI interrupt Serial channel 0 interrupt LVI interrupt Timer 2 interrupt IIC interrupt Sequence Polling sequence b. W77E58 中斷功能使用之暫存器說明 : Mnemonic: IE Address: A8h EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 00h EA: EA=0 Disable all interrupt. EA=1 Enable all interrupt. ES1: ES1=0 Disable Serial Port 1 interrupt. ES1=1 Enable Serial Port 1 interrupt. ET2: ET2=0 Disable Timer 2 overflow or external reload interrupt. ET2=1 Enable Timer 2 overflow or external reload interrupt. ES0: ES0=0 Disable Serial channel 0 interrupt. ES0=1 Enable Serial channel 0 interrupt. ET1: ET1=0 Disable Timer 1 overflow interrupt. ET1=1 Enable Timer 1 overflow interrupt. EX1: EX1=0 Disable external interrupt 1. EX1=1 Enable external interrupt 1. ET0: ET0=0 Disable Timer 0 overflow interrupt. ET0=1 Enable Timer 0 overflow interrupt. EX0: EX0=0 Disable external interrupt 0. EX0=1 Enable external interrupt 0. ISSFA Ver. A 2010/06

14 Mnemonic: EIE Address: E8h EWDI EX5 EX4 EX3 EX2 00h EWDI: Watchdog timer interrupt enable. EWDI = 0 Disable Watchdog timer interrupt. EWDI = 1 Enable Watchdog timer interrupt. EX5: External Interrupt 5 enable. EX5 = 0 Disable External Interrupt 5. EX5 = 1 Enable External Interrupt 5. EX4: External Interrupt4 enable EX4 = 0 Disable External Interrupt4. EX4 = 1 Enable External Interrupt4. EX3: External Interrupt3 enable. EX3 = 0 Disable External Interrupt3. EX3 = 1 Enable External Interrupt3. EX2: External Interrupt2 enable. EX2 = 0 Disable External Interrupt2. EX2 = 1 Enable External Interrupt2. Mnemonic: IP Address: B8h - PS1 PT2 PS0 PT1 PX1 PT0 PX0 00h PS1: This bit defines the Serial port 1 interrupt priority. PS = 1 sets it to higher priority level. PT2: This bit defines the Timer 2 interrupt priority. PT2 = 1 sets it to higher priority level. PS0: This bit defines the Serial port 0 interrupt priority. PS = 1 sets it to higher priority level. PT1: This bit defines the Timer 1 interrupt priority. PT1 = 1 sets it to higher priority level. PX1: This bit defines the External interrupt 1 priority. PX1 = 1 sets it to higher priority level. PT0: This bit defines the Timer 0 interrupt priority. PT0 = 1 sets it to higher priority level. PX0: This bit defines the External interrupt 0 priority. PX0 = 1 sets it to higher priority level. Mnemonic: EIP Address: F8h PWDI PX5 PX4 PX3 PX2 00h PWDI: Watchdog timer interrupt priority. PX5: External Interrupt 5 Priority. = 0 - Low priority = 1 - High priority PX4: External Interrupt 4 Priority. = 0 - Low priority = 1 - High priority PX3: External Interrupt 3 Priority. ISSFA Ver. A 2010/06

15 = 0 - Low priority = 1 - High priority PX2: External Interrupt 2 Priority. = 0 - Low priority = 1 - High priority W77E58 Priority structure of interrupts Source Flag Priority Level External Interrupt 0 IE0 1(Highest) Timer 0 Overflow TF0 2 External Interrupt 1 IE1 3 Timer 1 Overflow TF1 4 Serial Port RI+TI 5 Timer 2 Overflow TF2+EXF2 6 Serial Port 1 RI_1+TI_1 7 External Interrupt 2 IE2 8 External Interrupt 3 IE3 9 External Interrupt 4 IE4 10 External Interrupt 5 IE5 11 Watchdog Timer WDIF 12(Lowest) ISSFA Ver. A 2010/06

16 附件三 : 雙串口設定不同說明 1. SM59R09A5/SM59R09A3 與 W77E58 雙串口功能比較 : 新茂 SM59R09A5/ SM59R09A 之第二組串口接腳與 W77E58 同樣位於 P1.2 及 P1.3, 但新茂還可將第 二組串口接腳切換至 P4.2 及 P4.3 新茂第二組串口中斷向量位於 0x83H,W77E58 第二組串口中斷向量位於 0x3BH 2. SM59R09A5/SM59R09A3 與 W77E58 雙串口特殊功能暫存器比較 : 特殊功能暫存器名稱 SM59R09A5/SM59R09A3 名稱及位址 W77E58 名稱及位址 串口 0 控制 S0CON (0x98H) SCON (0x98H) 串口 0 資料暫存器 S0BUF (0x99H) SBUF(0x99H) 串口 0 重載低位元暫存器 S0RELL(0xAAH) 無 串口 0 重載高位元暫存器 S0RELH(0xBAH) 無 串口 1 腳位控制暫存器 AUX(0x91H) 無 串口 1 控制 S1CON (0x9BH) SCON1(0xC0H) 串口 1 資料暫存器 S1BUF (0x9CH) SBUF1 (0xC1H) 串口 1 重載低位元暫存器 S1RELL(0x9DH) 無 串口 1 重載高位元暫存器 S1RELH(0xBBH) 無 串口 0 從機位址 無 SADDR(0xA9H) 串口 0 從機位址致能 無 SADEN(0xB9H) 串口 1 從機位址 無 SADDR1(0xAAH) 串口 1 從機位址致能 無 SADEN1(0xBAH) 3. SM59R09A5/SM59R09A3 與 W77E58 雙串口之特殊功能暫存器說明 : a. SM59R09A5/SM59R09A3 雙串口功能使用之暫存器說明 : Mnemonic: PCON Address: 87h SMOD MDUF STOP IDLE 40h SMOD: This bit doubles the serial port baud rate in mode 1, 2, and 3 when set to 1. Mnemonic: AUX Address: 91h BRS - P4SPI P4UR1 P4IIC P0KBI P2PWM DPS 00H ISSFA Ver. A 2010/06

17 BRS: Baud rate generator at Serial interface 0 modes 1 and 3 SMOD 2 FOSC BRS = 0; Baud Rate = TH1 ( ) SMOD 2 FOSC BRS = 1; Baud Rate = ( 2 S0REL) P4UR1: P4UR1 = 0 Serial interface 1 function on P1. P4UR1 = 1 Serial interface 1 function on P4. P4UR1 RXD1 TXD1 0 P1.2 P1.3 1 P4.2 P4.3 Mnemonic: S0CON Address: 98h SM0 SM1 SM20 REN0 TB80 RB80 TI0 RI0 00h SM0,SM1: Serial Port 0 mode selection. SM0 SM1 Mode Description Board Rate Shift register Fosc/ bit UART Variable bit UART Fosc/32 or Fosc/ bit UART Variable SM20: Enables multiprocessor communication feature REN0: If set, enables serial reception. Cleared by software to disable reception. TB80: The 9 th transmitted data bit in modes 2 and 3. Set or cleared by the CPU depending on the function it performs such as parity check, multiprocessor communication etc. RB80: In modes 2 and 3, it is the 9 th data bit received. In mode 1, if SM20 is 0, RB80 is the stop bit. In mode 0, this bit is not used. Must be cleared by software. TI0: Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software. RI0: Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software. Mnemonic: S1CON Address: 9Bh SM - SM21 REN1 TB81 RB81 TI1 RI1 00h SM: Serial Port 1 mode select. SM Mode Description Baud Rate 0 A 9-bit UART Variable 1 B 8-bit UART Variable FOSC Baud rate generator at Serial interface 1; Baud Rate = ( 2 S1REL) SM21: Enables multiprocessor communication feature. REN1: If set, enables serial reception. Cleared by software to disable reception. TB81: The 9 th transmitted data bit in mode A. Set or cleared by the CPU depending ISSFA Ver. A 2010/06

18 on the function it performs such as parity check, multiprocessor communication etc. RB81: In mode A, it is the 9 th data bit received. In mode B, if SM21 is 0, RB81 is the stop bit. Must be cleared by software. TI1: Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software. RI1: Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software. b. W77E58 雙串口功能使用之暫存器說明 : Mnemonic: PCON Address: 87h SMOD SMOD STOP IDLE 00h SMOD: This bit doubles the serial port baud rate in mode 1, 2, and 3 when set to 1. SMOD0: Framing Error Detection Enable: When SMOD0 is set to 1, then SCON.7 (SCON1.7) indicates a Frame Error and acts as the FE(FE_1) flag. When SMOD0 is 0, then SCON.7(SCON1.7) acts as per the standard 8052 function. Mnemonic: SCON Address: 98h SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00h SM0/FE: Serial port 0, Mode 0 bit or Framing Error Flag: The SMOD0 bit in PCON SFR determines whether this bit acts as SM0 or as FE. The operation of SM0 is described below. When used as FE, this bit will be set to indicate an invalid stop bit. This bit must be manually cleared in software to clear the FE condition. SM0,SM1: Serial Port 0 mode selection. SM0 SM1 Mode Description Length Board Rate Synchronous 8 4/12 Tclk Asynchronous 10 Variable Asynchronous 11 Fosc/32 or Fosc/ Asynchronous 11 Variable SM2: Multiple processors communication. Setting this bit to 1 enables the multiprocessor communication feature in mode 2 and 3. In mode 2 or 3, if SM2 is set to 1, then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1, then RI will not be activated if a valid stop bit was not received. In mode 0, the SM2 bit controls the serial port clock. If set to 0, then the serial port runs at a divide by 12 clock of the oscillator. This gives compatibility with the standard When set to 1, the serial clock become divide by 4 of the oscillator clock. This results in faster synchronous serial communication. REN: Receive enable: When set to 1 serial reception is enabled, otherwise reception is disabled. TB8: This is the 9th bit to be transmitted in modes 2 and 3. This bit is set and cleared by software as desired. RB8: In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2 = 0, RB8 is the stop bit that was received. In mode 0 it has no function. TI: Transmit interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in all other modes during serial ISSFA Ver. A 2010/06

19 transmission. This bit must be cleared by software. RI: Receive interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bits time in the other modes during serial reception. However the restrictions of SM2 apply to this bit. This bit can be cleared only by software. Mnemonic: SADDR Address: A9h 00h SADDR: The SADDR should be programmed to the given or broadcast address for serial port 0 to which the slave processor is designated. Mnemonic: SADDR1 Address: AAh 00h SADDR1: The SADDR1 should be programmed to the given or broadcast address for serial port 1 to which the slave processor is designated. Mnemonic: SADEN Address: B9h 00h SADEN: This register enables the Automatic Address Recognition feature of the Serial port 0. When a bit in the SADEN is set to 1, the same bit location in SADDR will be compared with the incoming serial data. When SADEN.n is 0, then the bit becomes a "don't care" in the comparison. This register enables the Automatic Address Recognition feature of the Serial port 0. When all the bits of SADEN are 0, interrupt will occur for any incoming address. Mnemonic: SADEN1 Address: BAh 00h SADEN1: This register enables the Automatic Address Recognition feature of the Serial port 1. When a bit in the SADEN1 is set to 1, the same bit location in SADDR1 will be compared with the incoming serial data. When SADEN1.n is 0, then the bit becomes a "don't care" in the comparison. This register enables the Automatic Address Recognition feature of the Serial port 1. When all the bits of SADEN1 are 0, interrupt will occur for any incoming address. ISSFA Ver. A 2010/06

20 Mnemonic: SCON1 Address: C0h SM0_1/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00h SM0_1/FE_1: Serial port 1, Mode 0 bit or Framing Error Flag 1: The SMOD0 bit in PCON SFR determines whether this bit acts as SM0_1 or as FE_1. the operation of SM0_1 is described below. When used as FE_1, this bit will be set to indicate an invalid stop bit. This bit must be manually cleared in software to clear the FE_1 condition. SM0_1,SM1_1: Serial Port 1 mode selection. SM0_1 SM1_1 Mode Description Length Board Rate Synchronous 8 4/12 Tclk Asynchronous 10 Variable Asynchronous 11 Fosc/32 or Fosc/ Asynchronous 11 Variable SM2_1: Multiple processors communication. Setting this bit to 1 enables the multiprocessor communication feature in mode 2 and 3. In mode 2 or 3, if SM2_1 is set to 1, then RI_1 will not be activated if the received 9th data bit (RB8_1) is 0. In mode 1, if SM2_1 = 1, then RI_1 will not be activated if a valid stop bit was not received. In mode 0, the SM2_1 bit controls the serial port 1 clock. If set to 0, then the serial port 1 runs at a divide by 12 clock of the oscillator. This gives compatibility with the standard When set to 1, the serial clock become divide by 4 of the oscillator clock. This results in faster synchronous serial communication. REN_1: Receive enable: When set to 1 serial reception is enabled, otherwise reception is disabled. TB8_1: This is the 9th bit to be transmitted in modes 2 and 3. This bit is set and cleared by software as desired. RB8_1: In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2_1 = 0, RB8_1 is the stop bit that was received. In mode 0 it has no function. TI_1: Transmit interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in all other modes during serial transmission. This bit must be cleared by software. RI_1: Receive interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bits time in the other modes during serial reception. However the restrictions of SM2_1 apply to this bit. This bit can be cleared only by software. ISSFA Ver. A 2010/06

21 附件四 : 計時器 2 設定不同說明 1. SM59R09A5/SM59R09A3 與 W77E58 計時器 2 功能比較 : 新茂 SM59R09A5/ SM59R09A3 之計時器 2 除了可當 16 位元之計時器, 還有 4 個通道之比較 捕獲及 重載之功能, 類似於可編程計數器陣列 (PCA) W77E58 之計時器 2 只可當 16 位元之計時器用 2. SM59R09A5/SM59R09A3 與 W77E58 計時器 2 之特殊功能暫存器比較 : 特殊功能暫存器名稱 SM59R09A5/SM59R09A3 名稱及位址 W77E58 名稱及位址 計時器 2 控制暫存器 T2CON (0xA8H) T2CON (0xA8H) 計時器 2 模式控制暫存器 T2MOD(0xA9H) 計時器 2 捕獲重載低位元 CRCL(0xCAH) RCAP2L(0xCAH) 計時器 2 捕獲重載高位元 CRCH(0xCBH) RCAP2H(0xCBH) 計時器 2 低位元 TL2(0xCCH) TL2(0xCCH) 計時器 2 高位元 TH2(0xCDH) TH2(0xCDH) CKCON(0xA8H) 比較及補獲通道選擇暫存器 AUX2(0x92H) 比較及補獲控制暫存器 CCCON(0xC9H) 比較及補獲致能暫存器 1 CCEN(0xC1H) 比較及補獲致能暫存器 2 CCEN2(0xD1H) 比較 捕獲及重載通道 1 低位元 CCL1(0xC2H) 比較 捕獲及重載通道 1 高位元 CCH1(0xC3H) 比較 捕獲及重載通道 2 低位元 CCL2(0xC4H) 比較 捕獲及重載通道 2 高位元 CCH2(0xC5H) 比較 捕獲及重載通道 3 低位元 CCL3(0xC6H) 比較 捕獲及重載通道 3 高位元 CCH3(0xC7H) 3. SM59R09A5/SM59R09A3 與 W77E58 計時器 2 之特殊功能暫存器說明 : a. SM59R09A5/SM59R09A3 計時器 2 功能使用之暫存器說明 : Mnemonic: T2CON Address: C8h T2PS[2:0] T2R[1:0] - T2I[1:0] 00H T2PS[2:0]: Prescaler select bit: T2PS = 000 timer 2 is clocked with the oscillator frequency. T2PS = 001 timer 2 is clocked with 1/2 of the oscillator frequency. ISSFA Ver. A 2010/06

22 T2PS = 010 timer 2 is clocked with 1/4 of the oscillator frequency. T2PS = 011 timer 2 is clocked with 1/6 of the oscillator frequency. T2PS = 100 timer 2 is clocked with 1/8 of the oscillator frequency. T2PS = 101 timer 2 is clocked with 1/12 of the oscillator frequency. T2PS = 110 timer 2 is clocked with 1/24 of the oscillator frequency. T2R[1:0]: Timer 2 reload mode selection T2R[1:0] = 0X Reload disabled T2R[1:0] = 10 Mode 0 T2R[1:0] = 11 Mode 1 T2I[1:0]: Timer 2 input selection T2I[1:0] = 00 Timer 2 stop T2I[1:0] = 01 Input frequency f/12 or f/24 T2I[1:0] = 10 Timer 2 is incremented by external signal at pin T2 T2I[1:0] = 11 internal clock input is gated to the Timer 2 Mnemonic: AUX2 Address: 92h P42CC[1: 0] 00H P42CC[1: 0] 00: Capture/Compare function on Port1. 01: Capture/Compare function on Port2 10: Capture/Compare function on Port4 11: reserved P42CC[1: 0] CC0 CC1 CC2 CC3 00 P1.0 P1.1 P1.3 P P2.0 P2.1 P2.2 P P4.0 P4.1 P4.2 P4.3 Mnemonic: CCCON Address: C9h CCI3 CCI2 CCI1 CCI0 CCF3 CCF2 CCF1 CCF0 00H CCI3: Compare/Capture 3 interrupt control bit. 1 is enable. CCI2: Compare/Capture 2 interrupt control bit. 1 is enable. CCI1: Compare/Capture 1 interrupt control bit. 1 is enable. CCI0: Compare/Capture 0 interrupt control bit. 1 is enable. CCF3: Compare/Capture 3 flag set by hardware. This flag can be cleared by software. CCF2: Compare/Capture 2 flag set by hardware. This flag can be cleared by software. CCF1: Compare/Capture 1 flag set by hardware. This flag can be cleared by software. CCF0: Compare/Capture 0 flag set by hardware. This flag can be cleared by software. Compare/Capture interrupt share T2 interrupt vector. ISSFA Ver. A 2010/06

23 Mnemonic: CCEN Address: C1h -- COCAM1[2:0] -- COCAM0[2:0] 00H COCAM1[2:0]: 000: Compare/Capture disable 001: Compare enable but no output on Pin 010: Compare mode 0 011: Compare mode 1 100: Capture on rising edge at pin CC1 101: Capture on falling edge at pin CC1 110: Capture on both rising and falling edge at pin CC1 111: Capture on write operation into register CC1 COCAM0[2:0]: 000: Compare/Capture disable 001: Compare enable but no output on Pin 010: Compare mode 0 011: Compare mode 1 100: Capture on rising edge at pin CC0 101: Capture on falling edge at pin CC0 110: Capture on both rising and falling edge at pin CC0 111: Capture on write operation into register CC0 Mnemonic: CCEN2 Address: D1h -- COCAM3[2:0] -- COCAM2[2:0] 00H COCAM3[2:0]: 000: Compare/Capture disable 001: Compare enable but no output on Pin 010: Compare mode 0 011: Compare mode 1 100: Capture on rising edge at pin CC3 101: Capture on falling edge at pin CC3 110: Capture on both rising and falling edge at pin CC3 111: Capture on write operation into register CC3 COCAM2[2:0]: 000: Compare/Capture disable 001: Compare enable but no output on Pin 010: Compare mode 0 011: Compare mode 1 100: Capture on rising edge at pin CC2 101: Capture on falling edge at pin CC2 110: Capture on both rising and falling edge at pin CC2 111: Capture on write operation into register CC2 b. W77E58 計時器 2 功能使用之暫存器說明 : Mnemonic: T2CON Address: C8h TF2 EXF2 RCLK TCLK EXEN2 TR2 C / T2 CP / RL2 00H TF2: Timer 2 overflow flag: This bit is set when Timer 2 overflows. It is also set when the count is equal to the capture register in down count mode. It can be set only if RCLK and TCLK are both 0. It is cleared only by software. Software can also set or clear this bit. ISSFA Ver. A 2010/06

24 EXF2: Timer 2 External Flag: A negative transition on the T2EX pin (P1.1) or timer 2 overflow will cause this flag to set based on the CP / RL2, EXEN2 and DCEN bits. If set by a negative transition, this flag must be cleared by software. Setting this bit in software or detection of a negative transition on T2EX pin will force a timer interrupt if enabled. RCLK: Receive Clock Flag: This bit determines the serial port 0 time-base when receiving data in serial modes 1 or 3. If it is 0, then timer 1 overflow is used for baud rate generation, otherwise timer 2 overflow is used. Setting this bit forces timer 2 in baud rate generator mode. TCLK: Transmit Clock Flag: This bit determines the serial port 0 time-base when transmitting data in modes 1 and 3. If it is set to 0, the timer 1 overflow is used to generate the baud rate clock otherwise timer 2 overflow is used. Setting this bit forces timer 2 in baud rate generator mode. EXEN2: Timer 2 External Enable. This bit enables the capture/reload function on the T2EX pin if Timer 2 is not generating baud clocks for the serial port. If this bit is 0, then the T2EX pin will be ignored, otherwise a negative transition detected on the T2EX pin will result in capture or reload. TR2: Timer 2 Run Control. This bit enables/disables the operation of timer 2. Clearing this bit will halt the timer 2 and preserve the current count in TH2, TL2. C/T2: Counter/Timer Select. This bit determines whether timer 2 will function as a timer or a counter. Independent of this bit, the timer will run at 2 clocks per tick when used in baud rate generator mode. If it is set to 0, then timer 2 operates as a timer at a speed depending on T2M bit (CKCON.5), otherwise it will count negative edges on T2 pin. CP/RL2: Capture/Reload Select. This bit determines whether the capture or reload function will be used for timer 2. If either RCLK or TCLK is set, this bit will be ignored and the timer will function in an auto-reload mode following each overflow. If the bit is 0 then auto-reload will occur when timer 2 overflows or a falling edge is detected on T2EX pin if EXEN2 = 1. If this bit is 1, then timer 2 captures will occur when a falling edge is detected on T2EX pin if EXEN2 =1. Mnemonic: T2MOD Address: C9h HC5 HC4 HC3 HC2 T2CR T2OE DCEN 00H HC5: Hardware Clear INT5 flag. Setting this bit allows the flag of external interrupt 5 to be automatically cleared by hardware while entering the interrupt service routine. HC4: Hardware Clear INT4 flag. Setting this bit allows the flag of external interrupt 4 to be automatically cleared by hardware while entering the interrupt service routine. HC3: Hardware Clear INT3 flag. Setting this bit allows the flag of external interrupt 3 to be automatically cleared by hardware while entering the interrupt service routine. HC2: Hardware Clear INT2 flag. Setting this bit allows the flag of external interrupt 3 to be automatically cleared by hardware while entering the interrupt service routine. T2CR: Timer 2 Capture Reset. In the Timer 2 Capture Mode this bit enables/disables hardware automatically reset Timer 2 while the value in TL2 and TH2 have been transferred into the capture register. T2OE: Timer 2 Output Enable. This bit enables/disables the Timer 2 clock out function. DCEN: Down Count Enable: This bit, in conjunction with the T2EX pin, controls the direction that timer 2 counts in 16-bit auto-reload mode. ISSFA Ver. A 2010/06

25 Mnemonic: CKCON Address: 8Eh WD1 WD0 T2M T1M T0M MD2 MD1 MD0 04H WD1-0: Watchdog timer mode select bits: These bits determine the time-out period for the watchdog timer. In all four time-out options the reset time-out is 512 clocks more than the interrupt timeout period. WD1 WD0 Interrupt time-out Reset time-out T2M: Timer 2 clock select: When T2M is set to 1, timer 2 uses a divide by 4 clock, and when set to 0 it uses a divide by 12 clock. T1M: Timer 1 clock select: When T1M is set to 1, timer 1 uses a divide by 4 clock, and when set to 0 it uses a divide by 12 clock. T0M: Timer 0 clock select: When T0M is set to 1, timer 0 uses a divide by 4 clock, and when set to 0 it uses a divide by 12 clock. MD2-0: Stretch MOVX select bits: These three bits are used to select the stretch value for the MOVX instruction. Using a variable MOVX length enables the user to access slower external memory devices or peripherals without the need for external circuits. The RD or WR strobe will be stretched by the selected interval. When accessing the on-chip SRAM, the MOVX instruction is always in 2 machine cycles regardless of the stretch setting. By default, the stretch has value of 1. If the user needs faster accessing, then a stretch value of 0 should be selected. MD2 MD1 MD0 Stretch value MOVX duration machine cycles machine cycles (Default) machine cycles machine cycles machine cycles machine cycles machine cycles machine cycles ISSFA Ver. A 2010/06