Chapter 7. Signed/Unsigned Binary Numbers. Digital Arithmetic and Arithmetic Circuits. Unsigned Binary Arithmetic. Basic Rules (Unsigned)

Transcription

1 Chapter 7 Digital rithmetic and rithmetic Circuits igned/unsigned inary Numbers igned inary Number: binary number of fixed length whose sign (+/ ) is represented by one bit (usually M) and its magnitude by the remaining bits. Unsigned inary Number: binary number of fixed length whose sign is not specified by a bit. ll bits are magnitude and the sign is assumed +. 2 Unsigned inary rithmetic asic Rules (Unsigned) um: Result of an ddition Operation of two (or more) binary numbers (operands). Carry: digit (or bit) that is carried over to the next most significant bit during an n-it addition operation. The carry bit is a if the result was too large to be expressed in n bits. 3 One-it Unsigned ddition C C in out + + = + + = + + = + + = 4 inary ddition Examples carry to next + + Carry out bit 5 asic ubtraction asic ubtraction of x = a b, with a = minuend( 被減數 ), b = subtrahend ( 減數 ), and x = difference or result. Requires a orrow it if a < b. There are other forms of subtraction such as 2 s Complement ddition used by microprocessors (such as in a PC). 6

2 asic ubtraction Rules in 此處應該為 orrow Diff = = = = 7 - inary ubtraction with orrow Examples - () orrow tage () orrow ripples to L 8 igned inary Numbers igned inary Numbers 2 ign it: bit (usually the M) that indicates whether a number is positive (= ) or negative (= ). Magnitude its: The bits of a signed binary number that tell how large it is in value. 9 True-Magnitude Form: form of signed binary whose magnitude bits are the TRUE binary form (not complements). lso called sign-magnitude format igned inary Numbers 3 s Complement: form of signed binary in which negative numbers are created by complementing all bits. 2 s Complement: form of signed binary in which the negative numbers are created by complementing all the bits and adding a ( s Complement + ). True-Magnitude Form 5-it Numbers Negative ign ( = ) +25 = (Note sign bit (M) ign = ) 25 = (ame as +25 with sign = ) +2 = 2 = 2 2

3 s Complement Form 8-it s Complement Negative ( = ) +57 = 57 = (ll its Inverted) +72 = 72 = 3 2 s Complement Form Used in MPU (PC) rithmetic 57 = - 57 = + 原講義錯誤 = + 4 igned inary ddition (8-it) igned ddition Positive ( = ) + 3 = + 75 = imilar to binary addition with a sign bit. 5 ubtraction with s Complement dd the s Complement and then Carry. + 8 = ( + 8) = - 65 = ( + 65) = + (' s Comp 65) Uses an End around carry addition method. 6 2 s Complement ubtraction dd 2 s Complement to Minuend. + 8 = + 65 = + 65 = + Discard Carry it from Result 只要記住以 2 s complement 來運算,Carry 一律捨棄即可 7 Negative Results If the True-Magnitude Form is used for subtraction, the results are incorrect. If the result is from s or 2 s Complement and the result is negative ( = ), the magnitude is found by taking the complement of the result.( 當運算結果的 ign bit 為 時表示結果為 Negative number, 此時僅需再轉換為該數值之 Complement 即知是負多少 ; 至於要轉換為 s complement 或是 2 s complement 就看原來是使用哪一種負數表示法而定 ) 8 3

4 Negative Result Example 2 s Complement Negative Result (65 8) + 65 = - 8 = (2' s C.) Final Result + Invert dd + =(-5 ) = (5 ) = (+5 ) 9 Range of igned Numbers Range of Positive Numbers is to 2 (n-) for a number with n bits. Range of Negative Numbers is to 2 (n-) for a number with n bits. 8-it Example: 8-it Number Range is 2 (n-) x +2 (n-) or 28 to ign it Overflow Overflow: n erroneous carry into the sign bit of a signed binary number Results from a sum or difference that is larger than can be represented by the magnitude bits. Results in a False Positive or False Negative Number. 只有相同符號運算時才會有 Overflow 發生的可能 ( 例如 :++;--) 檢查 ign bit 是否改變即知是否發生 Overflow 2 False Negative Overflow ddition of two 8-it Positive Numbers: + 75 = + 96 = + Result is Negative (False) Two positive numbers added with a result greater than the range of +27 for 8-bit numbers causes an overflow. 22 False Positive Overflow ddition of two 8-it Negative Numbers: 8 = 65 = + oth in 2 s complement form! Result is Positive (False) Two Negative numbers were added to produce a False Positive Result due to overflowing the negative range of 8-bit numbers ( to 28). 23 Hexadecimal ddition imilar to decimal addition with a range of digits of to 9 and to F. Examples: F + = F + F = E F + F + = F 24 4

5 Hexadecimal ddition Hex 263H + 9CH For sums greater than 5, subtract 6 and carry to the next position. Carry Hex = Decimal Equivalent ( 2)( 6) ()( 3) ( )()( 9)(2) (3) (6)(2)(5) ( 2)( 6) ()(3) ( )()( 9)(2) ( 4)( ) ( 4)(5) 44FH 先轉成十進位 25 Hexadecimal ubtraction Hex 263H 9CH To subtract the least significant digit, borrowh (6 from the previous position. orrow Hex = Decimal Equivalent (2)(6)()(3) ()()(9)(2) ()(6 + 6) ()(6 + 3) - () () ()(2) C7H (9) (2) () ( 7) ) 26 CD Codes CD Code (inary-coded Decimal): code used to represent each decimal digit of a number by a 4-it inary Value. Valid Digits for to 9 are to. The binary codes to are invalid Called an 842 Code due to the decimal weight of each bit position. CD Examples Each digit is a 4-it inary group: (84) = (4987) = CD Excess-3 Code CD Code formed by adding 3 () to its true 4-bit binary value. Excess-3 is a self-complementing code: negative code equivalent can be found by inverting the binary bits of the positive code Inverting the bits of the Excess-3 digit yields 9 s Complement of the decimal equivalent. ee next page for reference. 29 Excess-3 Code Decimal Digit 842 Excess

6 Excess-3 Examples 3 = + = = 6 in E3. = + = = 4 in E3. If we complement = in E3, this is the code for an 8. 9 s Complement of = (9 ) = 8 (elf- Complement) Gray Code binary code that progresses so that only one bit changes between two successive codes Gray Code and inary inary: b 3 b 2 b b Gray: g 3 g 2 g g Gray code bits can be defined as follows: g 3 = b 3 g 2 = b 3 b 2 g = b 2 b CII Code merican tandard Code for Information Interchange. seven-bit alphanumeric code used to represent text letters, numerals, punctuation ( 標點符號 ), and special controls. n expanded 8-bit form is becoming more widespread. g = b b inary dders Half dder (H): circuit that will add two bits and produce a sum bit and a carry bit. Full dder (F): circuit that will add a carry bit from another H or F and two operand bits to produce a sum bit and a carry bit. 35 asic H ddition inary Two-it ddition Rules: + = + = + = 36 6

7 H Circuit asic Equations: = XOR, C = and where = um and C = Carry. Truth Table for H lock: Σ C OUT 原講義錯誤 Σ = + = C OUT = 37 H Circuit 38 Full dder asics dds a C IN input to the H block. Equations are modified as follows: C Σ OUT = ( ) C IN + = ( ) CIN F can be made from two H blocks and an OR Gate. 39 Full dder asics 4 Full dder asics Full dder asics

8 Parallel dders Parallel dders circuit, consisting of n full adders, that will add n-bit binary numbers. The output consists of n sum bits and a carry bit. C OUT of one full adder is connected to C IN of the next full adder Ripple Carry In the n-it Parallel dder (F tages) the Carryout is generated by the last stage (FN). This is called a Ripple Carry dder because the final carryout (Last tage) is based on a ripple through each stage by C IN at the L tage. 45 Ripple Carry 2 Each tage will have a propagation delay on the C IN to C OUT of one ND Gate and one OR Gate.(ee P.4; 必定先產生結果然後等待 Cin 的到來, 再做 ND, 最後經由 OR 輸出 ) 4-it Ripple Carry dder will then have a propagation delay on the final C OUT of 4 2 = 8 Gates. 32-it adder such as in an MPU in a PC could have a delay of 64 Gates. 46 Ripple Carry - 3 Look-head Carry Fast Carry or Look-head Carry: combinational network that generates the final C OUT directly from the operand bits ( to n, to n ). It is independent of the operations of each F tage (as the ripple carry is)

9 Look head Carry 2 Look head Carry 3 Fast Carry has a small propagation delay compared to the ripple carry. The fast carry delay is 3 Gates for a 4- it dder compared to 8 for the Ripple Carry Look head Carry 4 Using carry look-ahead to reduce the propagation delay Carry propagate: P i = i i Carry generate: G i = i i um: i = P i C i Carry: C i+ = G i +P i C i C = Input carry C = P C +G P i = i i C 2 = P C +G = P (G + P C ) + G = P G + P P C +G G i = i i 5 C 3 = P 2 C 2 +G 2 = P 2 P G + P 2 P P C + P 2 G + G 2 52 P i 與 G i 需一個 Gate 的 Delay 再加上此處的兩級, 因此共有三個 Gate 的 Delay time Look head Carry 6 Parallel dder Created in VHDL by using multiple instances of a full adder component in the top-level file of a VHDL design hierarchy

10 Parallel dder VHDL Full dder 55 ENTITY full_add I PORT( a, b, c_in : IN TD_LOGIC; c_out, sum : OUT TD_LOGIC; END full_add; RCHITECTURE adder OF full_add I EGIN c_out <= ((a xor b) and c_in) or (a and b); sum <= (a xor b) xor c_ini; END adder; 這是最基本 / 底層的 Component, 只有 ingle bit! 56 Parallel dder VHDL Requires a separate component file for a full adder, saved in a folder where the compiler can find it(i.e., in the Library path). component declaration statement is required in the top-level file of the design hierarchy( 要使用 Component 的上層電路必須要在 rchitecture 中加以宣告 ; 宣告 Component name 以及 I/O Port). component instantiation statement for each instance of the full adder component( 在 rchitecture 中還需要 Make Instances; 亦即建立 Component 實體 ). 57 Parallel dder VHDL Code ENTITY add4par I PORT( c : IN TD_LOGIC; a,b : IN TD_LOGIC_VECTOR (4 downto ); c4 : OUT TD_LOGIC; sum : OUT TD_LOGIC_VECTOR (4 downto )); END add4par; 這是 4 bit 的全加法器 ; 使用 Full_add 作為 Component! 58 Parallel dder VHDL Code 2 RCHITECTURE adder OF add4par I -- Component declaration. COMPONENT full_add PORT( a, b, c_in : IN TD_LOGIC; c_out, sum : OUT TD_LOGIC); END COMPONENT; Full_add 的所有 I/O Port 都需要再宣告一遍 -- Define a signal for the internal carry bits IGNL c : TD_LOGIC_VECTOR (3 downto ); Parallel dder VHDL Code 3 EGIN -- four component instantiation statements. adder : full_add Component Name PORT MP (a => a(), Instance Name b => b(), c_in => c, c_out => c() -- connects to c_in of adder 2. sum => sum()); END adder; Instance I/O 宣告一個 ignal c 用以串接內部訊號 59 6

11 VHDL Generate tatement ENTITY add4gen I PORT( c : IN TD_LOGIC; a,b : IN TD_LOGIC_VECTOR (4 downto ); c4 : OUT TD_LOGIC; sum : OUT TD_LOGIC_VECTOR (4 downto )); END add4gen; 這是 4 bit 的全加法器 ; 但使用 For Generate 敘述來簡化程式! 6 VHDL Generate tatement 2 RCHITECTURE adder OF add4gen I -- Component declaration COMPONENT full_add PORT( a, b, c_in :IN TD_LOGIC; c_out, sum : OUT TD_LOGIC); END COMPONENT; - - Defining a signal for internal carry bits. IGNL c : TD_LOGIC_VECTOR (4 downto ); 62 VHDL Generate tatement 3 EGIN c() <= c; -- Input port c mapped to internal signal (c) adders: FOR i IN to 4 GENERTE -- Implicit port mapping. Mapping 的順序必須與 Component 的 I/O Port 宣告順序相同 adder : full_add PORT MP (a(i), b(i), c(i-), c(i), sum (i)); END GENERTE; c4 <= c(4); -- Output port c4 mapped to internal signal c(4) END adder; 63 ubtractor (2 s Complement) The concept of ubtraction using 2 s Complement addition allows a Parallel F to be used. This could be used in a MPU LU (rithmetic Logic Unit) for ubtraction. The subtract operation involves adding the inverse( 就是取 的補數 )of the subtrahend( 減數 )to the minuend( 被減數 )and then adding a. The adding of a in the last step is equivalent to convert the subtrahend to its 2 s complement( 最後的加 等同於取減數 2 的補數與被減數相加 ). 64 ubtractor (2 s Complement) 2 Difference = = + + This operation can be done in a parallel n-it F by inverting ( to n ) and connecting C IN at the L tage to +5 V( 接 5V 就是最後要加 的意思 ). The circuit can be modified to allow either the DD or UTRCT operation to be performed. 65 ubtractor (2 s Complement) 2 66

12 Parallel inary dder/ubtractor XOR gates are used as programmable inverters to pass binary numbers (e.g., ) to the parallel adder in true or complemented form. When DD/U =, is complement ed. When DD/U =, is in its true form. 67 Parallel inary dder/ubtractor 這隻腳為 表示做減法用為 表示做加法用 68 Parallel inary dder/ubtractor VHDL Parallel inary dder/ubtractor ENTITY addsub4g I PORT( ub 為 表示做減法用 ub 為 表示做加法用 sub : IN IT; a,b : IN IT_VECTOR (4 downto ); c4 : OUT IT; sum : OUT IT_VECTOR (4 downto )); END addsub4g; 69 7 VHDL Parallel inary dder/ubtractor 2 RCHITECTURE adder OF addsub4g I COMPONENT full_add PORT( a, b, c_in : IN IT; c_out : OUT IT); END COMPONENT; - - Define a signal for internal carry bits IGNL c : IT_VECTOR (4 downto ); IGNL b_comp : IT_VECTOR (4 downto ); EGIN 7 VHDL Parallel inary dder/ubtractor add/subtract select to carry input (sub = for subtract) c() <= sub; adders: FOR i IN to 4 GENERTE --invert b for subtract function (b(i) xor,) --do not invert b for add function (b(i) xor ) b_comp(i) <= b(i) xor sub; adder: full_add PORT MP (a(i), b_comp(i), c(i -), c(i), sum (i)); END GENERTE; C4 <= C(4); END adder; 72 2

13 Overflow If the sign bits of both operands are the same and the sign bit of the sum is different from the operand sign bits, an overflow has occurred. Overflow is not possible if the sign bits of the operands are different from each other. 73 Overflow Examples dding two 8-bit negative numbers( 因為 M=): 8H + 8H H + (ign bit overflow; V = ) dding two 8-bit positive numbers( 因為 M=): 7FH + H 8H (ign bit overflow; V = ) 74 Overflow 8-bit Parallel dder ( ( ( = = = ign bit of ign bit of ign bit of ) ) sum) 75 Overflow Detector Truth Table ign bit 相異之兩數相加絕對不會 Overflow V = Σ + V Σ 76 Overflow Detector Truth Table CD dder Y 77 Parallel dder whose output sum is in groups of 4 bits, each representing a CD (842) Digit. asic design is a 4-it inary Parallel dder to generate a 4-it um of +. um is input to the four-bit input of a inary-to-cd Code Converter. 78 3

14 CD dder 79 4