TKT-3500 Microcontroller systems

Transcription

1 TKT-3500 Microcontroller systems Lec 5 IO part2: synchr. USART, SPI, I2C, GPIO Teemu Laukkarinen Department of Computer Systems Tampere University of Technology Fall 2011

2 Sources Original slides by Erno Salminen Robert Reese, Microprocessors: From Assembly to C with the PIC18Fxx2, Charles River Media, 2005 Tim Wilmshurst, Designing Embedded Systems with PIC Microcontrollers Principles and applications, Elsevier, Wikipedia TotalPhase Knowledge Base - Article #2/62

3 Contents Synchronous serial bus protocols USART in synchronous mode Separate data line and clock NOTE: not really a bus, since does not have built in support for master multiple slaves SPI - Serial peripheral interface Separate data lines and clock, chip select lines I2C - Inter integrated chip Only data line and clock CAN - controller area network One line synchronization (4 physical lines) USB universal serial bus One line synchronization (4 physical lines) #3/62

4 Update/reminder: Clocking: synchronous vs. asynchronous Luennoija selitti ekalla kerralla asian hivenen huonosti, joten lyhyt nopea ja (toivottavasti) selventävä kertaus! #4/62 a) Synchronous a common timing signal is established that dictates when individual bits can be read from the serial line i. Separate clock signal (two lines, obvious) ii. Clocking is encoded into data (so that receiver can synchronize to the senders clock, see iii) iii. Receiver s clock is synchronized to the data stream (one line) b) Asynchronous uses none of the above methods i-iii) sender and receiver agree on a common data rate Receiver reads bits when it thinks it should be ok Errors are a case of propability Simple HW, but lower bandwidth

5 Reminder: Synchronous serial IO ii) ii) Data strobe encoding Two lines: data line and strobe line Data line always contains the serial data, nothing special here Strobe encodes the clock, it has a pulse if data does not change -> Either Data or Strobe changes its logical value in one clock cycle, but never both Clock can be extracted with XOR from data and strobe line Better tolerance for wire delays compared to data+clk IEEE 1394 or FireWire uses this #5/62 Fig. 9.5 Data strobe encoding

6 Reminder: Synchronous serial IO iii) iii) Synchronization with one line Independently generated clocks of the same frequency might be out of phase PLL modifies receiver s clock to macth the sender s the data line must have enough changes within a particular time interval (transition density) so that PLL can synchronize itself continuously Thus, the line must be encoded to have enough transitions if the data does not have them Otherwise, PLL does not work Often, a start sequence is needed a b #6/62

7 Asynchronous serial IO Does not transmit the clock on any way Sender and receiver trust that other reads line at correct moments Does not guarantee a particular transition density the data line could remain in the same state, either 1 or 0 for the duration of the transmission after the initial state change indicating start of transmission READ: does not transmit any synchronization over the serial line, which could be used to remove out of phase problems Separate start and stop bits are sent to synchronize start and end of the transmission and to catch possible timing errors or trying to catch them as many have found out on the exercises by setting wrong baudrate #7/62

8 USART synchronous mode

9 USART synchronous mode Usage is pretty much the same to asynchronous mode Example shows a write operation where PIC is the master #9/62

10 USART synchronous mode (2) Single Receive Enable (SREN) initiates the transfer One may use also Continuous Receive (CREN) External device drives DT on each clk pulse #10/62

11 USART synchronous mode (3) There is no pre-defined baud rate because separate clk signal is used Just ensure that receiver is fast enough Any lower baud rate may be opted f Baud rate R baud = (11.1) (4 * (SPBRG+1)) where f is the clk frequency clk divisor is constant 4 unlike in asynch. mode SPBRG is counter s period (num of cycles) #11/62

12 SPI and I2C

13 SPI and I2C Possibly two most common serial buses SPI Serial Peripheral Interface requires at least 3 wires and usually 4 technically duplex but most transfers are half-duplex higher top speed than I2C I2C Inter IC two wires regardless of the number of communicating devices half-duplex lower top speed than SPI Non-licensed I2C implementations reffered often as two-wire or I2C compliant #13/62

14 SPI and I2C (2) Both are synchronous serial interface standards Clock provided as separate signal Both are rather common in industry Master Synchronous Serial Port (MSSP) subsystem implements these protocols in PIC18 They share IO pins One can use also GPIO pins and implement the protocol with SW Subsystem Protocol Classification Pins USART N/A Half-duplex RC6/TX/CK (clock), RC7/DT (data) MSSP SPI Duplex RC3/SCK/SCL (clock), RC4/SDI/SDA (data in), RC5/SDO (data out) MSSP I2C Half-Duplex RC3/SCK/SCL (clock), RC4/SDI/SDA (data) #14/62

15 SPI

16 SPI - Serial peripheral interface Originally developed by Motorola Frequencies are commonly in the range of 1-70 MHz Very simple protocol Data is sent MSb first (unlike in USART) Sometimes called a "four wire" serial bus Clock, data in both directions, and slave select Note that there is one select signal for each slave Num of signals grows with larger systems Actually it is 3+n wire bus, where n 1 Three other signals are shared by all slaves SPI can mean also System Packet Interface, family of interfaces from the Optical Internetworking Forum, but that does not interest us #16/62

17 Full-duplex in SPI Special full-duplex operation: Master and slave exchange data Data is shifted out from SDO while shifting other data in from SDI 1. Write the data to send here first 2. Read slave s data from here at the end ctrl bits will be explained later interrupt flag #17/62

18 SPI signals The SPI bus specifies four logic IO signals 1. SCK Serial Clock (output from master) 2. SDI Serial Data In 3. SDO Serial Data Out 4+. CS, CS# Chip Select (active low) Alternative naming conventions are also used: SCLK, CLK Serial clk MOSI/SIMO, DO Master Output-Slave Input, data out MISO/SOMI, DI Master Input, Slave Output, data in SS, STE Slave Select, Slave Transmit Enable #18/62

19 Connecting slaves Slave select is driven low prior to transfer and must remain low for the whole duration 1. Independent slaves: one-hot SS, tri-state MISO, more common 2. Co-operative slaves: chained together, single SS, rare 1. Typical SPI bus: master and three independent slaves 2. Daisy-chained SPI bus: master and cooperative slaves #19/62

20 SPI configuration possibilities 1. CKE bit = clock edge selection 2. CKP bit = clock polarity selection 3. SMP bit = input sample point selection 4. SSPM = synchr. serial port mode controls the SCK freq. TX on idle to active TX on active to idle Sample at middle Sample at end idle = low idle = high idle = low idle = high #20/62 CPU can read the from SSPBUF after interrupt flag is set

21 SPI usage Simple protocol No addressing nor commands defined in the standard Low overhead Handled by SPI HW Control data is device-specific Dig. potentiometer, serial EEPROM, AD- and DA-converter How many bits for commands, address, data etc. Basically, this means that one of the communicating devices is programmable It can adapt to the protocol assumed by the other SW running on PIC takes care of sending correct data words #21/62

22 SPI usage: MCP41xxx digital potentiometer Potentiometer provides variable resistance Controlled via parallel or serial interface Analog potentiometer is wiped mechanically Three terminals full resistance between PA0 and PB0 variable resistance from wiper, PW0-PA0 and PW0-PB0 #22/62 PIC is the master

23 SPI usage: MCP41xxx (2) Output s theoretical value range [1, 1/256] * Vdd Each transaction has exactly 2 bytes 1. Command does not need all 8 bits 2. Data value of variable resistance R Note that bits are sent MSb first #23/ xx01xxx xx10xxx1

24 SPI usage 2: serial EEPROM Another example shows how to use an external EEPROM for non-volatile storage Slaves EEPROM and potentiometer are independent separate slave select for each #24/62 Mem s HOLD and WP# inputs are deactivated by pull-up in the example RB4 or RB7 used as slave select pins 8

25 SPI usage: serial EEPROM (2) Mem transaction has 1 command byte 2 address bytes, uppermost bits are ignored 1-32 data bytes, mem updates internal address automatically EEPROM samples data on rising edge and writes output at falling edge (CKP=0, CKE=1, SMP=1) #25/62 1. read operation To continue reading or writing from/to sequential 2. write operation addresses provide more clock pulses

26 SPI usage: serial EEPROM (3) Mem is internally divided into 32-byte pages A multibyte write operation will wrap if addresses grow beyond page border All data goes into the same page Example of wrapping in fig b next 32-byte page string does not go here #26/62

27 SPI usage: serial EEPROM (4) Q: How long does it take to write one page of data to EEPROM? PIC s frequency f= 40 MHz SPI control SW overhead 20 instr/byte EEPROM s f max = 3 5V A: SPI frequency f SCK = 2.5 MHz < 3 MHz comes from 40MHz / 16 -> Closest frequency to 3 MHz but not over bit time t bit = 1/2.5 MHz = 0.4 us t instr = 4 cycles * (1/40 MHz) = 0.1 us #bytes = = 35 bytes (cmd,addr,data) = 35 bytes * 8 bit/byte = 280 bits t page write = (35 bytes * 20 instr/byte * t instr ) + (280 bits * t bit ) = (35 * 20 * 0.1us) + (280*0.4 us) = 182 us #27/62

28 Inter IC bus, aka I2C aka I 2 C (or two-wire)

29 Inter Integrated Circuit (I2C) bus Developed by Philips Semiconductor in the early 1980s Widely used in industry Term bus differs from the its usage with SPI In SPI, bus denotes only a group of wires the most basic definition of a bus With I2C, bus refers to a shared bus topology One master and multiple slaves Slaves decode the address on the bus to see if they are being accessed Only one slave responds #29/62

30 Addressing in bus Transmitter (master) first addresses one of the receivers (slaves) All slaves monitor the bus traffic to see if there is a new address Many buses allow broadcast operation where the same data go to all reveivers #30/62

31 I2C signals Two-level addressing: 1. select the device 2. select the location/register inside the device Device address is always the first byte Actually, the first 7 bits (max 128 devices on same bus) The 8th bit denotes the direction read/write Typically, address can be selected with HW (soldering resistors, or connecting pins etc.) Only 7 bits for addresses can cause trouble, especially since some devices actually allow less possible different addresses (e.g. 3bits or 8 different addresses, even devices with one possible address do exist..) Usage of address removes the separate slave select signals Number of wires does not depend on #slaves! Great. As long as slaves have unique addresses, otherwise parallel buses required #31/62

32 I2C signals (2) Just two wires, both with open-drain (i.e. open collector) drivers 1. clock SCL 2. data SDA Bidirectional, multimaster operation possible Half-duplex communication Example I 2 C devices and addressing #32/62

33 I2C timing: start When both SDA and SCL are high, bus is idle SDA s hi-to-low transition is the start condition Multiple bytes can be sent in one transaction Each byte is sent MSb first Address + R/W bit is the first byte #33/62

34 I2C timing: acknowledge The 9th bit is always a mandatory acknowledge bit Transmitter does not drive the bus Receiver tells the success of byte transfer 0 = ok = acknowledge = ACK 1 = not ok = negative ack = NACK If receiver does not respond, pull-up R gives automatic NACK Note that in read operation, the master gives ACK/NACK #34/62

35 I2C timing: data + stop SDA is allowed to change only when SCL==0 Preferably, equally far away from either SCL edge After ack bit, the slave can hold SCL line low Master has to wait unitl SCL is released This allows flow control Stop condition is SDA lo-to-hi and SCL=1 #35/62

36 Controlling I2C in PIC SFR SSPCON provides control and status bits for the I2C, e.g. enable, master/slave, send start/stop, send ack/nack received ack/nack SSPSTAT shows if tx is in progress or if rx buffer is full SSPIF (=PIR[3]) denotes that transfer of byte + ack completed (interrupt flag) SFR TRISC allows settings the IO pins to open-drain RC3/SCK/SCL RC3/SDI/SDA #36/62

37 Possible actions in I2C master mode Perform start Perform repeated start aborts currents tx Perform stop Perform ACK/NACK Transmit data Receive data #37/62

38 C code examples for I2C This shows the fucntion that was last called. If watchdog expires, we know post-mortem in which function that happened. This is a persistent variable - it is not overwritten by init function. Watchdog expires if do-while seems to take forever #38/62 Master mode: R/W# = low -> Transmit is not in progress SEN = low -> Start condition Idle RSEN = low -> Repeated Start condition Idle PEN = low -> Stop condition Idle RCEN = low -> Receive Idle ACKEN = low -> Acknowledge sequence Idle

39 C code examples for I2C (2) MSSP HW will clear SEN when start condition has been completed #39/62

40 C code examples for I2C (3) #40/62 In real code, always use braces with ifelse!

41 I2C transaction examples i.e. WR op SDA i.e. RD op SDA #41/62

42 Example usage of I2C 24LC515 is 512 Kbit serial EEPROM internally 64K x 8 bits hence 16-bit addresses 0x0 0xffff 16-bit address space split into two 32K blocks Address bits A0 and A1 allow 4 memory banks to exist in the same I2C bus #42/62

43 I2C address of EEPROM Upper addr bits are fixed B selects the upper/lower block A1 and A0 select one out of 4 EEPROMs LSb select Rd/Wr Once the EEPROM bank is selected like this, PIC provides the memory address #43/62

44 I2C EEPROM operations Write 1 byte I2C address selects the device, hi/lo block inside that, and the R/W bit 2 bytes provide the 15-bit memory address 1-64 bytes of data can be written in one transaction (wrapping occurs when crossing 64- byte boundary) #44/62

45 I2C EEPROM operations (2) Worst-case completion of write is 5 ms End-of-write condition can be polled by sending new write command More efficient than always waiting 5ms NACK means that there is a write in progress New operation cannot be started Once ACK is returned, the previous operations has completed #45/62

46 I2C EEPROM operations (3) Sequential read returns the contents of multiple consecutive memory locations Address given only once May read upto 32Kbytes PIC ends the operation with NACK #46/62

47 I2C arbitration Previous examples assumed that PIC is the only master However, I2C supports multi-master operation Note that only one master owns the bus at a time Arbitration decides which is the current master Many policies in buses: fixed priority, rotating priority (round-robin), TDMA, lottery, combination, collision detection #47/62

48 Bus arbitration

49 Basic arbitration schemes Centralized All master request the bus from a centralized arbiter Arbiter grants one Num of req/grant lines increases with system size Distributed No centralized arbiter or point-to-point signals a) TDM time division multiplexing b) Collision detection #49/62

50 Arbitration with collision detection Distributed arbitration is favored due to fewer signals Better scalability, easier layout TDM requires synchronization, all master must be aware of correct time when to send Collision detection is used in I2C, CAN and Ethernet 1. Master waits that bus is idle 2. It starts sending 3. It monitors if incoming data is the same as it sent itself a) If it is, continue b) If not, back-off and retry a bit later #50/62

51 Arbitration with collision detection When collision occurs, master waits random time berore retrying If another collision occurs, wait time is increseased Collisions cause unnecessary waits and hence lower the performance However, in I2C open-drain IO allows one master to continue despite the collision Bit 0 overrides the weak pull-up It does not notice any problem, no performance loss there #51/62

52 CAN

53 Controller area network (CAN) Half-duplex, multi-master, serial two-wire bus Arbitration is priorized, a message with a lower ID (more zeroes) will get the bus in a competitive situation lower ID (MSb first) will draw line down and wins (higher ID sender realizes that it cannot draw line up) Used for example in cars or in home-automation Distances of few meters, lots of noise, reliability requirements, 10 Kb/s 1Mb/s data rates Differential signaling Better noise immunity, especially for common-mode noise Each transaction starts with 11-bit identifier Must be unique, lower ID means higher priority Any node can initiate transfers Arbitration with collision detection similarly to I2C All can receive and they filter the incoming data according to identifier Devices must agree on baud rate #53/62

54 CAN (2) External transceiver used with PIC Differential signaling requires no common ground potential If fig, noise Vn sums to both lines but does not affect the voltage difference! All bits are clean #54/62

55 CAN (3) All data frames have error detection code with CRC (cyclic redundancy check) Bit stuffing ensures a signal edge at least once in 6 cycles Allows the PLL to generate reference clock at the receivers side #55/62 After 5 cycles with same signal level, additional stuff bit forces edge Removed by rx (it counts..) RX sees 5 ones and then expects 0, if after 0 is 1 == 6 ones, if after 0 is 0 == 5 ones, two zeroes

56 USB

57 Universal Serial Bus (USB) High-speed serial protocol 1.5 Mb/s,12 Mb/s, 480 Mb/s Replacing RS-232 in PCs Single master host- usually PC Multiple functions, such keyboards, mice, printers, speakers... Hubs grow the physical topology but logically it is a star #57/62

58 USB (2) Differential data signaling (two wires) and Vdd and ground Functions may be powered via USB, no need for external power source Hot swap - devices can added and removed while USB is operational Host provides address (bus enumeration) for each function D+ D- D- D+ Votlage levels for full- and low-bandwidth modes #58/62

59 USB (3) Each packet starts with a synchronization sequence High density of signal transitions to synchronize the receiver, b (or as NRZI line goes ) Data sent using Non Return to Zero Invert (NRZI) data encoding with bit stuffing Bit unfortunate name... (not inverse of NRZ encoding!) Changes signal level when 0 is transmitted whereas 1 keeps the level Maximum of 6 consecutive 1 #59/62 Each transmitted 0 bit causes level change

60 USB (4) Packet-based communication token, handshake, data packets packets protected with CRC Four transaction types bulk, control, interrupt, isochronouss Quite complicated protocol compared to SPI or I2C Thus, not very common in small MCUs, typically external UART-to-USB chips are used #60/62

61 Conclusions Synchronous serial protocols are more common than acynchronous Multi-master buses need arbitration Address decoding at slaves keeps the number of wires fixed Be careful which is transmitted first: MSb or LSb when data is allowed to change whether pos or neg- clk edge is used for sampling with signals voltage levels with multiple drivers for the same signal #61/62

62 General-purpose IO

63 General-purpose IO The simplest type of I/O via the PIC µc external pins are parallel I/O (PIO) ports PIC can have multiple PIO ports named PORTA, PORTB, PORTC etc. generically referred to as PORTx. number of PIO pins depends on the particular PIC µc and package Each pin on these ports can either be an input or output direction is controlled by the corresponding bit in the TRISx registers ( 1 = input, 0 = output). The LATx register holds the last value written to PORTx #63/62

64 IO port structure Accessed via microcontroller s internal data bus Three-state buffers allows bi-directional operation Controlled with TRISx reg Written output data is latched Read operation returns either a) latched value (reading LATx) b) value fo the IO pin (reading PORTx) #64/62

65 #65/62!= )

66 #66/62 While (_RB3);

67 #67/62

68 #68/62

69 #69/62

70 #70/62

71 External memory interface GPIO could be used for interfacing external memories Addr, data and ctrl signals are written separately to corresponding LATx reg Very slow #71/62

72 External memory interface (2) Some PIC devices support external memories directly Ports D, E, H form 20-bit multiplexed address/data bus Port J implements control signals Enabled and controlled with SFR MEMCON Supports both 8-bit and 16-bit data #72/62