Hardware Laboratory Configuration

Transcription

1 Field-programmable Port Extender () January 2002 Workshop Hardware Laboratory Configuration John Lockwood, Assistant Professor Washington University Department of Computer Science Applied Research Lab 1BrookingsDrive Saint Louis, MO Copyright Supported by: NSF ANI and Xilinx Corp. Network Platform 1 Laboratory Topology for this Workshop Network Platform 2

2 Laboratory Topology for this Workshop 2 Switch Controller MMX 2 Video Systems MMX 1 Video Systems 1 Switch Controller 1 Gigabit Switch 2 Switch CAD1 Workstation CAD2 Workstation Network Platform 3 Switch Kit Topology for this Workshop Network Platform 4

3 Switch Kit Topology for this Workshop OC3 Links to MMX Video Systems [port 0] Module w/xcv2000e [port 2] Gigabit Link to Controller [port 3] Module w/xcv2000e [port 7] Gigabit Fiber Loopback [port 6] Module w/xcv1000e [port 4] Module w/xcv2000e [port 5] Network Platform 5 Simplified Switch Port Configuration MMX Video Send Cell Dump Cell Fiber Loopback Network Platform 6

4 Controlling the Networked Configurable Hardware Administrator for Reconfiguration and Governing via End-system Basic Send 0.0 Telnet Basic Send CGI WEB Access 7.1 Provides Communication with For Users on the Internet Networked applications Supports Loadable Plugins NID RAD OC-3 Link (upto32vcis) NID RAD Network Platform 7 Allows communication to hardware over the Internet using the Web, TCP/IP Sockets, and/or Telnet. Multiple TCP Sockets for Remote Applications Issues and receives control cells to and from the Provides transport mechanism with retransmission Allows for multiple users or software applications to connect to simultaneously {0-7}.{0/1} Control cells Sent to and from (RAD & NID) Network Platform 8

5 HDR HEC OpCode PL1 PL2 PL3 PL4 PL5 PL6 PL7 PL8 PL9 PL10 PL11 Control Cell Format for 32/36 bit RAD SRAM Memory Operations V V V GFC / VPI D D D HEC OpCode R R R F F F Sequence # VCI ModuleID V- Valid Command: 1 = Valid command, 0 = Invalid, EOC D - Device: 1 = Device 1, 0 = Device 0 R - Read or Write: 1 = Read, 0 = Write F - 32 or 36 bit: 1 = 36 bit, 0 = 32 bit PAD ADDR(18:0) WORD 0 (31:0) WORD 1 (31:0) ADDR(18:0) WORD 0 (31:0) ADDR(18:0) WORD 0 WORD 1 WORD N CM DATA N/A 1 0 X W0(35:32) W1(35:32) W0(35:32) C(7:5) PTI N/A N/A CRC VPI = 0x000, VCI = 0x0023 (35) RAD Control Cell OpCode = 0x14 SRAM Memory Operation OpCode = 0x15 SRAM Memory Operation Response ModuleID = 0x00 RAD Control Cell Processor 36 Bit format 2 Address 36 Bit format 1 Address 32 Bit format 'N' Address Switch Setup WUGS Switch fpx2.arl.wustl.edu Port 4 Port 3 LC Port 2 Port 1 empty Port 5 Port 6 Loopback Port 7 Port 0 MMX Address Mappings Switch Ports VC from fpx2.arl to switch port 3 VC from switch port 3 to fpx2.arl VCforIPoverATM (using UDPtest) IP address to each port Network Platform 9 Hardware / Software Interface {0-7}.{0/1} Network Platform 10

6 Website ÿ ÿ ÿ Network Platform 11 Create Cells Web interface to create cells Custom Data Payloads Hello Data Hello Extended Sample Programs CHKHello Rot13 RLE RLD Network Platform 12

7 Generate Cell Creates Content of Raw Cells Padded Cells AAL5 Frames IP Packets (Ver 4 & 6) UDP Packets Control Cells Example Generate KCPSM Data packet 0x = data Payload = Hello Network Platform 13 Send Cell Sends Cell(s) to module VCI specified by pull-down menu VCI 145 (90h) switched to VCI 50 (32h) on Network Platform 14

8 Receive Response Waits for data to be received from Displays Hex and ASCII Values of received cells Notice that Hello transformed to Uryyb Network Platform 15 Acknowledgements Several Individuals have contributed to this work: Washington University Jon Turner Sarang Dharmapurikar Todd Sproull David Taylor Florian Braun Henry Fu James Moscola DaveLim Edson Horta Xilinx Dave Parlour Network Platform 16