Lecture 3: Computation Modeling

Transcription

1 COEN 691B: Embedded System Design Lecture 3: Computation Modeling Samar Abdi (slides courtesy of A. Gerstlauer, D. Gajski and R. Doemer) Assistant Professor Electrical and Computer Engineering Concordia University

2 Communication System Design Flow Abstraction based on level of detail & granularity Computation and communication System design flow Path from model A to model F Cycletimed D F Approximatetimed C E A. System specification model B. Timed functional model C. Transaction-level model (TLM) D. Bus cycle-accurate model (BCAM) E. Computation cycle-accurate model (CCAM) F. Cycle-accurate model (CAM) Untimed A Untimed B Approximatetimed Cycletimed Computation Source: L. Cai, D. Gajski. Transaction level modeling: An overview, ISSS 2003 Design methodology and modeling flow Set of models and transformations between models COEN 691B: Embedded System Design 2

3 Lecture 3: Outline Profiling Timing estimation using processor model RTOS modeling Hardware abstraction layer modeling COEN 691B: Embedded System Design 3

4 Profiling Input specification MoC Hierarchy Computation & communication B B1 c v B2 Multi-dimensional analysis Multi-entities Behavior, channel, port, variable Multi-metrics Operation, traffic, storage Static, dynamic Multi-levels Application, transaction, busfunctional Profiling Application Instrumentation Instr. Appl Simulation Counters Static Analysis Profiled App. COEN 691B: Embedded System Design 4

5 Profiling Instrumentation-based profiling B b : The execution counts of basic block b Enumerate execution paths C b,i,d : No. of computed characteristics for item type i and data type d in the block b Data type i: float, int,.. Item type d: metric-dependent int b,c; if( a = 0){ b++; } else{ b++; c++; } B 1 = 1 C 1,++,int = 1 B 3 = 3 C 3,++,int = 2 Specification metrics R i,d = b C b,i,d B R b ++,int= i [ B i * C i,++,int ] R = i d R i,d = 1 * * 2 = 7 Source: L. Cai, A. Gerstlauer, D. Gajski, Retargetable Profiling for Rapid, Early System-Level Design Space Exploration, DAC, COEN 691B: Embedded System Design 5

6 Retargeting Target machine model W i,d : weights of components which the entity mapped to Manual Simulation Complex cost function/ algorithm R(B1) ++,int = 7 B B1 c v B2 Implementation estimates E = i d (R i,d * W i,d ) Time complexity: O(n) W(PE1) ++,int = 1 E(B1,PE1) ++,int = 7 x 1 = 7 PE1 Mem PE2 Source: L. Cai, A. Gerstlauer, D. Gajski, Retargetable Profiling for Rapid, Early System-Level Design Space Exploration, DAC, COEN 691B: Embedded System Design 6

7 Vocoder Example Profiling Floating point not required Dedicated hardware multipliers HW acceleration Computational complexity of top-level Vocoder behaviors: LP_Analysis Open_Loop Closed_Loop Codebook Update MOp 337.1MOp MOp MOp 43.6 MOp Codebook operation mix: (x, int) (+, int) (-, int) (/,int) (others,int) 46.2% 33.5% 9.1% 7.1% 4.1% COEN 691B: Embedded System Design 7

8 Transcoding delay 35 ms Vocoder Design Space Exploration 30 ms SW (20.0, ms) 25 ms 20 ms Timing constraint 15 ms 10 ms Mapping of 8 top-level encoder behaviors onto ColdFire + DSP + HW 85:04h for 6561 alternatives (1.7s simulation + 3s refinement each) 100% fidelity HW (144.1, ms) Cost COEN 691B: Embedded System Design 8

9 General Processor Micro-Architecture Basic computation component is a processor (PE) Programmable, general-purpose software processor (CPU) Programmable special-purpose processor (e.g. DSPs) Application-specific instruction set processor (ASIP) Custom hardware processor PE Bus interface CLK t Controller Status lines Datapath Control signals Functionality and timing COEN 691B: Embedded System Design 9

10 Processor Models (1) Structural RTL models CPU Load/store unit CLK HW Bus interface CLK Controller Datapath Controller Datapath PC Fetch Memory (data & progr.) Register file Next state logic Register file Memory IR State Decode ALU Output logic FU1 Software processor Sub-cycle accurate Hardware processor COEN 691B: Embedded System Design 10

11 Binary Processor Models (2) Behavioral RTL/IS models App. RTOS HAL CPU HW ISS CPU_CLK HW_CLK Instruction set simulation (ISS) FSMD Cycle accurate COEN 691B: Embedded System Design 11

12 CPU Computation Modeling Process B1() { waitfor(15000); waitfor(25000); }; Bus HAL P1 OS Drv P2 ISR Interrupts Application modeling Native process execution (C code) Back-annotated execution timing Processor modeling Operating system Real-time multi-tasking (RTOS model) Bus drivers (C code) Hardware abstraction layer (HAL) Interrupt handlers Media accesses Processor hardware Bus interfaces (I/O state machines) Interrupt suspension and timing COEN 691B: Embedded System Design 12

13 Application Layer High-level, abstract programming model Hierarchical process graph ANSI C leaf processes Parallel-serial composition Abstract, typed inter-process communication Channels Shared variables Timed simulation of application functionality Back-annotate timing Estimation or measurement (trace, ISS) Function or basic block level granularity Execute natively on simulation host Discrete event simulator Fast, native compiled simulation CPU B2 B1... void f() { waitfor(5);... }... C1 C2 0 p1.c B3 Logical time 5 10 COEN 691B: Embedded System Design 13

14 C1 Timing Estimation Input: Application Model P1 P2 v1 C2 P3 P4 Application model consists of Processes for computation (eg. P1, P2, P3, P4) Channels for communication (eg. C1 between P1 and P3) Variables for storage (eg. v1) COEN 691B: Embedded System Design 14 14

15 C1 Application Model Objects Processes Symbolic representation of computation Contain C/C++ code imported from reference P1 P2 v1 Process ports Symbolic representation of communication services required by processes Provide object orientation by allowing processes to connect to different channels Channels Symbolic representation of inter-process communication Implement communication services such as blocking, non-blocking, handshake, FIFO etc. Encapsulation for communication functions Variables Symbolic representation of data storage P3 C2 P4 COEN 691B: Embedded System Design 15 15

16 Arbiter TX Timing Estimation Input: Platform Architecture CPU1 Mem OS1 Bus1 Bus2 OS2 HW CPU2 Platform consists of Hardware: PEs (eg. CPU1, HW), Buses (eg. Bus1), Memories (eg. Mem), Interfaces (eg. Transducer) Software: Operating systems (eg. OS1) on SW PEs COEN 691B: Embedded System Design 16 16

17 Arbiter TX Platform Objects Processing element (PE) Symbolic representation of computation resources Different types such as SW processors, HW IPs etc. CPU1 OS1 Mem Bus Symbolic representation of communication media Types include shared, point-to-point, link, crossbar etc. Bus1 Bus2 OS2 HW CPU2 Memory Symbolic representation of physical storage May contain shared variables or SW program/data Transducer For protocol conversion and store-forward routing Necessary for PEs with different bus protocols Operating system (OS) Software platform for individual PEs Needed for scheduling multiple processes on a PE COEN 691B: Embedded System Design 17 17

18 Arbiter C1 TX Timing Estimation Input: Mapping CPU1 P1 P2 Mem v1 Processes PEs Channels Routes Variables Memories OS C2 Bus1 Bus2 P3 P4 OS HW IP CPU2 COEN 691B: Embedded System Design 18 18

19 Mapping Rules Processes to PEs Each process in the application must be mapped to a PE Multiple processes may be mapped to SW PE with OS support Example: P1, P2 CPU1 Channels to Routes All channels between processes mapped to different PEs are mapped to routes in the platform Route consists of bus segments and interfaces Channel on each bus segment is assigned a unique address Variables to Memories Variables accessed by processes mapped to different PEs are mapped to shared memories All variables are assigned an address range depending on size COEN 691B: Embedded System Design 19 19

20 Computation Timing Estimation BB1 PC CMem CW const RF al Mul bl BB1 BB2 N If Y BB3 OR offset AG Sum P status AR ALU Mem Add DR Processor Model wait(t1) N If BB2 Y BB3 wait(t2) wait(t3) N If Y Timing Estimation N If Y Process CDFG Timed Process Stochastic memory delay model DFG scheduling to compute basic block delay [DATE 08] RTOS model added for PEs with multiple processes COEN 691B: Embedded System Design 20

21 Stochastic Memory Delay Model Assumption Cache and branch prediction hit rate available in data model Delay Estimation Operation access overhead = N op * ((1.0 HR i ) * (CD + L mem )) Data access overhead = N ld * ((1.0 HR d ) * (CD + L mem )) Branch prediction miss penalty = MP rate * Penalty 1: a = $i - 1 2: t1 = a + 2 3: t2 = $n * $m 4: t3 = t1 - t2 5: load b 6: t4 = b / 10 7: jmp LLVM Bytecode Cache D-Mapped 16K Icache: % Dcache: % Delay : 1 Me mory Delay: 8 BrPredict Policy: Taken Penalty : % Memory/Branch Model Mem./Br. Delay Calcutation Mem. Overhead= 4.1 Branch Delay= 1.2 COEN 691B: Embedded System Design 21

22 Processor Timing Estimation Assumptions In-order, single issue processor Optimistic during scheduling (100% cache hit) Operations Add IF ID EX: int-alu IntAdd Sub IF ID EX: int-alu IntSub Datapath Int-ALU Qty: 1 IntAdd IntSub Lat: 1 Lat: 1 Total BB delay= Op.+Mem.+Br. = 47.3 cycles 1: a = $i - 1 2: t1 = a + 2 3: t2 = $n * $m 4: t3 = t1 - t2 5: load b 6: t4 = b / 10 7: jmp 8: wait 47*CT LLVM Bytecode Processor Data Model Pipeline Scheduling Operation delay= 42 COEN 691B: Embedded System Design 22

23 CPU1 Output: SystemC Timed Model P1 OS P2 Mem TX Bus1 Bus2 P3 HW IP Model Generation Technique Application code sc_thread Processing element sc_module OS Model sc_module Bus sc_channel Memory Array inside sc_module Interface FIFO channel+sc_process CPU2 OS P4 COEN 691B: Embedded System Design 23 23

24 Operating System Layer Scheduling Group processes into tasks Static scheduling Schedule tasks Dynamic scheduling, multitasking Preemption, interrupt handling Task communication (IPC) Application Task Scheduler SLDL P1 P2 Scheduling refinement Flatten hierarchy Reorder behaviors OS refinement Insert OS model Task refinement IPC refinement Task P2 P1 C1 C2 OS Model Task P3 App OS COEN 691B: Embedded System Design 24

25 OS Modeling High-level RTOS abstraction Application Application T1 Application T2 Channels T1 T2 Channels RTOS Model RTOS Comm. & Sync. API Instruction Set Simulator SLDL SLDL SLDL Specification is fast but inaccurate Native execution, concurrency model Traditional ISS-based validation infeasible Accurate but slow (esp. in multi-processor context), requires full binary Model of operating system High accuracy but small overhead at early stages Focus on key effects, abstract unnecessary implementation details Model all concepts: Multi-tasking, scheduling, preemption, interrupts, IPC Specification TLM Implementation Source: A. Gerstlauer, H. Yu, D. Gajski. "RTOS Modeling for System-Level Design," DATE03. COEN 691B: Embedded System Design 25

26 P2 waitfor() c1.send() waitfor() P1 Simulated Dynamic Behavior waitfor() C1 P3 waitfor() c1.recv() waitfor() t0 t1 t2 t3 t0 t1 t2 Task P2 time_wait( ) P1 time_wait( ) Task P3 time_wait( ) c1.recv() bus.recv() t4 t3 c1.send() C1 time_wait( ) waitfor() ISR S1 Bus waitfor() t5 t6 t7 t8 t4 t5 t6 t7 time_wait( ) ISR time_wait( ) S1 Bus bus.recv() time_wait( ) Inaccuracy due to timing granularity Unscheduled t8 Logical time Scheduled COEN 691B: Embedded System Design 26

27 RTOS Model Implementation RTOS model OS, task, event management Descriptors & queues Scheduling Select and dispatch task based on algorithm Block all but active task on SystemC level Preemption Allow rescheduling at simulation time increases Event handling Remove task temporarily from OS while waiting for SystemC event RTOS model library RTOS models for different scheduling strategies Round robin, priority based Parametrizable Task parameters (priorities) channel OS implements OSAPI { Task current = 0; os_queue rdyq; void dispatch(void) { current = schedule(); notify(current.event); } void yield() { task = current; dispatch(); wait(task.event); } void time_wait(time t) { waitfor(t); yield(); } 20 Task pre_wait(void) { Task t = rdyq.get(current); dispatch(); return t; } void post_wait(task t) { 25 rdyq.put(t); wait(t.event); } }; COEN 691B: Embedded System Design 27

28 RTOS Model Interface Canonical, target-independent API 1 5 interface OSAPI { void init(); void start(int sched_alg); void interrupt_return(); OS management }; Task task_create(char *name, int type, sim_time period); void task_terminate(); void task_sleep(); void task_activate(task t); void task_endcycle(); void task_kill(task t); Task par_start(); void par_end(task t); Task pre_wait(); void post_wait(task t); void time_wait(sim_time nsec); Task management Event handling Delay modeling COEN 691B: Embedded System Design 28 Back

29 Task Refinement Convert processes into tasks Task initialization Register task with OS model Task activation Wait for task start trigger from OS Replace delay model Trigger rescheduling in OS Preemption points Communication and synchronization Wrap around SLDL event handling process task_b2(osapi os) { Task h; void task_b2(void) { h = os.task_create( B2, APERIODIC, 0); } void main(void) { os.task_activate(h); }... /* model execution delay */ os.time_wait(block1_delay) waitfor(block1_delay); ;... send(); /* os.time_wait(block2_delay) model execution delay */ waitfor(block2_delay); ;... os.task_terminate(h) ; void t send() = os.pre_wait(); { 25 wait(ack); os.post_wait(t); } }; COEN 691B: Embedded System Design 29 Back

30 Operating System Layer OS model On top of standard SystemC Wrap around SystemC primitives, replace event handling Block all but active task Select and dispatch tasks Target-independent, canonical API Task management Channel communication Timing and all events Application OS Model SLDL Task P2 Task P2 P1 C1 C2 OS Model Task P3 Task P3 App OS COEN 691B: Embedded System Design 30

31 Hardware Abstraction Layer (HAL) External communication Software Drivers Presentation, session, network communication layers Synchronization (interrupts) Hardware/software boundary Low-level HW access Bus drivers and interrupt handlers Canonical HW/SW interface External interface Bus transactions (TLM) Interrupt trigger Driver App. Task P2 P1 C1 C2 OS Model UsrInt1 INTA INTB INTC sample.send(v1); void send( ) { intr.receive(); bus.masterwrite(0xa000, &tmp, len); } Task P3 App UsrInt2 INTD OS Driver Driver HAL Bus TLM COEN 691B: Embedded System Design 31

32 Hardware Layer HAL: IntA Hardware: IntA T B2 T B2 T B1 Processor TLM HW interrupt handling Interrupt logic Suspend user code Interrupt scheduling Priority, nesting Peripherals Interrupt controller Timers TLM bus model Bus transactions t 1 t 2 Task P2 t 3 P1 C1 C2 time OS Model UsrInt1 IntA IntB IntC Task P3 T B1 App UsrInt2 IntD OS t 1 t 2 Driver Driver HAL Access HW Int HW t 3 time Bus TLM INTA INTB INTC INTD COEN 691B: Embedded System Design 32

33 Hardware Layer Bus-functional model (BFM) Pin-accurate processor model Timing-accurate bus and interrupt protocols Bus model Pin- and cycle-accurate Driving and sampling of bus wires REQ GRANT CNTRL ADDR WDATA READY Task P2 P1 C1 C2 OS Model UsrInt1 IntA IntB IntC Task P3 nonseq. word 0xA App UsrInt2 IntD OS 0x2F00 0x Driver Driver HAL Access HW Int HW Prot INTA INTB INTC INTD COEN 691B: Embedded System Design 33

34 Processor layers Application Native, hostcompiled C Annotated timing OS OS model Middleware, drivers HAL Firmware Processor hardware Bus interfaces Interrupts handling & suspension Processor Model Task P2 IntA inta P1 C1 C2 OS Model UsrIntr1 Task P3 App UsrIntr2 Features Target approx. computation timing Task mapping, dynamic scheduling Task communication, synchronization Interrupt handlers, low level SW drivers HW interrupt handling, int. scheduling Cycle accurate communication Cycle accurate computation OS IntB intb IntC intc IntD intd Appl. Source: G. Schirner, A. Gerstlauer, R. Doemer. Fast and Accurate Processor Models for Efficient MPSoC Design," TODAES, HAL COEN 691B: Embedded System Design 34 Driver Driver Access HW Int. OS HW HAL INTA INTB INTC INTD HW-TLM Bus TLM HW-BFM BFM - ISS