CoFluent Design FPGA. SoC FPGA. Embedded. Systems. HW/SW

Transcription

1 CoFluent Design Embedded HW/SW Systems SW SoC FPGA FPGA Integration Systems & Verification of GreenSocs Models in a CoFluent Testbench jerome.lemaitre@cofluentdesign.com NASCUG IX, June 2008

2 Outline Motivation Abstraction levels of GreenSocs & CoFluent models Integration objective and challenge Combining ESL and detailed SystemC IP models Integration approach: Graphical representation of the ESL testbench Conversion of ESL messages to IP-specific transactions Automatic verification of the detailed (IP) model Example of verification based on a use case in the ESL testbench Use of generic parameters for exploration purposes Linking ESL parameters with detailed model properties PV/PVT transactions, memory access time Optimization of the verification time in the ESL testbench Conclusion 6/16/08 Copyright CoFluent Design 2

3 Motivation This integration work was part of a project to generate testbenches and use cases around GreenSocs models for a leader in the semiconductor industry 6/16/08 Copyright CoFluent Design 3

4 Abstraction levels of GreenSocs and CoFluent models CoFluent models: Behavior: functions and inter-function relations Graphics, user C code and timing properties (budgets) Automatic SystemC generation: Message level (token-based) ~ TL3 Fast simulation for architecture exploration GreenSocs models: Platform: composition of library (IP) components Masters, slaves, bus, router, scheduler Address-based, memory maps SystemC: PV/PVT transactions ~ TL2/TL1 Detailed simulation, close to implementation 6/16/08 Copyright CoFluent Design 4

5 Integration objective & challenge Objective: Integration and validation of a detailed IP-based platform model in a system-level model (testbench) Automatic validation of the detailed model More accurate architecture exploration Challenge Fast simulation Automatic verification of the detailed platform TL3 Testbench? TL2/ TL1 Combining different levels of abstraction: Conversion from TL3 to TL2/TL1 specific transactions Verification and exploration without re-compiling: Relation between ESL and detailed parameters 6/16/08 Copyright CoFluent Design 5

6 Integration approach ESL testbench TL3 TL2/TL1 Use case: Write/read to/from each memory and verify received data Testbench parameters: PV/PVT protocol, memory access time, test function period 6/16/08 Copyright CoFluent Design 6

7 Integration approach: wrapping To be compatible with address-based transactions, tokens in the ESL testbench have to transport: A command (read/write PV/PVT) An address (to reach a memory) Data In the wrapper, generic commands have to be converted to GreenSocs transaction primitives: init_port.transact(transaction); init_port.request.block(transaction); Etc. We implement the wrapper as a SystemC module 6/16/08 Copyright CoFluent Design 7

8 Wrapper(sc_module_name name_, const char* data = NULL) : init_port("iport"), Mess_ToWrapper("Mess_ToWrapper"), Mess_FromWrapper("Mess_FromWrapper") { SC_THREAD(run); sensitive(init_port.default_event()); } I/Os must be compatible with the ESL tokens and with the IP-specific transactions void run(){ transactionhandle t1 = init_port.create_transaction(); while(1){ Mess_ToWrapper.Receive(&MessageToWrapper); if(messagetowrapper.command==wrpv){ t1->set_mcmd(generic_mcmd_wr); t1->set_maddr(messagetowrapper.address); t1->set_mdata(masterdatatype(&mem[0],strlen((char *)mem)+1)); t1->set_mburstlength(strlen((char *)mem)+1); init_port.transact(t1); Create transaction handler Receive token from ESL function PV write }else if(messagetowrapper.command==wrpvt){ t1->set_mcmd(generic_mcmd_wr);... init_port.request.block(t1); init_port.senddata(t1, init_port.get_phase()); PVT write } } }else if(messagetowrapper.command==rd){ t1->set_mcmd(generic_mcmd_rd);... MessageFromWrapper.Data=(const char *)mem; Mess_FromWrapper.Send(&MessageFromWrapper); } PV read, and send token back to ESL function 6/16/08 Copyright CoFluent Design 8

9 Automatic verification: use case example The behavior of the detailed platform model is verified automatically based on a use case, from the ESL testbench 6/16/08 Copyright CoFluent Design 9

10 Exploration of the detailed model We want to link ESL parameters to internal properties of the detailed platform model This permits studying the impact of parameter values on The behavior of the IP-based platform The performance of the complete system Only one compilation is required Example of parameters: Bus cycle Memory access time This association is done when instantiating the components of the detailed platform model 6/16/08 Copyright CoFluent Design 10

11 class GreenSocsModel : public FunctionClass { public: tlm_mess_initiator_port<deftokenwrapper> Mess_ToWrapper; tlm_mess_initiator_port<deftokenwrapper> Mess_FromWrapper; }; Wrapper m1; simplememory s1; simplememory s2; simplememory s3; simplememory s4; SimpleBusProtocol<GenericTransaction, GenericPhase> p; fixedpriorityscheduler<generictransaction, GenericPhase> s; GenericRouter<GenericTransaction, GenericPhase, GenericRouterAccess> r; GreenSocsModel(sc_module_name name, MessageQueueClass<DefTokenWrapper> *reffromwrapper, MessageQueueClass<DefTokenWrapper> *reftowrapper ) : FunctionClass(name), Mess_ToWrapper("Mess_ToWrapper"), Mess_FromWrapper("Mess_FromWrapper"), m1("wrapper","wrapper", reftowrapper, reffromwrapper), s1("memory1", MemoryDelay_ns), s2("memory2", MemoryDelay_ns), s3("memory3", MemoryDelay_ns), s4("memory4", MemoryDelay_ns), p("protocol", sc_time(busperiod_ns, SC_NS)), s("scheduler"), r("router") { } ~GreenSocsModel() { } FunctionClass allows to instrument the integrated model in the ESL testbench Declaration of the detailed platform components Platform internal properties are modified thanks to generic parameters that are declared in the ESL testbench 6/16/08 Copyright CoFluent Design 11

12 Detailed platform exploration results Impact of PV/PVT transactions 6/16/08 Copyright CoFluent Design 12

13 Detailed platform exploration results Impact of memory access time 6/16/08 Copyright CoFluent Design 13

14 Detailed platform exploration results Optimization of the verification time in the ESL testbench Example: PVT write/read cycle: 600 ns 600 ns 6/16/08 Copyright CoFluent Design 14

15 Conclusion (1/2) GreenSocs models can be integrated into a CoFluent ESL testbench Automatic verification of the GreenSocs model More accurate analysis and exploration of GreenSocs platform models The integration relies on a wrapper / transactor Conversion from message-level tokens (TL3) to specific transactions (TL2/TL1) and vice-versa Addressed-based transactions are simple to model in the ESL testbench CoFluent parameters are linked to GreenSocs internal properties Rapid exploration of PV/PVT, memory access times, etc. 6/16/08 Copyright CoFluent Design 15

16 Conclusion (2/2) We apply the same wrapping principle to close the implementation gap for HW components (FPGAs/ASICs) through HW behavioral synthesis The behavior of the system is validated in a reference transaction level testbench Critical elements are refined down to CA models (Catapult) These CA models (TL1) are wrapped and verified in the rerefence testbench (TL3) Conversion from tokens to handshakes & memory interfaces The reference testbench is back-annotated with exact timing properties for a more accurate (and still fast) architecture exploration Systematic wrapping methods are already available to integrate TLM2 IP models in CoFluent models 6/16/08 Copyright CoFluent Design 16

17 Questions? 6/16/08 Copyright CoFluent Design 17