EE382N: Embedded System Design and Modeling

Transcription

1 EE382N: Embedded System Design and Modeling Lecture 9 Communication Modeling & Refinement Andreas Gerstlauer Electrical and Computer Engineering University of Texas at Austin gerstl@ece.utexas.edu Lecture 9: Outline Communication layers Application Network: presentation, session, transport Protocol: link, stream, media access, physical Transaction-level modeling Abstraction levels Speed & accuracy tradeoffs Communication synthesis Protocol stack generation & optimization Backend HW/SW interface generation EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 2 (c) 2015 A. Gerstlauer 1

2 Specification-Level Communication Events, transitions Pure control flow, no data Shared variables No control flow, no synchronization Synchronous message passing No buffering, two-way control flow Asynchronous message passing Only control flow from sender to receiver guaranteed May or may not use buffers (implementation dependent) Queues Fixed, defined queue length (buffering) Complex channels Semaphores, mutexes Reliable communication primitives (lossless, error-free) EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 3 Taxonomy of Busses For each transaction between two communication partners 1 sender, 1 receiver PE1 PE2 1 master (initiator), 1 slave (listener) Sender Receiver t n t m Receiver Sender Master and/or slave? Any combination of master/slave, sender/receiver Master/Slave bus Statically fixed master/slave assignments for each PE pair PEs can be masters, slaves or both (dual-port) Node-based bus (e.g. Ethernet, CAN): Sender is master, receiver is slave Reliable (loss-less, error-free)?? Master and/or slave? EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 4 (c) 2015 A. Gerstlauer 2

3 Communication Modeling Busfunctional module Functional module Pin-Accurate (signals/wires) Transactions (function calls) Busfunctional module Functional module Pin-accurate model (PAM) Simulate every event (protocols) Transaction-level model (TLM) Communications by transactions (abstract channels) Granularity of transactions? Dynamic effects? Source: OSCI TLM-2.0 EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 5 Communication Layers ISO/OSI 7-layer network model Layer Semantics Functionality Implementation OSI Application Channels, variables Computation Application 7 Presentation End-to-end typed messages Data formatting Application 6 Session End-to-end untyped messages Synchronization, Multiplexing OS kernel 5 Transport End-to-end data streams Packeting, Flow control, Error correction OS kernel 4 Network End-to-end packets Routing OS kernel 3 Link Point-to-point logical links Station typing, Synchronization Driver 2b Stream Point-to-point control/data streams Multiplexing, Addressing Driver 2b Media Access Shared medium byte streams Data slicing, Arbitration HAL 2a Protocol Media (word/frame) transactions Protocol timing Hardware 2a Physical Pins, wires Driving, sampling Interconnect 1 A model, not an implementation! EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 6 (c) 2015 A. Gerstlauer 3

4 From Layers to System Models Cycle Accurate Model Transaction Level Models Specification Model App 7. Application MP 7. Application App 6. Presentation 6. Presentation 5. Session 5. Session OS 4. Transport 4. Transport OS 3. Network TLM 3. Network HAL 2b. Link + Stream 2a. Media Access 2b. Link + Stream 2a. Media Access HAL HW 2a. Protocol 2a. Protocol 1. Physical 1. Physical HW Address Data Control CAM EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 7 Specification Model Abstract, high-level system functionality Computation Processes Variables Communication Sync./async. message-passing Memory interfaces Events Abstract MP Channel Abstract MP Channel EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 8 (c) 2015 A. Gerstlauer 4

5 Application Layer (1) Synchronization Synthesize control flow BRcv BSnd PE1 PE2 Parallel processes plus synchronization events Implement sequential transitions across parallel components EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 9 Application Layer (2) Storage Shared variable mapping to memories v1 v1 BSnd PE1 C1 Distributed BRcv v1 PE2 C1 CPU C1 v1 HW Memory-mapped I/O C1 Map global storage to local memories CPU Mem Shared memory EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 10 v1 HW (c) 2015 A. Gerstlauer 5

6 Application Layer (3) Channels Complex channel synthesis HW1 C1 Queue C2 HW2 Dedicated hardware CQueue Client-server implementation Server process Remote procedure call (RPC) channels HW1 C1 Additional process HW2 EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 11 Architecture Model SW HW c1.recv(m1); c1 c1.send(m1); c2.send(m2); C3.send(m3); c2 c3 c2.recv(m2); C3.recv(m3); Application layer (virtual system architecture) Computation PEs (functionality) Memories (storage) Abstract end-to-end communication Queues, semaphores Sync./async. message-passing Shared variables/memories Events, transitions Reliable, loss-less application communication EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 12 (c) 2015 A. Gerstlauer 6

7 Presentation Layer Data formatting Translate abstract data types into canonical network byte layout 1. Global network data layout 2. Shared, optimized layout for each pair of communicating PEs Convert typed messages into untyped, ordered byte streams Convert variables into memory byte layout Bitwidth of machine character (smallest addressable unit) Size and Alignment (in characters) Endianess EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 13 Session Layer Channel merging Merge application channels into a set of untyped end-to-end message streams 1. Unconditionally merge sequential channels 2. Merge concurrent channels with additional session ID (message header) Channel selection over end-to-end transports C1 C2 HW2 C12 C1 C2 HW2 CPU C3 C4 P3 P4 HW1 CPU C1 C2 C3 C4 C3 C4 C3 P3 P4 C4 HW1 EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 14 (c) 2015 A. Gerstlauer 7

8 Network Layer Split network into subnets Routing of end-to-end paths over point-to-point links Insert communication elements (CEs) to connect busses CPU C1 C2 HW CPU C1 C2 L1A L2A CE L1B L2B C1 C2 HW Bridges Transparently connect slave & master sides at protocol level Bridges maintain synchronicity, no buffering Transducers Store-and-forwarding of data packets between incompatible busses Intermediate buffering, results in asynchronous communication EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 15 Transport Layer Packeting and routing Packetization to reduce buffer sizes 1. Fixed packet sizes (plus padding) 2. Variable packet size (plus length header) Protocol exchanges (ack) to restore synchronicity Iff synchronous message passing and transducer in the path Packet switching and identification (logical routing) 1. Dedicated logical links (defer identification to lower layers) 2. Network endpoint addressing (plus packet address headers) Physical routing in case of multiple paths between PEs 1. Static, predetermined routing (based on connectivity/headers) 2. Dynamic (runtime) routing EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 16 (c) 2015 A. Gerstlauer 8

9 Network Model Topology of communication architecture. PEs + Memories + CEs Upper protocol layers inserted into PEs/CEs Communication via point-to-point links Synchronous packet transfers (data transfers) Memory accesses (shared memory, memory-mapped I/O) Events (control flow) Middleware EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 17 Network Model SW T HW c1.recv(m1); c2.send(m2); C3.send(m3); c1 c2 c3 Net Link1 Link2 Net c3 c2 c1 c1.send(m1); c2.recv(m2); C3.recv(m3); Presentation, session: send(type msg) { char buf[m]; 1: msg->buf; 2: net.send(buf); Data conversion Network, transport: send(void* msg, len) { Packeting, acknowledgement Communication topology Network layers PEs + Memories + CEs Transducers (store-and-forward) Point-to-point link communication Synchronous packet transfers (data link channels) Memory accesses (shared memory, memory-mapped I/O) Events (control flow) EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 18 (c) 2015 A. Gerstlauer 9

10 Link Layer (1) Synchronization (1) Ensure slave is ready before master initiates transaction 1. Always ready slaves (memories and memory-mapped I/O) 2. Defer to fully synchronized bus protocol (e.g. RS232) 3. Separate synchronization mechanism Events from slave to master for master/slave busses Synchronization packets for node-based busses EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 19 Link Layer (2) Synchronization (2) Dedicated interrupts Shared interrupts PE1 BUS PE2 intflag? S0 intflag Set Read rdyflag Interrupt handler Generate interrupt rdyflag Set S0 S1 R/W Data Master I/O Slave I/O R/W Data S1 Transfer request? EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 20 (c) 2015 A. Gerstlauer 10

11 Link Layer (3) Synchronization (3) Slave polling PE1 BUS PE2 rdyflag? S0 Read rdyflag rdyflag Set S0 S1 R/W Data Master I/O Slave I/O R/W Data S1 Transfer request? Flag in master PE1 rdyflag? S0 rdyflag Slave I/O BUS Master I/O Write rdyflag S0 PE2 S1 R/W Data Master I/O Slave I/O R/W Data S1 Transfer request? EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 21 Stream Layer Addressing Multiplexing of links over shared medium Separation in space through addressing Assign physical bus addresses to links 1. Dedicated physical addresses per link 2. Shared physical addresses plus packet ID/address in packet header EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 22 (c) 2015 A. Gerstlauer 11

12 Media Access (MAC) Layer Data slicing Split data packets into multiple bus word/frame transactions Optimized data slicing utilizing supported bus modes (e.g. burst) Arbitration Separate individual bus transactions in time 1. Centralized using arbiters 2. Distributed Insert arbiter components EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 23 Protocol TLM Abstract component & bus structure/architecture PEs + Memories + CEs + Busses Communication layers down to protocol transactions Communication via transaction-level channels Bus protocol transactions (data transfers) Synchronization events (interrupts) Driver Middleware EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 24 (c) 2015 A. Gerstlauer 12

13 Protocol TLM CPU T HW SW c3 c2 c1 Net Link MAC TLM Bus1 TLM Bus2 MAC Link Net c3 c2 c1 int Link, stream: send(void* p, len) { S1 S2 wait(intr); mac.write(p, addr); Synchronization, addressing Media access: inthandler() { notify(intr); write(void* d, len, a) { Data slicing System communication architecture Link layers PEs + Memories + CEs + Busses Bus bridges Communication via bus transactions (bus TLM) Address, data, arbitration Synchronization (interrupts, polling) EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 25 Protocol, Physical Layers Bus interface Generate state machines implementing bus protocols Timing-accurate based on timing diagrams and timing constraints Bus protocol database HCLK HREQ HGRANT HCNTRL HADDR HWDATA HREADY nonseq. word 0xA Port mapping and bus wiring Connectivity of component ports to bus, interrupt wires/lines Generate top-level system netlist 0x2F00 0x Arbitration Cycle Address Cycle Data Cycle time EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 26 (c) 2015 A. Gerstlauer 13

14 Pin-/Bus Cycle-Accurate Model (P/BCAM) Component & bus structure/architecture PEs + Memories + CEs + Busses Pin-accurate bus-functional components Pin- and cycle-accurate communication Bus and interrupt protocols Pins and wires Arbiter Driver Middleware EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 27 Pin-Accurate Model (PAM) c3 c2 c1 Net SW Link int MAC ISR Protocol CPU Bus1 int T Bus2 HW Protocol MAC Link Net c3 c2 c1 Protocol, physical: writeword(addr, word) { Bus-functional layers PEs + Memories + CEs + Busses Pin-, cycle- and bit-accurate bus-functional components Communication via ports and wires Address, data, control busses Interrupts Protocol timing, wire driving & sampling EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 28 (c) 2015 A. Gerstlauer 14

15 Lecture 9: Outline Communication layers Application Network: presentation, session, transport Protocol: link, stream, media access, physical Transaction-level modeling Abstraction levels Speed & accuracy tradeoffs Communication synthesis Protocol stack generation & optimization Backend HW/SW interface generation EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 29 TLM Abstraction Levels ISO/OSI reference layer-based architecture Granularity of data and arbitration handling Layers: 1) Media Access Control (MAC) User Transaction» Contiguous block of bytes» Arbitrary length, base address 2) Protocol Bus Transaction» Bus primitives (e.g. store word)» Observes bus address restrictions 3) Physical Bus Cycle» Drive or sample bus wires on bus cycle Models are composed of layers Using fewer layers yields a more abstract model Source: G. Schirner, R. Dömer, Quantitative Analysis of the Speed/Accuracy Tradeoff in Transaction-Level Models, ACM TECS, EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 30 (c) 2015 A. Gerstlauer 15

16 Bus Functional Model (BFM) Implemented Layers: Granularity: MAC Protocol Physical May or may not be pin accurate Bus cycle accurate Arbitration check on each cycle Includes additional active components Multiplexers (tri-state-free bus) Arbiter Address decoder Clock generator AMBA AHB [ARM] EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 31 Transaction Level Model (TLM) Implemented Layers: Granularity: MAC Protocol Bus primitives StoreWord, StoreBurst4 Abstract model Not pin accurate, not bus cycle accurate in all cases Priority arbitration per bus transaction May lead to wrong arbitration decision, depending on execution order EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 32 (c) 2015 A. Gerstlauer 16

17 MAC-TLM Implemented Layers: Granularity: MAC User transaction (message) Arbitrary length, contiguous block of bytes No arbitration: contention avoidance by semaphore Resolution depends on simulator Expected to be the fastest model Single memcpy, Single time wait EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 33 TLM Accuracy Limitations Example: Low priority burst starting at t 0 High priority preemption at t 1 BFM: check every cycle slow accurate TLM: coarse grain check fast inaccurate: low prio. burst ends at t 2 instead of t 4 EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 34 (c) 2015 A. Gerstlauer 17

18 TLM Trade-Off Bus models AMBA AHB, CAN, ColdFire BFM, TLM, MAC-TLM Performance analysis 2 masters, 2 slaves Randomly distributed traffic 100 byte transactions 40% bus contention Transfer duration BFM TLM MAC -TLM Model Speed Error M-TLM <100 MByte/s 32% - 47% TLM ~ 1 MByte/s 18% - 39% BFM <0.2 MByte/s 0% 100x 100x EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 35 SystemC/TLM Loosely-timed Sufficient timing detail to boot OS and simulate multi-core systems Each transaction has 2 timing points: begin (call) and end (return) Typically blocking transport calls Initiator BEGIN END Target Approximately-timed Cycle-approximate or cycle-countaccurate Sufficient for architectural exploration Each transaction has at least 4 timing points Typically non-blocking transport calls BEGIN_REQ END_REQ BEGIN_RESP END_RESP Initiator Target Source: OSCI TLM-2.0 EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 36 (c) 2015 A. Gerstlauer 18

19 Advanced TLM Modeling tricks [SystemC/TLM] Early completion of non-blocking REQ/RESP sequence Timing annotation on call/return (pass) Temporal decoupling & quantum (lump, out-of-order) Direct interface (bypass) Advanced modeling approaches (see OS modeling) Conservative [ATGA] Optimistic [ROM] EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 37 Result-Oriented Modeling (ROM) Characteristics Observability at boundary of transaction Internal state changes not visible, may not be modeled Optimistically predict the end result at beginning optimistic == earliest time to finish Record disturbing influence Corrective measures at the end Source: G. Schirner, R. Dömer, Fast and Accurate Transaction Level Models using Result Oriented Modeling, ICCAD, EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 38 (c) 2015 A. Gerstlauer 19

20 Result Oriented Modeling (ROM) Same example transfer: Low priority burst at t 0 High priority preemption at t 1 ROM: t 0 low: predict t 2 t 1 high: preempt, predict t 3, record preemption for low t 2 low: detect disturbance, prediction update t 4 t 3 high: no preemptions, finish t 4 low: no preemptions, finish Accurate EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 39 ROM Results Two concurrent masters High priority: 33% bus load Measure bandwidth of low priority 100% accuracy ROM, BFM both on top No error BFM ATLM ROM At coarse-grain speeds ROMand TLM are in same magnitude! CAN ROM can not outperform TLM Data dependent length Bit inspection CRC, stuffing bits TLM EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 40 (c) 2015 A. Gerstlauer 20

21 Lecture 9: Outline Communication layers Application Network: presentation, session, transport Protocol: link, stream, media access, physical Transaction-level modeling Abstraction levels Speed & accuracy tradeoffs Communication synthesis Protocol stack generation & optimization Backend HW/SW interface generation EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 41 Protocol Stack Optimizations (1) Automatically generated code during refinement Layer-based code organization and separation PE c1.send(m1); c1 c2.send(m2); C3.send(m3); Presentation: Network: Link: send(type msg) { char buf[m]; 1: msg->buf; 2: net.send(buf); Data conversion c2 c3 Net Link MAC send(d) { 1: for (p in d) { link.send(d[p]); 2: link.recv(ack); Packeting, acknowledgement send(p) { 1: wait(intr); 2: mac.write(p); Synchronization MAC: write(b) { 1: for(w in b) { protocol.write(w); Data slicing EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 42 (c) 2015 A. Gerstlauer 21

22 Protocol Stack Optimizations (2) Apply automatic code optimizations during refinement Code optimized for HW/SW synthesis Layer merging and cross-optimizations (inline/interleave) PE c1.send(m1); c1 Merging of messages c23.send(m2,m3); c23 Code flattening Interrupt hoisting Fusion of packeting and conversion Word-aligned transactions send(type1 msg1, type2 msg2) { word buf; 1: wait(intr) 2: for (w in msgs) { msg[w]->buf; protocol.write(buf); 3: wait(intr); protocol.read(ack); EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 43 Interface Synthesis (1) PE1 PE2 readbyte(bit[] addr, bit[8] data) writebyte(bit[] addr, bit[8] data) readword(bit[] addr, bit[16] data) writeword(bit[] addr, bit[16] data) Protocol FSMD control addr data Bus Interface FSM / FU c23 c1 Protocol c123 Protocol RTL Database / Generator / IP PE1 Computation FSMD PE2 Computation FSMD Protocol FSMD control addr data Bus Interface FSM / FU PE1 PE2 EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 44 (c) 2015 A. Gerstlauer 22

23 Interface Synthesis (2) PE1 PE2 PE1 Computation/protocol FSMDs Bus Interface FSMD / FU Interrupt generation Protocol Protocol Int ISR send() receive() RTL Database / Generator / IP PE2 Computation/protocol FSMDs flag Interrupt detection Bus Interface FSMD / FU PE1 PE2 EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 45 Transducer Synthesis T1 Protocol Protocol RTL Database / Generator / IP Inline and compile/synthesize RTL Database / Generator / IP Bus Interface FSMD / FU control addr data Queue FSMDs control addr data Bus Interface FSMD / FU EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 46 (c) 2015 A. Gerstlauer 23

24 Cycle-Accurate Model (CAM) Component & bus implemenation PEs + Memories + CEs + Busses Cycle-accurate components Instruction-set simulators (ISS) runing final target binaries RTL hardware models Bus protocol state machines EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 47 Lecture 9: Summary Communication modeling & refinement Systematic, structured communication design flow Layer-based modeling and refinement Well-defined levels, models and design steps Support for rich applications and wide variety of target architectures Transaction-level modeling (TLM) of communication Rapid, early feedback, validation and exploration Various levels of abstraction, accuracy vs. speed tradeoffs Communication synthesis Generation of communication layer implementations Application and target-architecture specific, customized and optimized Protocol stack optimizations Merging and cross-optimizations of layers Interface backend synthesis EE382N: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 48 (c) 2015 A. Gerstlauer 24