Marcel Jacomet Roger Walti Lukas Winzenried Jaime Perez Martin Gysel. and verication of the FPGAs.

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1 : A Low Cost Rapid Prototyping and Test System f ASICs and FPGAs Marcel Jacomet Roger Walti Lukas Winzenried Jaime Perez Martin Gysel Biel School of Engineering, MicroLab{I3S, CH-2501 Biel, Switzerland Marcel.Jacomet@isbiel.ch Abstract The test bench methodology helps the design engineer to structure the simulation of his circuit. As showed in this paper, the test bench methodology can further be developed in der to eciently reuse simulation stimuli and f the real device under test. As FPGAs are very often used to prototype an ASIC design, an easy switch between simulation and real hardware test is necessary to establish a rapid prototyping design and test environment. Our system closes the gap between the simulation and the test environment with a low cost and easy to use computer{aided{test environment. 1. Introduction The technological evolution in microelectronics has lead to a permanent raise in complexity of VLSI systems integrated on high density chips. Since development and test time should not grow linearly with the complexity of VLSI chips new design and test methods are needed. At the microelectronics labaty of the Interdisciplinary Institute of Integrated Systems (MicroLab{I3S) a modern test bench design methodology [1,3] is used to eciently design VLSI circuits f research and industry projects. The following steps can be identied: step 1: Digital systems are designed using a technology independent hardware description languages like VHDL Verilog{HDL. The digital system is then simulated using the test bench methodology. step 2: The HDL description is synthesized into a logical fmat f recongurable FPGA chips. The FPGA chips are veried in real time on the low Further infmation about can be found on: cost rapid prototyping test system using the already dened test bench. step 3: The HDL description is synthesized into the target ASIC technology. The ASIC prototype chips are tested on the environment with the same test bench procedure as used f simulation and verication of the FPGAs. If the objective is to design an FPGA, then the rst two steps have to be perfmed. If the nal goal is to get an ASIC a masked programmable FPGA, step 3 has to be added. Synthesizing an FPGA in the ASIC design ow, described in intermediate step 2, has several advantages. This method allows to check f success of the design{f{testability atamuch earlier stage. Also specication errs are discovered befe producing the ASIC. This does lead to a much improved success rate f a crect design on the rst attempt. Thus the presented design methodology is a consequent implementation of the state{of{the art design{f{test approach. The key element of this design methodology is the system with the universal test adapter f dierent devices under test () like our FPGAs ASICs. VHDL CAD design tool Verilog-HDL CAD design tool Verilog-HDL monit VHDL monit CAT- Tool (server-client) HP16500 test machine low cost test machine Figure 1. CAT- tool acts as an interface between CAD design tools and test machines.

2 2. System Description The Computer{Aided{Test software CAT{ acts as an interface between the CAD environments and the test machines (see Fig. 1). The CAT{ software is implemented as client server conguration, which allows the suppt of multiple clients and test{ machines simultaneously. Since the CAT{ software is written in the platfm independent Java language, test sessions can even be controlled via internet access CAT- Tool Simulation results from the CAD environments are converted to test s f a specied test machine. The test results are taken back into the CAD simulation environment and compared against the simulation. Signal to physical pin mapping have tobe dened with the CAT{ tool. Currently drivers f the low{cost test machine and the HP16500 generat and logic analyzer are available. The CAT- tool can also be used as stand alone test development tool, without using any CAD environments. In this conguration the test program can be developed hierarchically with the CAT{ tool by dening test s (see Fig. 2) and expected s, test sequences and nally the test programm itself. The test machines can directly be controlled by the CAT- tool. In stand-alone conguration the test results can be visualized graphically with the CAT- tool Low Cost Test Machine The low{cost hardware test machine (Fig. 3) is able to generate test vects and s with a resolution of 100ns. Up to six dierent clock signals can be generated with the hardware. The test machine has 240 congurable signal input, output, bidirectional and clock pins (see Fig. 4). A library of universal test adapters allows the test of ASICs and FPGAs with standard device sockets. User specic test adapter PCBs can easily be developed. Denition of user specic test adapters can be done with the CAT- tool. Figure 3. Prototype of test machine. Figure 2. Test tool. definition in CAT- Using the HP16500 generat and logic analyzer an improved resolution of 4ns is achievable Monit The is designed as a VHDL and a Verilog-HDL library package. Fig. 5 illustrates a sample VHDL test bench consisting of a simulation model call and a call. Every input, output bidirectional signal of the has to be dened with a procedure call like MinitInpSignal, MonitOutSignal MonitBidSignal. Clock signals are generated by calling the MonitClock procedure. A simple HDL variable is used to switch between the

3 use std.textio.all; library IEEE; use IEEE.std_logic_1164.all; library ; use.monit_2_0.all; entity TestBench is end TestBench; Architecture sample of TestBench is signal data : std_ulogic_vect(7 downto 0); signal clk,load,dir : std_ulogic; signal tmp_bus : std_ulogic_vect(7 downto 0); signal tmp_adr : std_ulogic_vect(7 downto 0); signal adr,bus : std_logic_vect(7 downto 0); Figure 4. Definition of input, output and bidirectional pins with the CAT- tool. simulation of the circuit model and the comparison between this simulation model with the test from the real Clock Cycle The input s are applied at the ning of each test cycle. The of the output s are d at a predened time in the test cycle. A sample clock signal within a test cycle is shown in Fig Test Bench Methodology Fig 7 shows a classical test bench used to simulate and verify a circuit model described with a hardware description language with a schematic. The prede- ned s test s and simulation s in a le during regular simulation. The is activated by a VHDL Verilog{ HDL library call. Once the digital system is designed and veried, synthesis into an FPGA an ASIC target technology can be perfmed. In der to guarantee a rapid prototyping, reuse of the simulation test bench is mandaty. The environment uses the same test bench as already developed in the HDL simulation and verication phase. Test s and simulation results d by the during simulation are used to stimulate the real device{under{test. Fig. 8 illustrates the close relationship between the CAT{ software and a test-machine. component FPGA_circuit pt(adrin: in std_ulogic_vect(7 downto 0); clk,load,dir : in std_ulogic; adr,bus : out std_ulogic_vect(7 downto 0); end component; : FPGA_circuit pt map(data, lock, load, tmp_adr, tmp_bus, dir); adr <= std_logic_vect(tmp_adr); bus <= std_logic_vect(tmp_bus); -- Test Bench Monit TB: Block _monit: process file ofile: text is out "_.vec"; file ifile: text is in "_.res"; -- definition of global variable variable dutv : datarec; -- variable to mask signals f comparison constant mask: boolean:=false; MonitClock(ofile,ifile,dutv,simulate, "clk",clk,'0',20 ns,40 ns,80 ns,100 ns,10 ns); MonitInpSignal(ofile,dutv,"data",data); MonitInpSignal(ofile,dutv,"load",load); MonitOutSignal(ofile,dutv,"adr",adr,mask); MonitBidSignal(ofile,dutv,"bus",bus,dir,mask); end process; end block; -- Test Bench Signal Stimuli end sample; Figure 5. Sample test bench file f simulation with VHDL procedure calls.

4 clock1 stimuli application test result le into the users CAD environment in der to perfm the comparison between simulation and obtained with a test machine. Fig. 9 illustrates the test bench used to read back the test results into the CAD environment. test cycle Figure 6. Typical test cycle with clock signal. manualy test bench (CAD environment) circuit model verification test bench (CAD environment) circuit model test file and comparison with real Figure 9. CAD environment interfaces to testmachine results. simulation stimuli and file Figure 7. Test bench f simulation with additional to stimuli and vects. Design engineers are used to wk with CAD environments. Thus design and test procedures are faster if no additional tools have to be introduced to test the. We reuse the test bench developed f circuit simulation f the real tests and result comparisons. Therefe the circuit model is simulated once again and the simulation results are immediately compared with the s in the CAD environment. In der to perfm the comparison of the simulation data with the real chip test data, a simple switch of the monit has to be changed from simulation to comparison. The switch causes the to load the simulation stimuli and file CAT- test-machine ASIC FPGA verification Figure 8. CAT- software interface to test-machine. 4. Related Wk There exist numerous FPGA development boards, but they hardly can be compared with a rapid prototyping system with a tight link to a HDL simulat as presented in this paper. Alowcost test system called MacTester was recently presented in [2]. The MacTester has on-line testing capabilities and is tightly connected to Mac computers with the LogicWks simulation software. The disadvantage of the MacTester is its 3rd party tool and computer platfm dependency and especially the lack of the test bench methodology implemented in the test procedure. 5. Results and Conclusions Surveys of HDL users have indicated that the of HDL test benches typically consumes 35% of the entire front{end ASIC design cycle. It is clear that the reuse of the test bench f the test of ASICs and FPGAs would signicantly reduce the costs of HDL based designs. The presented system achieves the primary goal to merge design, rapid prototyping and test of ASICs and FPGAs. Due to the client server based principle of the CAT{ system, student class exercises on design{f{test can easily be executed. Using an application specic test adapter PCB, one even several integrated circuits can be grouped to fm a. In such a conguration the target integrated circuit can be tested in its application environment similar to a bread{board design. The CAT{ software can either be used as a stand alone (see Fig. 10) test development tool as an easy to

5 Figure 10. In stand-alone configuration the test results of can be viewed in the CAT- tool. handle interface between CAD design tools and test machines. Due to the principle described above, all 3rd party CAD simulation tools using the VHDL Verilog{HDL description language are suppted by the CAT{ tool. As the CAT{ tool is written in the Java language, the system represents a highly platfm and CAD vend independent rapid prototyping and test environment. References [1] M. A. Breuer and A. D. Friedman. Diagnosis and Reliable Design of Digital Systems. IEEE Computer Society Press, Nth-Holland, [2] N. R. McKenzie, C. Ebeling, L. McMurchie, and G. Briello. Experiences with the mactester in computer science and engineering education. IEEE Trans. on Education, vol. 40:12{21, [3] N. N. E. Weste and K. Eshraghian. Principles of CMOS VLSI Design. Addison-Wesley Publishing Company, [4] T. W. Williams and K. P. Parker. Design f testability { a survey. InProceedings of the IEEE, volume Vol. 71, pages 98 { 112, January 1983.