FPGAs: : Quality through Model Based Design and Implementation
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1 FPGAs: : Quality through Model Based Design and Implementation Yves LaCerte Rockwell Collins Advanced Technology Center 400 Collins Road N.E. Cedar Rapids, IA ylacerte@rockwellcollins.cm Yang Zhu General Dynamics Advanced Information Systems 8800 Queen Ave South Bloomington, MN Yang.Zhu@gd-ais.com ais.com
2 The Challenge Transform C code into Impulse C Commercial version of Streams-C C (Los Alamos National Lab) Efficient compiler technology to map high level parallel-c language descriptions into circuits FPGAs under the control of a software engineer with application-specific knowledge Polarimetric imaging application Convolutions, FFT, etc 1,000 lines of C code 2
3 Implications Transform C to Impulse C Parallelize the code Architecture Issues es Streams Signals Clocking strategies Accuracy/precision of computations Memory 3
4 SW Engineer or HW Engineer Can we remove the boundary? Overlap? Specialized? HW engineer is still needed Tweak/debug VHDL Build FPGA infrastructure 4
5 Can Coding Be Automated Model transformation Transform a model into another model From model to C, Impulse C From processes and streams into standardized, error free code Modeling blurs the distinction between HW and SW engineers Shift toward domain expertise Automated transformations can produce high quality code 5
6 When is it enough? 2006 MAPLD International Conference Enough Parallelization Model performance early Analysis performed at design time, before detailed simulation of completed code Use architecture description language 6
7 Typical Specifications System Model / C Code RTL Description (VHDL or Verilog) Synthesis FPGA Place and Route Gate Level Simulation Post Layout Simulation / Timing Static / Dynamic Analysis RTL Simulation / Timing 7
8 Enhanced Specifications Architecture Model System Model / C Code RTL Description (VHDL or Verilog) Synthesis FPGA Place and Route Gate Level Simulation Post Layout Simulation / Timing Architecture Analysis Static / Dynamic Analysis RTL Simulation / Timing 8
9 Architecture Model Clock Strategy B Memory E A Port Depth High Bandwidth Synchronous C F Low Bandwidth Asynchronous G Execution D Deployment 9
10 Architecture Analysis Architecture Analysis and Design Language (AADL) Architecture description language SAE standard AS5506 System device memory Models structure and high-level constraints of embedded computer systems Abstract specifications with general system design concepts Components, interconnections, hierarchy, data flow, etc. Concrete Specifications Properties (custom name/value pairs) Annexes (non-standard language embedded in AADL specifications) in in out bus processor Data Thread out 10
11 System Model Architecture Model Platform Independent Model Transform Rules System Model / C Code Platform Specific Platform Model Specific Platform Model Specific Model Any language From code-oriented to model-oriented production techniques Clear separation of the fundamental logic of the specification from the particular implementation 11
12 Conclusion Rapid high quality implementation of Impulse C code suitable for FPGA High quality through model transformations Rapid through performance analysis of models Models and analyses necessarily coarse grained Notions extensible to any FPGA and any code base 12
FPGAs: High Assurance through Model Based Design
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