DRPM architecture overview
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1 DRPM architecture overview Jens Hagemeyer, Dirk Jungewelter, Dario Cozzi, Sebastian Korf, Mario Porrmann Center of Excellence Cognitive action Technology, Bielefeld University, Germany Project partners: European Agency, ESTEC, Netherlands Politecnico di Torino, Italy Swiss Technology, Switzerland TWT GmbH Science & Innovation, Neuhausen, Germany
2 DRPM architecture overview System Architecture Run-Time Infrastructure
3 DRPM System Overview Design goals Scalability Number, type and size of s faces Migration path towards future flight versions Debugging and monitoring facilities DRPM Dynamically Reconfigurable 3
4 Platform for DRPM implementation RAPTOR Prototyping Systems Prototypic Implementation of Microelectronic Circuits on s PCI-X / PCIe Mainboard Up to six modules High bandwidth between modules Partial dynamic reconfiguration USB USB USB 2.0-High-Speed USB-OTG System Monitor Voltage, Tempature, Analog Inputs Clock Sythesis, Distribution TST-JTAG CFG-JTAG USB Logic - Master - Slave OTG-Control +Config Logic Arbiter, MMU Diagnostics, CLK, Configuration, etc. Xilinx SystemACE CF CF Access, JTAG Control PCI-X- (64Bit Data / 32Bit Address) PCI-- Master, Slave, DMA Dual-Port SRAM 6, SMB SelectMAP, CFG-JTAG - (32Bit Data / 32Bit Address) 85 75, SMB SelectMAP, CFG-JTAG 85 75, SMB SelectMAP, CFG-JTAG Broadcast- 4
5 Platform for DRPM implementation -s I/O-s Xilinx s up to Virtex 5 (7-series in design) Embedded processors Up to 4 GB SDRAM Ethernet FireWire, USB CAN, LON, EIB, bus Serial, Parallel Analog I/Os Digital I/Os SSI interfaces VGA interface 5
6 DRPM Overview USB I/F Host PC PCI-X/ RAPTOR Configuration Logic PR (Virtex-4) RS232/ Flash PR (Virtex-4) CAN Debug Timer Wire 422 (2x) ADC/DAC SRAM FIFO I/F MEM I/F FPU LEON2-FT Wire-RTC CPLD External Ext. Comm. nal Comm. DDR2-RAM DB-V4 DB-SPACE DDR2-RAM DB-V4 6
7 DB-SPACE CAN ADC/DAC Ext. Comm. Wire (4x) FIFO I/F FIFO Wizard Debug Timer MEM I/F MEM MIL-STD- 1553B I/F RS232/ 422 FPU Wire (2x) LEON2-FT Wire-RTC Flash SRAM CPLD External nal Comm. DB-SPACE System : Wire RTC AT7913E LEON2-FT CPU 2 Wire faces CAN, ADC/DAC,, External 4 Wire s Wizard face (2.7 Gbit/s) used as PHY for Fibre MIL-STD-1553B 32b nal Flexible communication to other modules Monitoring interface AMBA 4 communication between IP cores Ext. 7
8 DB-SPACE Frontpanel DB-SPACE Frontpanel CAN Debug Timer RS232/ 422 Wire (2x) Flash ADC/DAC FIFO I/F MEM I/F FPU LEON2-FT Wire-RTC SRAM CPLD External Ext. Comm. FIFO MEM nal Comm. Wire (4x) Wizard MIL-STD- 1553B I/F DB-SPACE DB-SPACE Frontpanel Easy access to the interfaces of DB-SPACE 8
9 DB-V4 Partially Reconfigurable Region ^ ^ Dynamic Control Unit MicroBlaze BRAM Frame ECC PR (Virtex-4) ICAP Self-Hosting DDR2-RAM DB-V4 4 GByte DDR2 SDRAM memory Configuration Cache Static Area Multi Port 32b data, 7b ECC (BCH 32,7) Integrated ECC statistics unit Integrated fault injection based module interconnect to other modules Monitoring and debug bridge for streaming data controller Dynamic Control Unit Partially Reconfigurable Region 9
10 DB-V4 Partially Reconfigurable Region PR Region Comm. Infrastructure Dynamic Control Unit BRAM MicroBlaze PR (Virtex-4) Frame ICAP ECC Self-Hosting DDR2-RAM DB-V4 Partially Reconfigurable Region Tiled PR-region Flexible module placement PR-modules can be placed at any position within the partially reconfigurable region Homogeneous communication infrastructure Integrated address decoder and PR tile management Enables relocation of modules Automatically generated using DHHarMa tool [FCCM 2011] ^ ^ 10
11 DB-V4 macro must occupy the same resources in every tile Homogeneity allows placement of modules at any position with the same type of tiles Automatic generation of communication infrastructure based on VHDL specification Dedicated placer and router for homogeneous macros up to Xilinx Virtex-7 Static Region PR Modul Tile 1 A PR Modul B Tile 2 PR-Region PR Modul C 11
12 DB-V4 DHHarMa toolflow overview Starting from HDL description Based on XDL, using Xilinx tools as Frontend Automatic creation of homogeneous structures Allows easy modifications Allows easy migration to other (Families) 12
13 DB-V4 Partially Reconfigurable Region Tile 1.1 Tile 2.1 MPMC Tile 1.2 Tile 2.2 Tile 1.3 Tile 2.3 BRAMC VCM to EWB bridge Tile 1.4 Tile 2.4 Tile 1.5 Tile 2.5 Tile 1.6 Tile 2.6 Tile 1.7 Tile 2.7 Tiled PR-region Flexible module placement PR-modules can be placed at any position within the partially reconfigurable region Homogeneous communication infrastructure Integrated address decoder and PR tile management Enables relocation of modules Automatically generated using DHHarMa tool [FCCM 2011] Tile 1.8 Tile 2.8 INTC MicroBlaze PR tile decoder Xilinx Virtex-4 FX100 13
14 External Partially Reconfigurable Region PR Region Comm. Infrastructure Dynamic Control Unit MicroBlaze BRAM Frame ECC PR (Virtex-4) Self-Hosting ICAP RS232/ CAN Debug Timer 422 Wire (2x) ADC/DAC FIFO I/F MEM I/F FPU LEON2-FT Wire-RTC Ext. Comm. FIFO MEM Flash CPLD SRAM External nal Comm. DDR2-RAM DB-V4 Wire (4x) Wizard MIL-STD- 1553B I/F DB-SPACE Initial startup configuration of and s 128 Mbyte flash memory stores golden copies of all configuration data Partial run-time reconfiguration of s Accessible via any configured interface, e.g., Wire, MIL-STD-1553B SelectMap reconfiguration with 50 MByte/s Supports blind scrubbing 14
15 Self-hosting Partially Reconfigurable Region PR Region Comm. Infrastructure Dynamic Control Unit MicroBlaze BRAM Frame ECC PR (Virtex-4) Self-Hosting ICAP CAN ADC/DAC Ext. Comm. FIFO I/F FIFO Debug MEM I/F MEM Timer RS232/ 422 FPU Wire (2x) LEON2-FT Wire-RTC Flash SRAM CPLD External nal Comm. DDR2-RAM DB-V4 Wire (4x) Wizard MIL-STD- 1553B I/F DB-SPACE Partial run-time reconfiguration implemented in the static part of the DDR2-SDRAM stores configuration data Dynamic Control Unit Maintains the free resources, determines feasible position for new modules Self-hosting Performs bitstream relocation, transfers bitstream to ICAP 15
16 Self-hosting Partially Reconfigurable Region PR Region Comm. Infrastructure Dynamic Control Unit MicroBlaze BRAM Frame ECC PR (Virtex-4) Self-Hosting ICAP CAN ADC/DAC Ext. Comm. FIFO I/F FIFO Debug MEM I/F MEM Timer RS232/ 422 FPU Wire (2x) LEON2-FT Wire-RTC Flash SRAM CPLD External nal Comm. DDR2-RAM DB-V4 Wire (4x) Wizard MIL-STD- 1553B I/F DB-SPACE Partial run-time reconfiguration is triggered internally or via external interfaces 400 MByte/s reconfiguration bandwidth Readback scrubbing using intrinsic EDAC support of the Individual scrubbing rates for different regions Fault injection utilizing partial reconfiguration Monitoring and statistics functions 16
17 Infrastructure Partially Reconfigurable Region PR Region Comm. Infrastructure Dynamic Control Unit BRAM MicroBlaze PR (Virtex-4) Frame ICAP ECC Self-Hosting RS232/ CAN Debug Timer 422 Wire (2x) ADC/DAC FIFO I/F MEM I/F FPU LEON2-FT Wire-RTC Ext. Comm. FIFO MEM Flash CPLD SRAM External nal Comm. DDR2-RAM DB-V4 Wire (4x) Wizard MIL-STD- 1553B I/F DB-SPACE - interface for communication between s Abstracts from physical interface between s Master/Slave interface to / bus Routing capability for up to four ports (IP core configured at design-time) Integrated packetizer and flow control 17
18 Infrastructure Partially Reconfigurable Region PR Region Comm. Infrastructure Dynamic Control Unit MicroBlaze BRAM Frame ECC PR (Virtex-4) Self-Hosting ICAP CAN ADC/DAC Ext. Comm. FIFO I/F FIFO Debug MEM I/F MEM Timer RS232/ 422 FPU LEON2-FT Wire-RTC Wire (2x) Flash SRAM CPLD External nal Comm. DDR2-RAM DB-V4 Wire (4x) Wizard MIL-STD- 1553B I/F DB-SPACE - interface for communication between s DMA unit enables burst transfers RRMU (Resource and Management Unit) schedules parallel data transmission and controls the involved DMA units 18
19 Infrastructure Partially Reconfigurable Region PR Region Comm. Infrastructure Dynamic Control Unit MicroBlaze BRAM Frame ECC PR (Virtex-4) Self-Hosting ICAP CAN ADC/DAC Ext. Comm. FIFO I/F FIFO Debug MEM I/F MEM Timer RS232/ 422 FPU LEON2-FT Wire-RTC Wire (2x) Flash SRAM CPLD External nal Comm. DDR2-RAM DB-V4 Wire (4x) Wizard MIL-STD- 1553B I/F DB-SPACE - interface for communication between s DMA unit enables burst transfers RRMU (Resource and Management Unit) schedules parallel data transmission and controls the involved DMA units 19
20 Infrastructure Partially Reconfigurable Region PR Region Comm. Infrastructure Dynamic Control Unit MicroBlaze BRAM Frame ECC PR (Virtex-4) Self-Hosting ICAP CAN ADC/DAC Ext. Comm. FIFO I/F FIFO Debug MEM I/F MEM Timer RS232/ 422 FPU Wire (2x) LEON2-FT Wire-RTC Flash SRAM CPLD External nal Comm. DDR2-RAM DB-V4 Wire (4x) Wizard MIL-STD- 1553B I/F DB-SPACE - interface for communication between s DMA unit enables burst transfers RRMU (Resource and Management Unit) schedules parallel data transmission and controls the involved DMA units 20
21 Infrastructure Signaling Rate Effective Bandwidth Wire-RTC 200 Mbit/s (FD) 160 Mbit/s (FD) Wire- 200 Mbit/s (FD) 160 Mbit/s (FD) Wizard 2700 Mbit/s (FD) 2100 Mbit/s (FD) MIL-STD-1553B 1 Mbit/s (HD) 0.7 Mbit/s (HD) Mbit/s (FD) 3100 Mbit/s (FD) AMBA Mbit/s 3100 Mbit/s 6400 Mbit/s 6200 Mbit/s Wizard IP Core Integrated scatter gather DMA functionality 2.7 Gbit/s (2.1 Gbit/s effective) 3m PCIe cable (4.5m chip to chip) Next step: Integration of Fibre protocol Transmitter Receiver 21
22 Scalability - Examples (DB-V4) (DB-V4) (DB-SPACE) (DB-V4) (DB-V4) (DB-V4) 6x Wire 1x Wizard, MIL, CAN, ADC/DAC 54x 20 GByte DDR2, 1 Gbit Flash 5 Xilinx Virtex-4 FX100 s (DB-V4) (DB-V4) (DB-SPACE) (DB-SPACE) (DB-V4) (DB-V4) 12x Wire 2x Wizard, MIL, CAN, ADC/DAC 108x 16 GByte DDR2, 2 Gbit Flash 4 Xilinx Virtex-4 FX100 s (DB-SPACE) (DB-SPACE) (DB-V4) (DB-SPACE) (DB-SPACE) (DB-SPACE) 30x Wire 5x Wizard, MIL, CAN, ADC/DAC 270x 4 GByte DDR2, 5 Gbit Flash 1 Xilinx Virtex-4 FX100 22
23 Conclusion Scalable system architecture Number of s and faces New s (Xilinx Virtex-5 FX100T) New host interfaces (PCIe) Powerful communication infrastructure Reconfigurable at design time / inside s IP-core for - communication Partial run-time reconfiguration Homogeneous communication in PR region 400 MByte/s reconfiguration bandwidth Self-reconfiguration or reconfiguration via external interfaces Adaptive scrubbing with fast scrub rates EDK based design flow Easy IP-core reuse 23
24 Thank you for your attention! Jens Hagemeyer Cognitronics and Sensor Systems Center of Excellence Cognitive action Technology Bielefeld University, Germany
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