Intel Cyclone 10 LP FPGA Webinar

Transcription

1 Intel Cyclone 10 LP FPGA Webinar Uniquest Train the Trainer February 2018

2 Learn about Intel Cyclone 10 LP FPGA Intel s next generation low cost and low power FPGA Get hands on experience with hardware and software required to build an FPGA and run an embedded processor system Programmable Solutions Group Intel Confidential 2

3 Intel Cyclone 10 LP FPGA Webinar Agenda 10 minutes 1. Intel Cyclone 10 LP FPGA product & target applications 2. Overview of Intel Cyclone 10 LP FPGA evaluation kits 3. Device, SW and evaluation kit rollout status 1. My first FPGA design using Nios II 20 min 20 minutes Programmable Solutions Group Intel Confidential 3

4 Introduction to Intel Cyclone 10 LP FPGA Improved number of I/O / watt Up to 50% lower power Simplified power distribution network Saves board costs, board space, & design time Half the Power at Half the Cost (1) (1) As compared to previous generation Cyclone V family Programmable Solutions Group Intel Confidential 4

5 Intel Cyclone 10 LP FPGA Device Features Built on a 60 nm TSMC process technology Supports highly integrated, low power and efficient Empirion PowerSoCs Only requires two core power supplies Supports flexible and integrated Nios II processor Packages starting from 8x8 mm up to 29X29 mm Densities beginning from 6KLE up to 120 KLE Industrial & Automotive qualifications IEC 61508, AEC-Q100 Grade 2 Low cost and low risk proven technology Programmable Solutions Group Intel Confidential 5

6 Typical Intel Cyclone 10 LP FPGA - End Market and Applications Industrial IoT Medical Test & Measurement Automotive I/O Modules Interfacing Sensors Actuators Bridging Imaging Programmable Solutions Group Intel Confidential 6

7 Intel Cyclone 10 LP FPGA : Control Application Examples Market Trend: Abundance of evolving connectivity standards, impacts the scalability of: Static power System cost Sensor interfacing needs Voltage translation needs I/O Expansion System synchronization Enables a lower power, cost sensitive and flexible solution Programmable Solutions Group Intel Confidential 7

8 Intel Cyclone 10 LP FPGA : Motor Control Examples Market Trend: Need for greater integration and motor monitoring: Drive on a chip integration reduces system cost while increasing performance Scalable performance via more advanced control loops Functional safety growing in customer importance. Intel Cyclone 10 FPGA reduces overall cost of ownership Programmable Solutions Group Intel Confidential 8

9 Intel Cyclone 10 LP FPGA Dev Kit - 100% Powered by Enpirion USB_5V DC_5V EN5329QI 1.2V 2A VCCINT Intel Cyclone 10 LP FPGA Filter VCCD_PLL EP5358HUI 2.5V 0.6A VCCA EN5329QI 3.3V 2A VCCIO_3.3V EP5358HUI 1.8V 0.6A VCCIO_1.8V EP5358LUI VAR 0.6A VCCIO_VAR Power Tree for example reference only. Refer to FPGA Pin Connection Guidelines for exact sequencing requirements. Refer to FPGA datasheet for recommended operating conditions and voltage tolerances. Programmable Solutions Group Intel Confidential 9

10 Intel Cyclone 10 FPGA Silicon / Software / Kit Rollout- On Schedule 1Q2017 2Q2017 3Q2017 4Q2017 1Q2018 Cyclone 10 Advanced Information Brief & Pinouts Quartus Prime 17.0 Quartus Prime 17.1 GX Datasheets & Handbooks Cyclone 10 GX Dev Kit Shipping GX Silicon Rollout LP Datasheets & Handbooks LP Silicon Rollout Cyclone 10 LP Eval Kit Shipping Get started today Programmable Solutions Group Intel Confidential 10

11 Intel Cyclone 10 FPGA : Product Table Product Line 10CL006 10CL010 10CL016 10CL025 10CL040 10CL055 10CL080 10CL120 Logic Elements (LE) 6,000 10,000 16,000 25,000 40,000 55,000 80, ,000 M9K Memory Blocks Memory Block (Kb) ,134 2,340 2,745 3,888 18x18 Multipliers PLLs LVDS Channels (0.83 Gbps) Ball count, package size, ball pitch Package Options (number of I/O available) M164 (8X8 mm), 0.5 mm U256 (14x14 mm), 0.8 mm U484 (19x19 mm), 0.8 mm E144 (22x22 mm), 0.5 mm F484 (23x23 mm), 1.0 mm F780 (29x29 mm), 1.0 mm Programmable Solutions Group Intel Confidential 11

12 Hardware solutions and tools to enable technology evaluation and / or accelerate the customer design process Programmable Solutions Group Intel Confidential 12

13 Intel Cyclone 10 FPGA Board & Kit Introduction Cyclone 10 LP FPGA Evaluation kit I/O feature rich kit targeted at technology evaluation $99.95 price EK-10C025U256 Shipping September 2017 (1) Target Price (2) Open for bookings October 17 Programmable Solutions Group Intel Confidential 13

14 Intel Cyclone 10 LP FPGA Evaluation Kit - $99.95 Shipping Now Features: Intel Cyclone 10 LP 25KLE Intel MAX 10 System Manager Including USB Blaster II HyperRAM Ethernet 10/100/1000Mbps* Diligent PMOD connector Arduino Interface connector GPIO connector Push Buttons / DIP Switch's / Status LED s * Supported from Quartus Prime 17.1 onwards Programmable Solutions Group Intel Confidential 14

15 Intel Cyclone 10 LP FPGA Evaluation Kit JTAG Ethernet (1) 5 Volt Power (Optional) MAX 10 System Manager GPIO Header USB (Communications & Power) DIP Switches LED s Push Buttons Cyclone 10 LP HyperRAM Diligent PMOD Arduino (1) Supported from Quartus 17.1 onwards Programmable Solutions Group Intel Confidential 15

16 Use of Low-Pin-Count Memories When to use HyperRAM memories Where this is no requirement for DDR3/4 widths /speed Requires low access overhead Small footprint Target Market examples Automotive Clusters user settings Board Management fault logs Instrumentation data storage Embedded application storage Ideal EMIF devices for Cyclone 10 & MAX 10 FPGA s Programmable Solutions Group Intel Confidential 16

17 Advantages of HyperRAM? Controller IP FPGA (Cyclone 10 LP or MAX 10) P H Y IP Controller IP DRAM HyperRAM Item HyperRAM (1) DDR2 DDR3 # of pins 12 or 13 ~50 ~50 Controller IP size 400 LE s & 2x M9K s 6,000 LE s & 11x M9K s 6573 & 11x M9K s Licensing/ cost Synaptic Labs ($) PSG p/n = IP-SDRAM/HPDDR2 ($) PSG Altmemphy Performance 150 MHz (C10-LP) 167 MHz (CIV) 300 MHz (MAX10) Width x8 x4, x8, x16 x8, x16, x24 $0 Densities 64 Mb 128 Mb 256Mb (2017) 512 Mb 4 Gb 1 Gb 16 Gb (1) Synaptic L:abs soft IP core Programmable Solutions Group Intel Confidential 17

18 HyperBUS Memory Controller IP Synaptic Labs Supports HyperRAM & HyperFlash memories Low pin count 13 Low logic utilization Small packages 8x6mm Dual function Flash & Ram in same multi chip package variant available IP Core available as either Basic or Full versions OpenCore plus free evaluation licenses Licenses available direct from Synaptic Labs Request a license here Feature Basic Full Clock Speed (DDR) 100MHz 150MHz Device(s) 1x HyperRAM 2x HyperRAM or HyperFLASH LE Count M9K RAM Blks 0 2 Programmable Solutions Group Intel Confidential 18

19 Intel Cyclone 10 GX FPGA Development Board Features: 10CX220YF780E5G + Enpirion power MAX 10: USB blaster & BMC Memory DDR3: 2 GB 933 MHz Flash NOR Flash: 128 MB Interfaces FMC Connector PCIe Gen2 x4 USB 3.1 Gen2 Ethernet: 10G x2 Availability : December 2017 Programmable Solutions Group Intel Confidential 19

20 New Users Existing Users Demonstrate Ease of Use of FPGA by building and running an embedded system Demonstrate Intel Cyclone 10 FPGA device and board features Programmable Solutions Group Intel Confidential 20

21 Nios II Processor An overview TCM I-MEM CUSTOM INSTR I/F TCM D-MEM Add one or more embedded processors to FPGA design Royalty free, 32-bit RISC architecture, MHz (1), soft IP core, no external RAM or storage needed User-customizable processor Add or remove peripherals, as needed Support for real-time applications Configuration in under 10 ms Avionic, automotive & industrial compliant versions Extensive software ecosystem & support Cyclone 10 FPGA I$ D$ INT CNTRL JTAG DEBUG MMU HW BrkPt MPU Debug I & D TRACE EXCP CNTRL TRACE PORT (1) Dhrystones 2.1 benchmark (Intel Estimate) Programmable Solutions Group Intel Confidential 21

22 Flexible and integrated Nios II development flow Hardware Hardware Configuration HW Simulation Software System Information Configure & Integrate.sopcinfo Nios II SW enables ultimate system design flexibility and productivity SW Simulation Nios II Software Build Tools for Eclipse Compile & Debug Programmable Solutions Group Intel Confidential 22

23 My first FPGA design using Nios II processor Foundation Exercise Objective : 1. Demonstrate ease of use to a new user. New User 2. Build a Nios II processor based embedded hardware system, download it to the development board and run Hello world software program in C. Exercises : 1. Create basic Nios II Processor System using Qsys 2. Run Hello World on the Nios II Processor 3. Control LEDs from software SW/Tools requirements: 1. Quartus Prime Lite software v17.0 (or later) 2. Design files for exercises Programmable Solutions Group Intel Confidential 23

24 For more information go to altera.com and more Programmable Solutions Group Intel Confidential 24

25 Online Training Go to catalog and Filter on subject of interest, e.g. Nios II Online Courses Developing Software for the Nios II Processor: HAL Primer (OEMB1150) 20 Minutes Developing Software for the Nios II Processor: Nios II Software Build Tools for Eclipse (OEMB1128) 14 Minutes Nios II Software Build Tools for Eclipse and BSP Editor (Quartus II Software 10.0 Update) (ONSW1128) 26 Minutes Nios II Software Tools and Design Flow (ONIITOOLSDESIGN) 22 Minutes Using the MAX 10 User Flash Memory with the Nios II Processor (OMAXNIOS) 24 Minutes Using the Nios II Processor: Custom Components and Instructions (ONIICUS) 11 Minutes Using the Nios II Processor: Hardware Development (ONIIHW) 27 Minutes Using the Nios II Processor: Software Development (ONIISW) 10 Minutes Qsys II Online Courses Advanced System Design Using Qsys: Component & System Simulation (OAQSYSSIM) 28 Minutes Advanced System Design Using Qsys: Qsys System Optimization (OAQSYSOPT) 32 Minutes Advanced System Design Using Qsys: System Verification with System Console (OAQSYSSYSCON) 25 Minutes Advanced System Design Using Qsys: Utilizing Hierarchy in Qsys Designs (OAQSYSHIER) 22 Minutes Creating a System Design with Qsys (OQSYSCREATE) 37 Minutes Custom IP Development Using Avalon and AXI Interfaces (OQSYS3000) 113 Minutes Introduction to Qsys (OQSYS1000) 26 Minutes System Design with Qsys Pro (OQSYSPRO) 42 Minutes Programmable Solutions Group Intel Confidential 25

26 Intel Cyclone 10 - Design Examples Available Today Design Store Cyclone 10 LP FPGA Designs Evaluation Kit targeted 10 Designs Non targeted LP 4 Designs More designs added every day Programmable Solutions Group Intel Confidential 26

27 Intel is shipping Intel Cyclone 10 LP FPGA evaluation kits - Enabling the next generation of low cost and low power FPGA applications Intel Cyclone 10 FPGA Ease of programmability enables new FPGA users and gives time to market advantage to all FPGA users You can get started today! Programmable Solutions Group Intel Confidential 27

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30 Intel FPGA : application specific The right performance and features for the right application Cloud, datacenter, and HPC Management, Sensors and edge devices performance Vision systems, and purpose-built, application-specific hardware Scalable and efficient computing performance Datacenter / CSP Acceleration Board Management Edge Compute Machine Vision Embedded Vision Robotics Datacenter Networking Military / Defense ADAS 5G Wireless Infrastructure Network Communications Military / Defense I/O Expansion Automobile sensors, traffic sensors Infotainment, ADAS, telematics Copyright 2017, Intel Corporation. All rights reserved.

31 Cyclone 10 LP FPGA : Part Number Decoder Family Variant Core Voltage Y = Standard voltage - LP = 1.2V Z = Low Voltage* - LP = 1.0V Pin / Ball Count L : LP Family Signature 10C L 025 Y U 256 I 7 G αα Suffix (optional) 10C : Cyclone 10 αα : Special (optional) Logic Density 006 : 6K LE - smallest 120 : 120K LE - largest Package Type M : 0.5mm BGA U : 0.8mm BGA F : 1.0mm BGA E : 0.5mm EQFP Operating Temperature C : Commercial I : Industrial A : Automotive (Tj = 0 C to 85 C) (Tj = -40 C to 100 C) (Tj = -40 C to 125 C) FPGA Fabric Speed Grade 6 : Fastest 8 : Slowest Package Designation G : RoHS 6 P : Leaded (1) (1) Contact factory Programmable Solutions Group Intel Confidential 31

32 So what s in the Kit? Plastic clam shell packing Evaluation Board USB Cable Card insert with quick start instructions Web Based Quick Start Web page altera.com\lp Programmable Solutions Group Intel Confidential 32

33 Other low cost kits Intel Max 10 FPGA Evaluation Kit $49.95 Intel Max 10 FPGA Evaluation Kit 50 - $125 Intel Max 10 FPGA Evaluation Kit - $ Arrow BeMicro MAX 10 Evaluation Kit - $30 Arrow DECA MAX 10 Evaluation Kit - $65 Arrow MAX1000 Evaluation Kit - $29 Take advantage - Get started today with one of the many low cost development kits! Programmable Solutions Group Intel Confidential 33

34 Intel Cyclone 10 LP FPGA Evaluation Kit On Line Getting Started Programmable Solutions Group Intel Confidential 34

35 HyperRAM IP and Low Power Measurement Foundation Exercise Objective : 1. Demonstrate product features to new and existing users. 2. Become familiar with Qsys, Nios SBT and the Nios II HAL. New Users Existing Users Exercises : 1. Build a system with the Synaptic Labs Hyperbus controller 2. Test the HyperRAM and accessing peripherals from software 3. Measure the board power consumption using the MAX10 ADCs SW/Tools requirements: 1. Quartus Prime Lite software v17.0 (or later) 2. Design files for exercises Programmable Solutions Group Intel Confidential 35

36 Engineer-to-Engineer Videos More how to videos to get started today. w-to-videos.html Programmable Solutions Group Intel Confidential 36