COSC 243. Instruction Sets And Addressing Modes. Lecture 7&8 Instruction Sets and Addressing Modes. COSC 243 (Computer Architecture)

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1 COSC 243 Instruction Sets And Addressing Modes 1

2 Overview This Lecture Source Chapters 12 & 13 (10 th editition) Textbook uses x86 and ARM (we use 6502) Next 2 Lectures Assembly language programming 2

3 Stored Program Computer Address (A) Output Enable Write Enable Memory Data In (D) Data Out (Q) Data Out (Q) Data In (D) CPU PC IR Control Bus Command (X) Instruction X1 X0 A1 A0 3

4 Machine Code Recall that we programmed the computer by putting bit-patterns into the instruction. Those bit patterns determined the operations and memory locations to perform those operations upon Instruction X1 X0 A1 A0 We call programming in 1s and 0s in this way machine code programming It is extremely rare to have to do this, but important to understand what it is 4

5 MOS Technology 6502 CPU 5

6 Apple I, Apple ][, and Apple /// 1976 the Apple I 1977 the Apple ][ 1980 the Apple /// 6502 CPU computers Images from Wiklipedia 6

7 Other 6502 Machines Commodore 64 Nintendo Entertainment System BBC Micro 6502 CPU Computers Images from Wiklipedia 7

8 6502 Fibonacci 4C A2 10 A9 01 8D D D A9 31 8D 0F 00 8D 0F 00 AD D D D 0F 00 AD D AD D CA D0 E3 d=4c a210a9018d 10008D11008D1200A9318D0F008D0F00AD10006D11008D D0F00AD11008D1000AD12008D1100CAD0E3 8

9 Machine Code These numbers tell the computer what to do They tell the CPU to Assign values to registers Load registers from memory Add numbers to registers Store registers in memory And so on 9

10 Machine Code It is very difficult to program using numbers Programs are slow to enter Each individual bit must be chosen by the programmer The programs are not human readable Programs are long and tiresome to write Debugging is extremely difficult 10

11 Assembly Language 11

12 Assembly Language If we give mnemonics (names) to the numbers It is easier to remember them We can program symbolically We call this assembly language programming Each different CPU has its own mnemonics and its own assembly language (its own machine language) Assembly language programs are not portable across CPU architectures 12

13 Assembly Language Example Print a String (puts) Memory mapped ASCII output device at location $000F Strings are terminated with a $00 character Algorithm Start: Load a character Compare the character to $00 If equal exit this routine Write the character to address $000F Move on to the next character Go to start 13

14 Assembly Language Example ; pass the address of the string in X PRINT LDA $0000,X ; load A with the next char BEQ DONE ; if it was 0 then stop STA $000F ; write to the output device INX ; move on to the next char JMP PRINT ; and print that DONE RTS ; return from the subroutine 14

15 Assembly Language We can give names (labels) to memory locations In this case PRINT is the name of the memory location where the routine is stored. DONE is the name of the memory location where the return statement is stored There is a direct correspondence between mnemonic assembly language and machine code. An assembler translates from assembly to machine code, a disassembler translates from machine code to assembly language The assembler assigns absolute addresses to these labels 15

16 Assembly Language Listing Memory Location Label Assembly Machine Code 0016 PRINT 0016 LDA $0000,X BD BEQ DONE F B STA $000F 8D 0F E INX E8 001F JMP PRINT 4C DONE 0022 RTS 60 16

17 Instruction Set The set of all instructions for the particular CPU is called the instruction set It is determined by the designers (or micro-coded) Instructions consist of one or more fields The mnemonic opcodes E.g. Increment the X register (INX) And (optionally) parameters called operands E.g. Goto (JMP PRINT) Instructions are of different lengths RTS is one byte on the 6502 JMP PRINT is three bytes on the

18 Instruction Syntax Syntax <label> <opcode> <operands> ; <comment> Parameters # immediate $ hex value % binary 0 octal () use the target as a pointer Example Here STA $0F ; store A at memory location 0F (hex) 18

19 Programmer s Model The programmer s model of a computer is not the same as the hardware model. The hardware makes the computer look a particular way to the programmer 19

20 6502 Programmer s Model The computer has 64KB (2 16 Bytes) of memory The memory space or address space Each byte is numbered (from $0000 to $FFFF) All memory locations exist Some have special meaning (e.g. interrupts) $FFFA $FFFB : NMI $FFFC $FFFD : Reset $FFFE $FFFF : IRQ More on interrupts in an upcoming lecture... FFFF FFFE FFFD FFFC Memory

21 6502 Programmer s Model Memory space is divided into three chunks ROM RAM Memory Mapped I/O... More on this in upcoming lectures ROM from F000 upwards Memory Mapped I/O... FFFF FFFE FFFD FFFC RAM from E000 downwards Example memory map 21

22 6502 Programmer s Model The memory space is conceptually broken into chunks of 256 bytes each called pages. The first page is called zero-page (all addresses are of the form 00xx) The second page is called page 1 (all addresses are of the form 01xx), and so on If an address is of the form 00xx then the CPU can automatically put the 00 on the address bus. This makes the instruction shorter (and the decoding faster) 22

23 6502 Registers General purpose A, the 8 bit accumulator X, the 8 bit index register Y, the 8 bit index register Special purpose PC, the Program Counter S, the Stack pointer P, the Processor flags Bit number Accumulator (A) Index Register (X) Index Register (Y) Program Counter (PCH) Program Counter (PCL) 0 1 Stack Pointer (S) N V 1 B D I Z C P or flags 23

24 6502 Flags (P) The flags (P) hold the result of the previous operation We already know about the ripple-carry-adder Where does the final carry go? It goes into flag C Bit number N V 1 B D I Z C Flags Flag Meaning Flag Meaning C Carry (1=true) B BRK (1 = in BRK) Z Zero (1 = true) 1 Not used I IRQ (1 = disable) V Overflow (1 = true) D BCD (1 = true) N Negative (1 = neg) 24

25 The Stack You ll notice that the stack is a 16-bit address that starts 01. It is on page 1. Page 1 is reserved for the stack This is an unusual feature of the 6502, the stack is usually at the top of RAM (below the ROM) Like many CPUs, the 6502 stack grows downwards 25

26 Hello World HelloWorld.asm 2.org/JSSim/expert. html?loglevel=0&r=0 010&a=0010&d=A C C 6C6F00BD0000F00 78D0F00E84C1C00 60 * = $ LDX #STRING A JSR PRINT 20 1C RTS STRING 0016.BYTE $ BYTE $ BYTE $6C 6C 0019.BYTE $6C 6C 001A.BYTE $6F 6F 001B.BYTE $ C PRINT 001C LDA $0000,X BD F BEQ DONE F STA $000F 8D 0F INX E JMP PRINT 4C 1C DONE 0028 RTS 60 26

27 Procedure Calls In C we go X = "string"; print(x); But in assembly language we do it all by hand Either put the parameters into registers and then call Or push the parameters onto the stack and then call In helloword.asm we load the address of the string into X and then call print LDX #STRING JSR PRINT 27

28 Procedure Calls (JSR / RTS) JSR <address> push the return address onto the stack and call Store the value of PC + 2 at memory location S and S 1 Push the high byte then the low byte Subtract 2 from S Load PC with <address> RTS return to the caller Load PC with the value of S + 1 and S + 2 Add 2 to S Add 1 to PC 28

29 Procedure Calls (JSR / RTS) JSR (Jump to Subroutine) When this happens in helloworld.asm the stack pointer changes from $01FD to $01FB. At $01FC you ll notice the address of the instruction that caused the call ($0014). RTS (Return from Subroutine) When this happens in helloworld.asm you ll notice that the stack pointer changes back to $01FD and the program continues from where it left off. 29

30 JSR / RTS S B7 PC 0124 F EE 90 A9 01B9 01B8 01B7 01B6 01B5 01B4 What happens in a JSR $0436? Recall: push high, then push low What happens in the matching RTS? 30

31 Functional Groups Instructions exist for Data transfer Transfer data between registers or registers and memory Push and pull from the stack Data processing Arithmetic, logical, shift, operations Test and branch Check bits in the flag register and conditional jump Input / output Instructions that access the zero page OUT and IN instructions on x86 Control Interrupt handling 31

32 Instruction Mnemonics The instruction names usually make sense once you know them (just like the vi command set) LDA / LDX / LDY Load a value into the given register STA / STX / STY Store the value of the register back in memory TAX / TAY / TSX / TXA / TXS / TYA Transfer from one register to another (TAX: Transfer A to X) However, the hard part is the missing instructions There is no LDS or TSY. So to set the value of the S register its necessary to first load it into X and then transfer into S 32

33 Addressing Modes The 6502 has many more addressing modes than contemporary CPUs. It has 11 in total. Many of these are specializations of more general addressing modes Such as special zero-page addressing modes 33

34 Inherent These instructions don t take operands Useful to assign value of one register to another Examples include: TXS ; Transfer X to S 34

35 Immediate The value to use is specified as the operand Useful for loading constant values Examples include: LDX #$FF ; X = 255; LDX #$FF Immediate 35

36 Example VALUE = $10 *=$0000 LDA #$10 ADC #VALUE LOOP JMP LOOP 36

37 Direct (Absolute) Addressing The value is stored at the memory location specified in the operand Useful for accessing memory mapped I/O Examples include: LDX $FF ; X = value of memory location $FF LDX $FF Value Direct 00FF 00FE 00FD 37

38 Example *=$0000 JMP START VALUE.BYTE $20 START LDA #$10 ADC VALUE LOOP JMP LOOP 38

39 Zero Page Addressing Use a single-byte address only the first page (the first 256 bytes) of memory is accessible. This is faster, as only one byte needs to be looked up, and takes up less space in the assembled code as well. LDX $00FF -- works but uses an extra byte LDX $FF -- the zero page address 39

40 Relative Addressing The value is relative to here Must be used with conditional branch instructions Examples include: BCC HERE ; Branch to HERE if the carry is clear PC BCC value Value relative FF 00FE 00FD 40

41 Example *=$0000 LOOP BEQ LOOP BNE LOOP 41

42 Indexed Addressing The value to use is stored at the memory location that is the sum of the operands Useful for accessing stack-based parameters passed to a routine Examples include: LDY $311E,X ; Use memory location ($311E+X) X $10 LDY $311E,X Value Indexed F 312E 312D 312C 42

43 *=$0010 START LDA #$10 PHA JSR DOUBLE PLA OVER JMP OVER Example DOUBLE TSX LDA $0103,X ADC $0103,X STA $0103,X RTS We use $103 because $100 + X is the next free space on the stack. $101 and $102 store the return address, so $103 is the location of the parameter 43

44 Indirect Addressing The value is stored at the memory location specified at the memory location in the operand Can only be used in unconditional branch instructions The only example is: JMP ($31FE) ; Jump to where $31FE says we should go 3200 $31 31FF JMP ($31FE) $FC 31FE Indirect 31FD Here 31FC 44

45 Indexed Indirect Addressing The value is stored at the memory location specified at the memory location in the operand An example is: LDA ($80,X) ; Load A with where X bytes past $80 says X $0E LDA ($80,X) Indexed Indirect value $31 $FC 31FC 31FB 008F 008E 45

46 Indirect Indexed Addressing The value to use is stored at the memory location that is the sum of the register and the memory location at the memory location in the operand Examples include: LDA ($80),Y ; Y past where $80 says LDA ($80),Y Indirect indexed $31 $EC F 007E Y $10 Value 31FE 31FD 31FC 31FB 31FA 46

47 6502 Mnemonics Code Meaning Code Meaning Code Meaning Code Meaning ADC Add With Carry CLD Clear Decimal Flag JSR Jump Subroutine RTS Return From Subroutine AND Logical AND CLI Enable Interrupts LDA Load A SBC Subtract With Carry ASL Arithmetic Shift Left CLV Clear Overflow LDX Load X SEC Set Carry BCC Branch Carry Clear CMP Compare To A LDY Load Y SED Set BCD Mode BCS Branch Carry Set CPX Compare To X LSR Logical Shift Right SEI Disable Interrupts BEQ Branch Equal To Zero CPY Compare To Y NOP No Operation STA Store A BIT Bit Test DEC Decrement Memory ORA Logical Or STX Store X BMI Branch Minus DEX Decrement X PHA Push A STY Store Y BNE Branch Not Equal DEY Decrement Y PHP Push P TAX Transfer A To X BPL Branch Plus EOR Exclusive Or PLA Pull A TAY Transfer A To Y BRK Break INC Increment Memory PLP Pull P TSX Transfer S To X BVC Branch Overflow Clear INX Increment X ROL Rotate Left TXA Transfer X To A BVS Branch If Overflow INY Increment Y ROR Rotate Right TXS Transfer X To S CLC Clear Carry JMP Jump RTI Return From Interrupt TYA Transfer Y To A 47

48 Data Transfer Instructions Memory to registers LDA Load A LDX Load X LDY Load Y Register to memory STA Store A STX Store X STY Store Y Between registers TAX Transfer A to X TAY Transfer A to Y TSX Transfer S to X TXA Transfer X to A TXS Transfer X to S TYA Transfer Y to A Stack PHA Push A PHP Push P PLA Pull A PLP Pull P 48

49 Data Processing Instructions Arithmetic ADC Add with carry SBC Subtract with Carry DEC Decrement Memory DEX Decrement X DEY Decrement Y INC Increment Memory INX Increment X INY Increment Y Logic AND Logical AND ORA Logical OR EOR Exclusive OR Shifts ASL Arithmetic Shift Left LSR Logical Shift Right ROL Rotate Left ROR Rotate Right 49

50 Test and Branch Instructions Branches BCC Branch Carry Clear BCS Branch Carry Set BEQ Branch equal To Zero BNE Branch not equal to Zero BMI Branch Minus BPL Branch Plus BVC Branch Overflow Clear BVS Branch If Overflow Jumps JMP Jump JSR Jump Subroutine RTS Return from Subroutine Comparisons (these only change the P (flags) register) BIT AND memory with accumulator, zero flag updated CMP Compare to A CPX Compare to X CPY Compare to Y 50

51 Input and Output Instructions Input and output Many instructions have addressing modes that provide fast access to the zero page Often memory mapped I/O is on the zero page for fast access 51

52 Control Instructions Control CLC Clear Carry SEC Set Carry CLD Clear Decimal Flag SED Set BCD Mode CLV Clear Overflow CLI Enable Interrupts SEI Disable Interrupts Misc BRK Break NOP No Operation RTI Return from Interrupt 52

The 6502 Instruction Set

The 6502 Instruction Set Load and Store Group LDA Load Accumulator N,Z LDX Load X Register N,Z LDY Load Y Register N,Z STA Store Accumulator STX Store X Register STY Store Y Register Arithmetic Group ADC