OSIAC Read OSIAC 5362 posted on the course website
|
|
- Shonda Carroll
- 5 years ago
- Views:
Transcription
1 OSIAC 5362 Read OSIAC 5362 posted on the course website
2 The Basic Structure of Control Unit m CLK Run/Inhibit Control Step Counter m Preset (to any new state) Reset IR Decoder/Encoder (combinational logic) Status Flag Condition Codes Control Signals mostly data transfers between registers
3 OSIAC 5362 In the following lectures, we will cover a new processor OSIAC 5362 developed by The Ohio State University We will develop the control unit for the OSIAC 5362 Write the microinstructions to implement the instruction set with associated addressing modes We will compare the instructions and addressing modes with the example computer because many are similar
4 Register Structure of OSIAC 5362 There are four registers R AC: Accumulator R1 X: Index register R2 SP: System stack pointer R3 PC: Program counter Also 4 condition code bits C V Z N Carry out, Overflow, Zero, Negative
5 Organized as 16-bit words Not byte addressable No long words One or more words long Operands and Addresses Instruction Types - Opcode word + others needed by addressing mode Four types Double operand Single operand Branch instruction Special instruction
6 Addressing Modes Seven basic addressing modes similar to the example machines Mode Name Assembler Syntax Operand* 0 Register Rk [Rk] 1 Register Indirect (Rk) [[Rk]] 2 Autoincrement (Rk)+ [[Rk]] then [Rk] + 1 Rk 3 Autodecrement -(Rk) [Rk] 1 Rk then [[Rk]] 4 Index n(rk) [n+[rk]] 5 Absolute n [n] 6 Immediate #n n * Operand is for arithmetic instructions. JUMP type instruction use is for effective address (EA).
7 Instructions Double operand instructions - 4 bit opcode - Instruction defines src and dst (2 operands) - There are addressing fields for each operand: 4 bits (mode) + 2 bits (register number) OP2 SAD DAD S D OP2: op code SAD: source addressing mode DAD: destination addressing mode S: source register number D: destination register number ADD (op code = 1), SUB (=2), MOVE (=3), EXG (=4), OR (=5), AND (=6) Condition codes set accordingly
8 Use of Condition Code C for Borrow in Subtract Operations Example No borrow (-7) Computer does (2 s complement addition) Carry out is not set in subtraction C = 0 Needs borrow (-7) Carry out is set in subtraction C = 1
9 Single operand instructions Instructions (continued) - 4 bit opcode in bits Instruction defines dst only (1 operand) - There is one addressing field for the operand: 4 bits (mode) + 2 bits (register number) OP1: op code 0000 OP1 DAD XX D DAD: destination addressing mode D: destination register number CLR (op code = 1), INC (=2), DEC (=3), NEG (=4), COM (=5), JMP (=6), JSR (=7), TST (=8) Condition codes set There are 8 instructions accordingly - NEG gets 2 s complement - JMP and JSR both EA(dst) PC, JSR also stores the returning address in STACK
10 Instructions (continued) Branch Instructions e.g. BEQ (2 words) Uses relative address (branch relative to where you are) Offset = 2 nd word First Word A branch occurs if the following expression is true Second Word IR5 [IR3 (IR4 C) + IR2 (IR4 V) + IR1 (IR4 Z) + IR0 (IR4 N)] PCUPD = PCoriginal + 2, [PCUPD] + Offset PC Special Instructions I S/C CVZN Offset Return from subroutine RTS, opcode = $0080 [[SP]] PC, [SP]+1 SP Set/Clear Condition Codes, opcode = S/C CVZN HALT halt, opcode = $
11 Condition Codes Make sense of the condition codes can an operation cause a condition change? AND, OR, MOVE cannot get a carry or overflow ADD, SUB all CC s can change INC, DEC like ADD and SUB #1, all can change TST cannot cause carry or overflow, N, Z, possible CLR only Z=1; N=0, V=0, C=0 JMP, JSR not moving/operating on data, none of CC s is affected
12 Condition Branch Bits marked C, V, Z, N set to 1 if that is the condition to test (most often just one at a time) Bit 4 S/C 1 test if condition is set 0 test if condition is clear Bit 5 Invert inverts the sense of everything tested to decide whether or not to branch generally 0
13 Opcodes for Branch Instructions IR5 IR4 IR3 IR2 IR1 IR0 Opcode (I) (S/C) (C) (V) (Z) (N) BEQ (equal) $0092 IR1 (IR4 Z)=Z BNE (not equal) $0082 = Z BPL (plus) $0081 IR0 (IR4 N) =N BMI (minus) $0091 = N BLS(low/same) $009A IR3 (IR4 C) +IR1 (IR4 Z) = C+Z BHI (high) $00BA = C+Z
14 Addressing Modes Allowed Each instruction is allowed different addressing modes ADD: s source from anywhere d immediate would not make sense AND: something you do to data, not to address Bcc: relative addressing which is just n(pc) JMP: operand is EA (where jump to)
Grundlagen Microcontroller Processor Core. Günther Gridling Bettina Weiss
Grundlagen Microcontroller Processor Core Günther Gridling Bettina Weiss 1 Processor Core Architecture Instruction Set Lecture Overview 2 Processor Core Architecture Computes things > ALU (Arithmetic Logic
More informationCSIS1120A. 10. Instruction Set & Addressing Mode. CSIS1120A 10. Instruction Set & Addressing Mode 1
CSIS1120A 10. Instruction Set & Addressing Mode CSIS1120A 10. Instruction Set & Addressing Mode 1 Elements of a Machine Instruction Operation Code specifies the operation to be performed, e.g. ADD, SUB
More informationCOSC 243. Instruction Sets And Addressing Modes. Lecture 7&8 Instruction Sets and Addressing Modes. COSC 243 (Computer Architecture)
COSC 243 Instruction Sets And Addressing Modes 1 Overview This Lecture Source Chapters 12 & 13 (10 th editition) Textbook uses x86 and ARM (we use 6502) Next 2 Lectures Assembly language programming 2
More informationEE 3170 Microcontroller Applications
Lecture Overview EE 3170 Microcontroller Applications Lecture 7 : Instruction Subset & Machine Language: Conditions & Branches in Motorola 68HC11 - Miller 2.2 & 2.3 & 2.4 Based on slides for ECE3170 by
More informationThe 6502 Instruction Set
The 6502 Instruction Set Load and Store Group LDA Load Accumulator N,Z LDX Load X Register N,Z LDY Load Y Register N,Z STA Store Accumulator STX Store X Register STY Store Y Register Arithmetic Group ADC
More informationinstruction 1 Fri Oct 13 13:05:
instruction Fri Oct :0:0. Introduction SECTION INSTRUCTION SET This section describes the aressing modes and instruction types.. Aressing Modes The CPU uses eight aressing modes for flexibility in accessing
More informationThe Assembly Language of the Boz 5
The Assembly Language of the Boz 5 The Boz 5 uses bits 31 27 of the IR as a five bit opcode. Of the possible 32 opcodes, only 26 are implemented. Op-Code Mnemonic Description 00000 HLT Halt the Computer
More informationComputer Organization II CMSC 3833 Lecture 33
Term MARIE Definition Machine Architecture that is Really Intuitive and Easy 4.8.1 The Architecture Figure s Architecture Characteristics: Binary, two s complement Stored program, fixed word length Word
More informationMicrocontroller Intel [Instruction Set]
Microcontroller Intel 8051 [Instruction Set] Structure of Assembly Language [ label: ] mnemonic [operands] [ ;comment ] Example: MOV R1, #25H ; load data 25H into R1 2 8051 Assembly Language Registers
More informationChapter 3 Machine Instructions & Programs. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 3 Machine Instructions & Programs Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Numbers, Arithmetic Operations, and Characters Memory Locations
More informationDisassembly of MC9S12 op codes Decimal, Hexadecimal and Binary Numbers
Disassembly of MC9S12 op codes Decimal, Hexadecimal and Binary Numbers o How to disassemble an MC9S12 instruction sequence o Binary numbers are a code and represent what the programmer intends for the
More informationDisassembly of MC9S12 op codes Decimal, Hexadecimal and Binary Numbers
Disassembly of MC9S12 op codes Decimal, Hexadecimal and Binary Numbers o How to disassemble an MC9S12 instruction sequence o Binary numbers are a code and represent what the programmer intends for the
More informationH8/300L Series Programming Manual
H8/300L Series Programming Manual Notice When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved:
More information2. ADDRESSING METHODS
2 Addressing Methods STUDY MATERIALS ON COMPUTER ORGANIZATION (As per the curriculum of Third semester BSc Electronics of Mahatma Gandh Uniiversity) Compiled by Sam Kollannore U Lecturer in Electronics
More informationTYPES OF INTERRUPTS: -
There are 3 types of interrupts. TYPES OF INTERRUPTS: - External Interrupts. Internal Interrupts. Software interrupts. Hardware Interrupts (1) External interrupts come from I/O devices, from a timing device
More informationINSTRUCTION SET OF 8085
INSTRUCTION SET OF 8085 Instruction Set of 8085 An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions that a microprocessor
More informationINTRODUCTION TO BRANCHING. There are two forms of unconditional branching in the MC68000.
INTRODUCTION TO BRANCHING UNCONDITIONAL BRANCHING There are two forms of unconditional branching in the MC68000. BRA instruction BRA Program control passes directly to the instruction located at
More informationMOS 6502 Architecture
MOS 6502 Architecture Lecture 3 Fall 17 1 History Origins lie in the Motorola 6800. Was very expensive for consumers. ($300, or about $1500 in 2017 $s) Chuck Peddle proposes lower-cost, lower-area 6800
More information2. Arithmetic Instructions addition, subtraction, multiplication, divison (HCS12 Core Users Guide, Sections 4.3.4, and ).
AS12 Assembler Directives A Summary of 9S12 instructions Disassembly of 9S12 op codes Huang Section 1.8, Chapter 2 MC9S12 V1.5 Core User Guide Version 1.2, Section 12 o A labels is a name assigned the
More information8085 INSTRUCTION SET INSTRUCTION DETAILS
8085 INSTRUCTION SET INSTRUCTION DETAILS DATA TRANSFER INSTRUCTIONS MOV Rd, Rs Copy from source to destination This instruction copies the contents of the source register Rs into the destination register
More informationSCRAM Introduction. Philipp Koehn. 19 February 2018
SCRAM Introduction Philipp Koehn 19 February 2018 This eek 1 Fully work through a computer circuit assembly code Simple but Complete Random Access Machine (SCRAM) every instruction is 8 bit 4 bit for op-code:
More informationLecture 6 Assembly Programming: Branch & Iteration
CPE 390: Microprocessor Systems Spring 2018 Lecture 6 Assembly Programming: Branch & Iteration Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ
More informationInstruction Set Instruction set of 8085 can be classified in following groups: Data Transfer Instructions These instructions can perform data transfer operations between Registers of 8085 e.g. MOV 8085
More informationEE 3170 Microcontroller Applications
Q. 3.9 of HW3 EE 37 Microcontroller Applications (a) (c) (b) (d) Midterm Review: Miller Chapter -3 -The Stuff That Might Be On the Exam D67 (e) (g) (h) CEC23 (i) (f) (j) (k) (l) (m) EE37/CC/Lecture-Review
More informationLecture 5: Computer Organization Instruction Execution. Computer Organization Block Diagram. Components. General Purpose Registers.
Lecture 5: Computer Organization Instruction Execution Computer Organization Addressing Buses Fetch-Execute Cycle Computer Organization CPU Control Unit U Input Output Memory Components Control Unit fetches
More informationARM Assembly Language. Programming
Outline: ARM Assembly Language the ARM instruction set writing simple programs examples Programming hands-on: writing simple ARM assembly programs 2005 PEVE IT Unit ARM System Design ARM assembly language
More information(2) Explain the addressing mode of OR What do you mean by addressing mode? Explain diff. addressing mode for 8085 with examples.
(1) Explain instruction format and Opcode format of 8085 μp with example. OR With help of examples, explain the formation of opcodes of 8085 OR What is an instruction? List type of instruction based on
More informationECE331 Handout 3- ASM Instructions, Address Modes and Directives
ECE331 Handout 3- ASM Instructions, Address Modes and Directives ASM Instructions Functional Instruction Groups Data Transfer/Manipulation Arithmetic Logic & Bit Operations Data Test Branch Function Call
More informationLecture 04: Machine Instructions
CSCI2510 Computer Organization Lecture 04: Machine Instructions Ming-Chang YANG mcyang@cse.cuhk.edu.hk Reading: Chap. 2.3~2.4, 2.10~2.11 Recall: Instructions & Program A computer is governed by instructions.
More informationIA-32 architecture. PDP8/e architecture Arithmetic. IA-32 architecture (cont)
PDP8/e architecture Arithmetic CS207, Fall 2004 September 27, 2004 1 IA-32 architecture 20-year development cycle (!) First version: 8086 architecture (16-bit), 1978 Moved to 32-bit in 1985 (80386) Now:
More informationCHAPTER 8: Central Processing Unit (CPU)
CS 224: Computer Organization S.KHABET CHAPTER 8: Central Processing Unit (CPU) Outline Introduction General Register Organization Stack Organization Instruction Formats Addressing Modes 1 Major Components
More informationMicroprocessors 1. The 8051 Instruction Set. Microprocessors 1 1. Msc. Ivan A. Escobar Broitman
Microprocessors 1 The 8051 Instruction Set Microprocessors 1 1 Instruction Groups The 8051 has 255 instructions Every 8-bit opcode from 00 to FF is used except for A5. The instructions are grouped into
More informationINSTRUCTION SET AND EXECUTION
SECTION 6 INSTRUCTION SET AND EXECUTION Fetch F1 F2 F3 F3e F4 F5 F6 Decode D1 D2 D3 D3e D4 D5 Execute E1 E2 E3 E3e E4 Instruction Cycle: 1 2 3 4 5 6 7 MOTOROLA INSTRUCTION SET AND EXECUTION 6-1 SECTION
More informationProgramming. A. Assembly Language Programming. A.1 Machine Code. Machine Code Example: Motorola ADD
A. Assembly Language Programming Programming of a computer system: Machine code direct execution Assembly language tool: assembler High level programming language tool: interpreter tool: compiler Programming
More informationProgramming the Motorola MC68HC11 Microcontroller
Programming the Motorola MC68HC11 Microcontroller COMMON PROGRAM INSTRUCTIONS WITH EXAMPLES aba Add register B to register A Similar commands are abx aby aba add the value in register B to the value in
More informationUnsigned Binary Integers
Unsigned Binary Integers Given an n-bit number x x n 1 n 2 1 0 n 12 xn 22 x12 x02 Range: 0 to +2 n 1 Example 2.4 Signed and Unsigned Numbers 0000 0000 0000 0000 0000 0000 0000 1011 2 = 0 + + 1 2 3 + 0
More informationAssembly Language Programming of 8085
Assembly Language Programming of 8085 Topics 1. Introduction 2. Programming model of 8085 3. Instruction set of 8085 4. Example Programs 5. Addressing modes of 8085 6. Instruction & Data Formats of 8085
More informationUnsigned Binary Integers
Unsigned Binary Integers Given an n-bit number x x n 1 n 2 1 0 n 12 xn 22 x12 x02 Range: 0 to +2 n 1 Example 2.4 Signed and Unsigned Numbers 0000 0000 0000 0000 0000 0000 0000 1011 2 = 0 + + 1 2 3 + 0
More informationLC-3 Instruction Set Architecture. Textbook Chapter 5
LC-3 Instruction Set Architecture Textbook Chapter 5 Instruction set architecture What is an instruction set architecture (ISA)? It is all of the programmer-visible components and operations of the computer
More informationMotorola 6809 and Hitachi 6309 Programmer s Reference
Motorola 6809 and Hitachi 6309 Programmer s Reference 2009 by Darren Atkinson A note about cycle counts The MPU cycle counts listed throughout this document will sometimes show two different values separated
More informationCPU Design John D. Carpinelli, All Rights Reserved 1
CPU Design 1997 John D. Carpinelli, All Rights Reserved 1 Outline Register organization ALU design Stacks Instruction formats and types Addressing modes 1997 John D. Carpinelli, All Rights Reserved 2 We
More informationBasic Processor Design
Basic Processor Design Design Instruction Set Design Datapath Design Control Unit This lecture deals with Instruction Set Design. 1001 Instruction Set Terminology Mnemonic (Instruction Name) SUBI Syntax
More informationTable 1: Mnemonics Operations Dictionary. Add Accumulators Add B to Y. Add with carry to B. Add Memory to B. Add 16-bit to D And B with Memory
Table 1: Mnemonics s Dictionary ABA ABX ABY ADCA ADCB ADDA ADDB ADDD ANDA ANDB ASL ASLA ASLB ASLD ASR ASRA ASRB BCC BCLR BCS BEQ BGE BGT BHI BHS BITA BITB BLE BLO BLS BLT Add Accumulators Add B to X Add
More informationAssembly Language Programming of 8085
Assembly Language Programming of 8085 1. Introduction A microprocessor executes instructions given by the user Instructions should be in a language known to the microprocessor Microprocessor understands
More informationRegarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi
More informationMark II Aiken Relay Calculator
Introduction to Embedded Microcomputer Systems Lecture 6.1 Mark II Aiken Relay Calculator 2.12. Tutorial 2. Arithmetic and logical operations format descriptions examples h 8-bit unsigned hexadecimal $00
More informationComputer Science and Engineering 331. Midterm Examination #1. Fall Name: Solutions S.S.#:
Computer Science and Engineering 331 Midterm Examination #1 Fall 2000 Name: Solutions S.S.#: 1 41 2 13 3 18 4 28 Total 100 Instructions: This exam contains 4 questions. It is closed book and notes. Calculators
More informationIntroduction to Computer. Chapter 5 The LC-3. Instruction Set Architecture
Introduction to Computer Engineering ECE/CS 252, Fall 2010 Prof. Mikko Lipasti Department of Electrical and Computer Engineering University of Wisconsin Madison Chapter 5 The LC-3 Instruction Set Architecture
More informationA. CPU INSTRUCTION SET SUMMARY
A. CPU INSTRUCTION SET SUMMARY This appendix summarizes the CPU instruction set. Table A-1 is a matrix of CPU instructions and addressing modes arranged by operation code. Table A-2 lists the CPU instruction
More informationLevels of Programming. Registers
Levels of Programming COSC 2021: Computer Organization Instructor: Dr. Amir Asif Department of Computer Science York University Handout # 3: MIPS Instruction Set I Topics: 1. Arithmetic Instructions 2.
More informationFaculty of Engineering Systems & Biomedical Dept. First Year Cairo University Sheet 6 Computer I
aculty of Engineering Systems & Biomedical Dept. irst Year Cairo University Sheet 6 Computer I 1. Choose rue or alse for each of the following statements a) In a direct addressing mode instruction, the
More informationH8/500 Series Programming Manual
H8/500 Series Programming Manual Catalog No. ADE-602-021 Preface The H8/500 Family of Hitachi-original microcontrollers is built around a 16-bit CPU core that offers enhanced speed and a large address
More informationHomework 2. Lecture 6: Machine Code. Instruction Formats for HW2. Two parts: How to do Homework 2!!!!
Lecture 6: Machine How to do Homework 2!!!! Homework 2 Two parts: Part 1: Use Debug to enter and run a simple machine code program convert input data into 2 s complement hex enter data at the correct address
More informationCourse Administration
Fall 2017 EE 3613: Computer Organization Chapter 2: Instruction Set Architecture 2/4 Avinash Kodi Department of Electrical Engineering & Computer Science Ohio University, Athens, Ohio 45701 E-mail: kodi@ohio.edu
More information9/25/ Software & Hardware Architecture
8086 Software & Hardware Architecture 1 INTRODUCTION It is a multipurpose programmable clock drive register based integrated electronic device, that reads binary instructions from a storage device called
More informationCISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization
CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationComputer Architecture
Computer Architecture Lecture 1: Digital logic circuits The digital computer is a digital system that performs various computational tasks. Digital computers use the binary number system, which has two
More informationCode segment Stack segment
Registers Most of the registers contain data/instruction offsets within 64 KB memory segment. There are four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1
More information... Executing conditional instructions
1 2 Executing conditional instructions Our design to this point has been the SISD (single instruction single data) architecture This is fine if we wish to execute in a purely sequential mode We now wish
More informationEE 3170 Microcontroller Applications
EE 37 Microcontroller Applications Lecture 8: Instruction Subset & Machine Language: A Brief Tour of the 68HC Instruction Set - Miller 2.4 & 5.2-5.3 & Appendix A Based on slides for ECE37 by Profs. Davis,
More informationSTEVEN R. BAGLEY ARM: PROCESSING DATA
STEVEN R. BAGLEY ARM: PROCESSING DATA INTRODUCTION CPU gets instructions from the computer s memory Each instruction is encoded as a binary pattern (an opcode) Assembly language developed as a human readable
More informationTHE MICROPROCESSOR Von Neumann s Architecture Model
THE ICROPROCESSOR Von Neumann s Architecture odel Input/Output unit Provides instructions and data emory unit Stores both instructions and data Arithmetic and logic unit Processes everything Control unit
More informationContents 8051 Instruction Set BY D. BALAKRISHNA, Research Assistant, IIIT-H Chapter I : Control Transfer Instructions Lesson (a): Loop Lesson (b): Jump (i) Conditional Lesson (c): Lesson (d): Lesson (e):
More informationCISC 662 Graduate Computer Architecture. Lecture 4 - ISA
CISC 662 Graduate Computer Architecture Lecture 4 - ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationA First Look at Microprocessors
A First Look at Microprocessors using the The General Prototype Computer (GPC) model Part 2 Can you identify an opcode to: Decrement the contents of R1, and store the result in R5? Invert the contents
More informationDepartment of Computer and Mathematical Sciences. Lab 4: Introduction to MARIE
Department of Computer and Mathematical Sciences CS 3401 Assembly Language 4 Lab 4: Introduction to MARIE Objectives: The main objective of this lab is to get you familiarized with MARIE a simple computer
More information10-1 C D Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e
10-1 C D E A B 10-2 A B A B C (A B) C D A A B (A B) C E D (A B) C D E (A B) C + D E (A B) C 10-3 Opcode Mode Address or operand 10-4 Memory 250 Opcode Mode PC = 250 251 ADRS 252 Next instruction ACC Opcode:
More informationCPE 323 MSP430 INSTRUCTION SET ARCHITECTURE (ISA)
CPE 323 MSP430 INSTRUCTION SET ARCHITECTURE (ISA) Aleksandar Milenković Email: milenka@uah.edu Web: http://www.ece.uah.edu/~milenka Objective Introduce MSP430 Instruction Set Architecture (Class of ISA,
More informationChapter. Computer Architecture
Chapter 4 Computer Architecture Figure 4.1 Input device Central processing unit Main memory Output device Bus Data flow Control Figure 4.2 Central processing unit () Status bits ( ) Accumulator ( ) Index
More information20/08/14. Computer Systems 1. Instruction Processing: FETCH. Instruction Processing: DECODE
Computer Science 210 Computer Systems 1 Lecture 11 The Instruction Cycle Ch. 5: The LC-3 ISA Credits: McGraw-Hill slides prepared by Gregory T. Byrd, North Carolina State University Instruction Processing:
More informationThe PAW Architecture Reference Manual
The PAW Architecture Reference Manual by Hansen Zhang For COS375/ELE375 Princeton University Last Update: 20 September 2015! 1. Introduction The PAW architecture is a simple architecture designed to be
More information8051 Overview and Instruction Set
8051 Overview and Instruction Set Curtis A. Nelson Engr 355 1 Microprocessors vs. Microcontrollers Microprocessors are single-chip CPUs used in microcomputers Microcontrollers and microprocessors are different
More informationNotes: The Marie Simulator
The Accumulator (AC) is the register where calculations are performed. To add two numbers together, a) load the first number into the accumulator with a Load instruction b) Add the second number to the
More informationAccumulator and memory instructions 1. Loads, stores, and transfers 2. Arithmetic operations 3. Multiply and divide 4. Logical operations 5. Data test
HC11 Instruction Set Instruction classes 1. 2. 3. 4. Accumulator and Memory Stack and Index Register Condition Code Register Program control instructions 2 1 Accumulator and memory instructions 1. Loads,
More informationMC9S12 Assembler Directives A Summary of MC9S12 Instructions Disassembly of MC9S12 op codes. Summary of HCS12 addressing modes ADDRESSING MODES
MC9S12 Assembler Directives A Summary of MC9S12 Instructions Disassembly of MC9S12 op codes o Review of Addressing Modes o Which branch instruction to use (signed vs unsigned) o Using X and Y registers
More informationIntroduction to Embedded Microcomputer Systems Lecture 8.1. Computers in the future may weigh no more than 1.5 tons Popular Science, 1949
Introduction to Embedded Microcomputer Systems Lecture 8.1 Computers in the future may weigh no more than 1.5 tons Popular Science, 1949 Recap Debugging: Monitor, dump TExaS Real 9S12DG Overview Addition
More informationECE232: Hardware Organization and Design
ECE232: Hardware Organization and Design Lecture 4: Logic Operations and Introduction to Conditionals Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Overview Previously examined
More informationCS401 - Computer Architecture and Assembly Language Programming Glossary By
CS401 - Computer Architecture and Assembly Language Programming Glossary By absolute address : A virtual (not physical) address within the process address space that is computed as an absolute number.
More informationCHAPTER ASSEMBLY LANGUAGE PROGRAMMING
CHAPTER 2 8051 ASSEMBLY LANGUAGE PROGRAMMING Registers Register are used to store information temporarily: A byte of data to be processed An address pointing to the data to be fetched The vast majority
More informationLC-3 Instruction Set Architecture
CMPE12 Notes LC-3 Instruction Set Architecture (Textbookʼs Chapter 5 and 6)# Instruction Set Architecture# ISA is all of the programmer-visible components and operations of the computer.# memory organization#
More information68000 Instruction Set (2) 9/20/6 Lecture 3 - Instruction Set - Al 1
68000 Instruction Set (2) 9/20/6 Lecture 3 - Instruction Set - Al 1 Lecture Overview The 68000 Instruction Set continued The understand and effectively use an architecture must understand the register
More informationME 4447/6405. Microprocessor Control of Manufacturing Systems and Introduction to Mechatronics. Instructor: Professor Charles Ume LECTURE 6
ME 4447/6405 Microprocessor Control of Manufacturing Systems and Introduction to Mechatronics Instructor: Professor Charles Ume LECTURE 6 MC9S12C Microcontroller Covered in Lecture 5: Quick Introduction
More informationCN310 Microprocessor Systems Design
CN310 Microprocessor Systems Design Instruction Set (AVR) Nawin Somyat Department of Electrical and Computer Engineering Thammasat University Outline Course Contents 1 Introduction 2 Simple Computer 3
More informationEXPERIMENT NO. 1 THE MKT 8085 MICROPROCESSOR TRAINER
OBJECT: EXPERIMENT NO. 1 THE MKT 8085 MICROPROCESSOR TRAINER To understand the structure and operating instruction of the microprocessor trainer. INTRODUCTION: The MKT 8085 is a single-board microcomputer,
More informationLecture 11: Control Unit and Instruction Encoding
CSCI25 Computer Organization Lecture : Control Unit and Instruction Encoding Ming-Chang YANG mcyang@cse.cuhk.edu.hk Reading: Chap. 7.4~7.5 (5 th Ed.) Recall: Components of a Processor Register file: a
More informationComputer System Architecture
CSC 203 1.5 Computer System Architecture Department of Statistics and Computer Science University of Sri Jayewardenepura Addressing 2 Addressing Subject of specifying where the operands (addresses) are
More informationSN8F5000 Family Instruction Set
SONiX Technology Co., Ltd. 8051-based Microcontroller 1 Overview SN8F5000 is 8051 Flash Type microcontroller supports comprehensive assembly instructions and which are fully compatible with standard 8051.
More informationChapter 2 Instruction Set Architecture
Chapter 2 Instruction Set Architecture Course Outcome (CO) - CO2 Describe the architecture and organization of computer systems Program Outcome (PO) PO1 Apply knowledge of mathematics, science and engineering
More informationChapter 7 Central Processor Unit (S08CPUV2)
Chapter 7 Central Processor Unit (S08CPUV2) 7.1 Introduction This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more
More informationProcessing Unit CS206T
Processing Unit CS206T Microprocessors The density of elements on processor chips continued to rise More and more elements were placed on each chip so that fewer and fewer chips were needed to construct
More informationA3 Computer Architecture
A3 Computer Architecture Engineering Science 3rd year A3 Lectures Prof David Murray david.murray@eng.ox.ac.uk www.robots.ox.ac.uk/ dwm/courses/3co Michaelmas 2000 1 / 1 2: Introduction to the CPU 3A3 Michaelmas
More informationInstructions: Language of the Computer
CS359: Computer Architecture Instructions: Language of the Computer Yanyan Shen Department of Computer Science and Engineering 1 The Language a Computer Understands Word a computer understands: instruction
More informationEE 361 University of Hawaii Fall
C functions Road Map Computation flow Implementation using MIPS instructions Useful new instructions Addressing modes Stack data structure 1 EE 361 University of Hawaii Implementation of C functions and
More informationComputer Architecture Prof. Mainak Chaudhuri Department of Computer Science & Engineering Indian Institute of Technology, Kanpur
Computer Architecture Prof. Mainak Chaudhuri Department of Computer Science & Engineering Indian Institute of Technology, Kanpur Lecture - 7 Case study with MIPS-I So, we were discussing (Refer Time: 00:20),
More informationMath 230 Assembly Programming (AKA Computer Organization) Spring 2008
Math 230 Assembly Programming (AKA Computer Organization) Spring 2008 MIPS Intro II Lect 10 Feb 15, 2008 Adapted from slides developed for: Mary J. Irwin PSU CSE331 Dave Patterson s UCB CS152 M230 L10.1
More informationQ. Classify the instruction set of 8051 and list out the instructions in each type.
INTRODUCTION Here is a list of the operands and their meanings: A - accumulator; Rn - is one of working registers (R0-R7) in the currently active RAM memory bank; Direct - is any 8-bit address register
More informationAssembler. Lecture 8 CS301
Assembler Lecture 8 CS301 Discussion Given the following function header, int foo(int a, int b); what will be on the stack before any of the calculations in foo are performed? Assume foo() calls some other
More informationbits 5..0 the sub-function of opcode 0, 32 for the add instruction
CS2 Computer Systems note 1a Some MIPS instructions More details on these, and other instructions in the MIPS instruction set, can be found in Chapter 3 of Patterson and Hennessy. A full listing of MIPS
More informationModule 5 - CPU Design
Module 5 - CPU Design Lecture 1 - Introduction to CPU The operation or task that must perform by CPU is: Fetch Instruction: The CPU reads an instruction from memory. Interpret Instruction: The instruction
More informationInstruction Sets: Characteristics and Functions Addressing Modes
Instruction Sets: Characteristics and Functions Addressing Modes Chapters 10 and 11, William Stallings Computer Organization and Architecture 7 th Edition What is an Instruction Set? The complete collection
More information