Chapter. Computer Architecture

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Hector McKenzie
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1 Chapter 4 Computer Architecture

2 Figure 4.1 Input device Central processing unit Main memory Output device Bus Data flow Control

3 Figure 4.2 Central processing unit () Status bits ( ) Accumulator ( ) Index register ( ) Program counter ( ) Stack pointer ( ) Instruction register ( )

4 Figure 4.3 Main memory FFFE FFFF

5 Figure 4.4 Main memory A 000B 000D..

6 Figure B C (a) The content in binary. 02 D1 000B 000C (b) The content in hexadecimal. 000B 02D1 (c) The content in a machine language listing.

7 Figure 4.6 Instruction Specifier Instruction Stop execution Return from trap Move stack pointer (SP) to accumulator (A) Move NZVC flags to accumulator (A) a Branch unconditional a Branch if less than or equal to a Branch if less than a Branch if equal to a Branch if not equal to a Branch if greater than or equal to a Branch if greater than a Branch if V a Branch if C a Call subroutine

8 Figure 4.6 (Continued) r Bitwise invert register r r Negate register r r Arithmetic shift left register r r Arithmetic shift right register r r Rotate left register r r Rotate right register r n Unimplemented opcode, unary trap aaa Unimplemented opcode, nonunary trap aaa Unimplemented opcode, nonunary trap aaa Unimplemented opcode, nonunary trap aaa Unimplemented opcode, nonunary trap aaa Character input aaa Character output nn Return from call with n local bytes

9 Figure 4.6 (Continued) aaa Add to stack pointer (SP) aaa Subtract from stack pointer (SP) 0111 raaa Add to register r 1000 raaa Subtract from register r 1001 raaa Bitwise AND to register r 1010 raaa Bitwise OR to register r 1011 raaa Compare register r 1100 raaa Load register r from memory 1101 raaa Load byte register r from memory 1110 raaa Store register r to memory 1111 raaa Store byte register r to memory

10 Figure 4.7 Instruction specifier Operand specifier (a) The two parts of a nonunary instruction Instruction specifier (b) A unary instruction

11 Figure 4.8 aaa Addressing mode Immediate Direct Indirect Stack-relative Stack-relative deferred Indexed Stack-indexed Stack-indexed deferred (a) The addressing-aaa field.

12 Figure 4.8 (Continued) a Addressing mode r Register 0 1 Immediate Indexed 0 1 Accumulator, A Index register, X (b) The addressing-a field. (c) The register-r field.

13 Figure 4.9 Main memory A A A A5

14 The stop instruction Instruction specifier: Causes the computer to stop

15 The load instruction Instruction specifier: 1100 raaa Loads one word (two bytes) from memory to register r r Oprnd ; N r < 0, Z r = 0

16 Figure 4.10, 4.11 Instruction specifier Opcode r aaa Operand specifier C A NZ A 036D 92EF C1004A NZ A Load accumulator A 92EF 92EF 004A (a) Before (b) After

17 The store instruction Instruction specifier: 1110 raaa Stores one word (two bytes) from register r to memory Oprnd r

18 Figure 4.12, 4.13 Instruction specifier Opcode r aaa Operand specifier E A X 16BC F082 E9004A X 16BC 004A Store index register 16BC 004A (a) Before (b) After

19 The add instruction Instruction specifier: 0111 raaa Adds one word (two bytes) from memory to register r r r + Oprnd ; N r < 0, Z r = 0, V {overflow}, C {carry}

20 Figure 4.14, 4.15 Instruction specifier Opcode r aaa Operand specifier A NZVC X 0005 FFF9 004A 79004A Add index register NZVC 1000 X FFFE FFF9 004A (a) Before (b) After

21 The subtract instruction Instruction specifier: 1000 raaa Subtracts one word (two bytes) from memory from register r r r Oprnd ; N r < 0, Z r = 0, V {overflow}, C {carry}

22 Figure 4.16, 4.17 Instruction specifier Opcode r aaa Operand specifier A NZVC A A 81004A Subtract accumulator NZVC 1000 A FFF4 FFFA A (a) Before (b) After

23 The and instruction Instruction specifier: 1001 raaa ANDs one word (two bytes) from memory to register r r r Oprnd ; N r < 0, Z r = 0

24 Figure 4.18, 4.19 Instruction specifier Opcode r aaa Operand specifier A NZ X 5DC3 00FF 004A 99004A Add And index register NZ 00 X 00C3 00FF 004A (a) Before (b) After

25 The or instruction Instruction specifier: 1010 raaa ORs one word (two bytes) from memory to register r r r Oprnd ; N r < 0, Z r = 0

26 Figure 4.20 NZ X 5DC3 00FF 004A A9004A Or index register NZ 00 X 5DFF 00FF 004A (a) Before (b) After

27 The not instruction Instruction specifier: r Bit-wise NOT operation on register r Each 0 changed to 1, each 1 changed to 0 r r ; N r < 0, Z r = 0

28 Figure 4.21, 4.22 Instruction specifier Opcode r NZ AX Not accumulator NZ 10 XA FFFC (a) Before (b) After

29 The negate instruction Instruction specifier: r Negate (take two s complement of) register r r r ; N r < 0, Z r = 0

30 Figure 4.23 NZ A X A Negate accumulator NZ 10 A X FFFD (a) Before (b) After

31 The load byte instruction Instruction specifier: 1101 raaa Loads one byte from memory to the right half of register r r byte Oprnd ; N r < 0, Z r = 0

32 Figure 4.24, 4.25 Instruction specifier Opcode r aaa Operand specifier D A NZ A 036D A D1004A Load byte accumulator NZ 00 A A (a) Before (b) After

33 The store byte instruction Instruction specifier: 1111 raaa Stores one byte from the right half of register r to memory byte Oprnd r 8..15

34 Figure 4.26 XA 036D 92 F1004A Store byte A 036D 004A accumulator 6D 004A (a) Before (b) After

35 The character input instruction Instruction specifier: aaa Stores one ASCII byte from the input device to memory byte Oprnd {character input}

36 Figure 4.27, 4.28 Instruction specifier Opcode aaa Operand specifier A Input Input W A 49004A Character input W A (a) Before (b) After

37 The character output instruction Instruction specifier: aaa Sends one ASCII byte from memory to the output device {character output} byte Oprnd

38 Figure 4.29 Output Output A 51004A Character output A H (a) Before (b) After

39 The von Neumann execution cycle Fetch instruction from [PC] Decode the instruction fetched Increment PC Execute the instruction fetched Repeat

40 Load the machine language program Initialize PC and SP do { Fetch the next instruction Decode the instruction specifier Increment PC Execute the instruction fetched } while (the stop instruction does not execute) Figure 4.30

41 Figure 4.31 Load the machine language program into memory starting at address 0000 PC 0000 SP [FFF8] do { Fetch the instruction specifier at address in PC PC PC + 1 Decode the instruction specifier if (the instruction is not unary) { Fetch the operand specifier at address in PC PC PC + 2 } Execute the instruction fetched } while ((the stop instruction does not execute) && (the instruction is legal))

42 Figure 4.32 Address Machine Language (bin) Address Machine Language (hex) ;Character output ;Character output ;Stop ;ASCII H character ;ASCII i character Output Hi

43 Figure 4.33 PC IR 0000?????? 0003?????????? 0006?? Output PC???? 0007???????? IR?????? 0008?? Output (a) Initial state before loading. (b) Program loaded into main memory. PC IR 0000?????? Output PC IR Output (c) 0000 (hex) (d) Fetch

44 Figure 4.33 (Continued) PC IR Output PC IR Output (e) Increment. (f) Execute. Character sent to output device. PC IR Output PC IR Output (g) Fetch. (h) Increment.

45 Figure 4.33 (Continued) PC IR Output PC IR ???? Output (i) Execute. Character sent to output device. (j) Fetch PC IR Output PC ???? IR 00???? Output (k) Increment PC. (l) Execute. The computer halts.

46 Figure 4.34 Address Machine Language (bin) C Address Machine Language (hex) D ;Character input E ;Character input E ;Character output D ;Character output 000C 00 ;Stop Input up Output pu

47 Figure 4.35 Address Machine Language (bin) C F Address Machine Language (hex) 0000 C10011 ;A := first number ;Add the two numbers 0006 A10015 ;Convert sum to character 0009 F10010 ;Store the character 000C ;Output the character 000F 00 ;Stop ;Character to output ;Decimal ;Decimal ;Mask for ASCII char Output 8

48 Figure 4.36 Address Machine Language (bin) C F B D

49 Figure 4.36 (Continued) Address Machine Language (hex) 0000 D1001D ;Load byte accumulator 0003 F10009 ;Store byte accumulator 0006 C10017 ;A := first number ;Add the two numbers 000C A1001B ;Convert sum to character 000F F10016 ;Store the character ;Output the character ;Stop ;Character to output ;Decimal ;Decimal 3 001B 0030 ;Mask for ASCII char 001D 81 ;Byte to modify instruction Output 2

50 Figure FBCE FBCF Application program Operating system FFFF

51 ory devices Read/Write memory Also called Random-Access ory (RAM) Can load from RAM and store to RAM Read-Only memory (ROM) Can load from ROM Cannot store to ROM RAM and ROM are both random

52 Figure FBCE FBCF FC56 FC57 FFFF Application program Operating system RAM Operating system ROM RAM ROM

53 Figure Applications program User stack FBCF System stack FC4F FC57 I/O buffer Loader FC9B Trap handler FFF8 FFFA FFFC FFFE FBCF FC4F FC57 FC9B

54 The load option SP [FFFA] PC [FFFC] Start the von Neumann cycle

55 Figure 4.40 SP PC???????? FFFA FFFC 7C4F 7C57 SP PC FC4F???? FFFA FFFC FC4F FC57 (a) Initial state. (b) SP [FFFA] SP PC FC4F FC57 FFFA FFFC FC4F FC57 (c) PC [FFFC]

56 The execute option SP [FFF8] PC 0000 Start the von Neumann cycle

n NOPn Unary no operation trap U aaa NOP Nonunary no operation trap i

n NOPn Unary no operation trap U aaa NOP Nonunary no operation trap i Instruction set Instruction Mnemonic Instruction Addressing Status Specifier Mode Bits 0000 0000 STOP Stop execution U 0000 0001 RET Return from CALL U 0000 0010 RETTR Return from trap U 0000 0011 MOVSPA