ILI9163V. a-si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color. Specification

Transcription

1 a-si TFT LCD Single Chip Driver Specification Version V Document No. _DTS_V_2346 ILI TECHNOLOGY CORP. 8F, No.38, Taiyuan St., Jhubei City, Hsinchu County, Taiwan 32, R.O.C. Tel ; Fax http//

2 Table of Contents. Introduction Features Block Diagram Pin Descriptions Pad Arrangement and Coordination Function Description MCU Interface Type Selection Serial Interface Command Write Read Function Series Parallel Interface (P68= ) Write Cycle/Sequence Read Cycle/Sequence Series Parallel Interface (P68= ) Write Cycle/Sequence Read Cycle/Sequence Display Data Transfer Recovery Display Data Transfer Pause Display Data Transfer Mode RGB Interface RGB Interface Selection RGB Interface Timing RGB Interface Mode Set Display Data Color Coding Serial Interface bit Parallel Interface (IM2=, IM[] = ) bit Parallel Interface (IM2=, IM, IM= ) bit Parallel Interface (IM2= 2, IM, IM= ) bit Parallel Interface (IM2=, IM, IM= ) Display Data RAM Configuration Memory to Display Address Mapping RGB x 32 resolution (GM[2] =, SMX=SMY=SRGB= ) RGB x 3 resolution(gm[2] =, SMX=SMY=SRGB= ) RGB x 6 resolution (GM[2] =, SMX=SMY=SRGB= ) RGB x 6 resolution (GM[2] =, SMX=SMY=SRGB= ) RGB x 28 resolution (GM[2] =, SMX=SMY=SRGB= ) RGB x 62 resolution (GM[2] =, SMX=SMY=SRGB= ) MCU to memory write/read direction (Address Counter)... 6 Page 2 of 2

3 8. Tearing Effect Output Line Tearing Effect Line Modes Tearing Effect Line Timing Example MCU Write is Faster than Panel Read Example 2 MCU Write is slower than Panel Read Power ON/OFF Sequence Case RESX line is held high or Unstable by Host at Power On Case 2 RESX line is held Low by Host at Power On Uncontrolled Power Off Power Level Definition Power Levels Power Flow Chart Gamma Curves Gamma curve according to the Gamma./.8/2.2/ Gamma Structure Reset Registers Input/Output Pins Output Pins, I/O Pins Input Pins Reset Timing SleepOut Command and Self-Diagnostic Functions of Displap Register loading Detection Functionality Detection Command Command List Command Description NOP (h) Software Reset (h) Read Display Identification Information (4h) Read Display (9h) Read Display Power Mode (Ah) Read Display MADCTL (Bh) Read Display Pixel Format (Ch) Read Display Image Mode (Dh) Read Display Signal Mode (Eh) Read Display Signal Mode (Fh) Sleep In (h) Sleep Out (h) Partial Mode On (2h)... 7 Page 3 of 2

4 4.2.4 Normal Display Mode On (3h) Display Inversion Off (2h) Display Inversion On (2h) Gamma Set (26h) Display Off (28h) Display On (29h) Column Address Set (2Ah) Page Address Set (2Bh) Memory Write (2Ch) Color Setting fro 4K, 65K and 262K (2Dh) Memory Read (2Eh) Partial Area (3h) Vertical Scrolling Definition (33h) Tearing Effect Line Off (34h) Tearing Effect Line On (35h) Memory Access Control (36h) Vertical Scrolling Start Address (37h) Idle Mode Off (38h) Idle Mode On (39h) Interface Pixel Format (3Ah) Frame Rate Control (In normal mode/full colors) (Bh) Frame Rate Control(In Idle mode/8-colors) (B2h) Frame Rate Control(In Partial mode/full colors) (B3h) Display Inversion Control (B4h) RGB Interface Blanking Porch setting (B5h) Display Fuction set 5 (B6h) Source Driver Direction Control (B7h) Gate Driver Direction Control (B8h) Power_Control (Ch) Power_Control 2 (Ch) Power_Control 3 (C2h) Power_Control 4 (C3h) Power_Control 5 (C4h) VCOM_Control (C5h) VCOM Offset Control (C7h) Write ID4 Value (D3h) NV Memory Function Controller() (D5h) NV Memory Function Controller(2) (D6h) NV Memory Function Controller(3) (D7h) Read ID (DAh) Page 4 of 2

5 Read ID2 (DBh) Read ID3 (DCh) Positive Gamma Correction Setting (Eh) Negative Gamma Correction Setting (Eh) GAM_R_SEL (F2h) Example Connection with Panel direction and Different Resolution Application of connect with panel direction (when GM= ) Application of connection with Different resolution OTP Programming Flow Electrical Characteristics Absolute Maximum Ratings DC Characteristics AC Characteristics Parallel CPU 8/6/9/8-bit Bus Display Serial Interface (SPI) pin Serial Interface pin Serial Interface Parallel RGB 8/6/6-bit Bus Revision History... 2 Page 5 of 2

6 . Introduction is a 262,44-color one-chip SoC driver for a-tft liquid crystal display with resolution of 32RGBx62 dots, comprising a 396-channel source driver, a 62-channel gate driver, 48,4bytes GRAM for graphic data of 32RGBx62 dots, and power supply circuit. The supports 8-/6-/9-/8-bit data bus interface and serial peripheral interfaces (SPI). It also supplies 8-bit, 6-bit or 6-bit RGB interface for driving video signal directly from application controller. The moving picture area can be specified in internal GRAM by window address function. The specified window area can be updated selectively, so that moving picture can be displayed simultaneously independent of still picture area. can operate with.65v I/O interface voltage, and an incorporated voltage follower circuit to generate voltage levels for driving an LCD. The also supports a function to display in 8 colors and a sleep mode, allowing for precise power control by software and these features make the an ideal LCD driver for medium or small size portable products such as digital cellular phones, smart phone, MP3 and PMP where long battery life is a major concern. 2. Features Display resolution [32xRGB](H) x 62(V) Output 396 source outputs 62 gate outputs Common electrode output AM-LCD driver with on-chip full display RAM 48,4 bytes System Interfaces 8-bits, 9-bits, 6-bits, 8-bits interface with 88-series MCU 8-bits, 9-bits, 6-bits, 8-bits interface with 68-series MCU 6-bits, 6-bits, 8-bits RGB interface 3-pin/4-pin serial interface Display mode Full color mode (idle mode off) 262K-colors Reduced color mode (idle mode on) 8-colors (3-bits MSB bits mode) On chip functions VCOM generator and adjustment Timing generator Oscillator DC/DC converter 4 preset gamma curve selectable Line/frame inversion MTP to store initialization register setting Factory default value(contrast, Module ID, Module version, etc) are stored on the display module Page 6 of 2

7 MTP 8-bits for ID2 8-bits for ID3 7-bits for VCOM adjustment Low power consumption architecture Low operating power supplies VDDI =.65V ~ 3.3 V (interface I/O) VCI = 2.5V ~ 4. V (analog) LCD Voltage drive Source/VCOM power supply voltage AVDD GND = 4.V ~ 6.V VCL GND = -.V ~ -3.V VCI VCL 6.V Gate driver output voltage VGH GND = V ~ 6V VGL GND = -6V ~ -2V VGH VGL 3V VCOM driver output voltage VCOMH = 2.5V ~5V VCOML = -2.5V ~ V VCOMH-VCOML 6.V Operate temperature range -4 to 85 Page 7 of 2

8 3. Block Diagram a-si TFT LCD Single Chip Driver Page 8 of 2

9 4. Pin Descriptions a-si TFT LCD Single Chip Driver P68 IM2 Pin Name I/O Descriptions 88/68 MCU Interface mode selection. I P68= select 68-MCU parallel interface P68= select 88-MCU parallel interface If not used, please fix this pin at GND level. MCU Parallel interface bus and Serial interface select I - IM2= ;Parallel Interface - IM2= ;Serial Interface MCU parallel interface type selection IM, IM SPI4W RESX CSX D/CX (SCL) RDX (E) WRX (R/WX)(D/CX) D[7] D[]/SDIO I I I I I I I I/O IM IM Parallel interface MCU 8-bit Parallel MCU 6-bit Parallel MCU 9-bit Parallel MCU 8-bit Parallel SPI interface selection pin SPI4W= 3-wire SPI. (default) SPI4W= 4-wire SPI. This pin is internal pull low. Chip reset pin ( Low Active ). This signal low will reset the device and must be applied to properly initialize the chip. Chip select input pin ( Low enable). This pin can be permanently fixed Low in MCU interface mode only. Display data / Command selection pin in parallel and SCL in 3-pin SPI interface. D/CX= Display data. D/CX= Command data. If not used, please connect this pin to GND. Read enable in 88-parallel interface and Read/ Write operation enable pin in 68-parallel interface. In 88-parallel interface, if not used, please connect this pin to VDDI. In 68-parallel interface, if not used, please connect this pin to VDDI or GND. Write enable in parallel interface. WRX for 88 MCU R/WX for 68 MCU D/CX for 4-wire SPI If not used, please connect this pin to VDDI or GND. When RCM= (MCU I/F), D[7] are used to MCU parallel interface data bus, and D is also the serial input/ output signal in SPI interface mode. In serial interface, D[7] are not used and should be connected to ground. When RCM= (RGB I/F), D[7] are used to RGB interface data bus. Page 9 of 2

10 TE SDA PCLK VS HS DE Pin Name I/O Descriptions O I/O I I I I Tearing effect output pin to synchronies MCU to frame writing, activated by S/W command. When this pin is not activated, this pin is low. If not used, please open this pin. When RCM,RCM= X (RGB I/F), serial input/output signal in serial I/F mode. The data is input on the rising edge of the SCL signal. The data is output on the falling edge of the SCL signal. When RCM,RCM= X (MCU I/F), this pin is not used, and fix at VDDI or GND level. If not used, please fix this pin at VDDI or GND level. Pixel clock signal in RGB I/F mode. -If it s not used, please fix this pin at GND level. Vertical sync. Signal in RGB I/F mode. -If it s not used, please fix this pin at GND level. Horizontal sync. Signal in RGB I/F mode. -If it s not used, please fix this pin at GND level. Data enable signal in RGB I/F mode. -If it s not used, please fix this pin at GND level. OSC O Oscillator output or test purpose. EXTC IDM I I To use extended command set, please connect this pin to VDDI. During normal operation, please open this pin. (It has an internal pull low resistor.) EXTC=, all the command can be used. EXTC=, only Command (h~3ah, DAh~DCh) can be used Normal mode and Idle mode control pin(only for RGB interface(2)) IDM Idle mode H/W controller Normal display (can be changed to Idle mode by S/W) Idle mode Panel Resolution selection pins GM2,GM,GM RCM[] I I GM2 GM GM Resolution selection 32RGB x 62(S~396 and G~ G62 output) 28RGB x 28(S7~39 and G2~ G29 output) 2RGB x 6(S7~366 and G2~ G6 output) 28RGB x 6(S7~39 and G2~ G6 output) 3RGB x 3(S7~396 and G2~ G3 output) 32RGB x 32(S~396 and G2~ G33 output) RGB and MCU interface mode selection pin RCM RCM Resolution selection X MCU interface mode RGB interface() RGB interface(2) SRGB I RGB direction select H/W pin for Color filter default setting. SRGB Color mapping selection S, S2, S3 filter order = R, G, B S, S2, S3 filter order = B, G, R Page of 2

11 Pin Name I/O Descriptions If the register is not changed, this H/W pin is always valid. If the register be changed, should be following registers setting. When Power On or H/W reset, this function follow H/W pins setting first. SMX SMY I I Source output direction H/W select pin SMX Source Output Direction GM= GM= GM= GM= GM= GM= S S396 S7 S396 S7 S39 S7 S366 S7 S39 S S396 S396 S S396 S7 S39 S7 S366 S7 S39 S7 S396 S If the register is not changed, this H/W pin is always valid. If the register be changed, should be following registers setting and H/W operation (XOR). When Power On or H/W reset, this function follow H/W pins setting first. Gate output direction H/W select pin SMY Gate Output Direction GM= GM= GM=, GM= GM= G2 G33 G2 G3 G2 G6 G2 G29 G G62 G33 G2 G3 G2 G6 G2 G29 G2 G62 G SHUT REV LCM[] GS I I I I If the register is not changed, this H/W pin is always valid. If the register be changed, should be following registers setting and H/W operation(xor). When Power On or H/W reset, this function follow H/W pins setting first. Display On/ Off H/W control pin In RGB I/F(Only for RGB interface(2)) SHUT Display On/Off in RGB interface Display on Display off Please refer RGB I/F for detail using. Source output data polarity select H/W pin. REV Source output data polarity Data not reverse Data reverse If the register is not changed, this H/W pin is always valid. If the register be changed, should be following registers setting. When Power On or H/W reset, this function follow H/W pins setting first. Different Liquid Crystal type selection pins. There is a pull-low resistor only in LCM pin LCM LCM LC Type Selection TM (Transmission) LC Type2 Input pin to select the gamma curve order Connect to VDDI for GC(2,2), GC(.8), GC2(2.5), GC3(.) Connect to GND for GC(,), GC(2.5), GC2(2.2), GC3(.8) Page of 2

12 Pin Name I/O Descriptions TESEL I Default is internal pull high. This pin is only for GM[2]= mode Connect to VDDI (Disable scroll function) Connect to GND (Enable scroll function) RL I Source output direction H/W select pin in RGB interface(2) When SMX= RL Module source output direction GM= GM= GM= GM= GM= GM= S S396 S7 S396 S7 S39 S7 S366 S7 S39 S S396 S396 S S396 S7 S39 S7 S366 S7 S39 S7 S396 S When SMX= Module source output direction RL GM= GM= GM= GM= GM= GM= S396 S S396 S7 S39 S7 S366 S7 S39 S7 S396 S S S396 S7 S396 S7 S39 S7 S366 S7 S39 S S396 TB I Gate output direction H/W select pin on RGB interface(2) When SMY=. When SMY= Module gate output direction TB GM=, GM= GM= GM= GM= G2 G33 G2 G3 G2 G6 G2 G29 G G62 G33 G2 G3 G2 G6 G2 G29 G2 G62 G Module gate output direction TB GM= GM= GM=, GM= GM= G33 G2 G3 G2 G6 G2 G29 G2 G62 G G2 G33 G2 G3 G2 G6 G2 G29 G G62 S ~ S396 O Source driver output pins. G ~ G62 O Gate driver output pins. VCI P Power supply for analog circuit. Could connect to external power supply (VCI=2.5~4.V). VDDI P Power supply for interface logic circuits (.65 ~ 3.3 V) VCC P Power supply for internal logic regulator. GND P GND voltage output level for control pins. VDDIO P VDDI voltage output level for control pins using. GNDO P GND voltage output level for control pins using. VCI P A reference voltage in step-up circuit AVDD P A power output pin for source driver block that is generated from power block. Page 2 of 2

13 VCL Pin Name I/O Descriptions Output of booster circuit (output of 2-times output of VCI) Connect a capacitor for stabilization. P A power supply pin for generating VCOML GVDD P A standard level for grayscale voltage generator. VGH P Positive power supply for the gate driver. VGL VCOM P O Negative power supply for the gate driver. Connect a capacitor for stabilization TFT display common electrode power supply. Alternates between voltage levels between VCOMH-VCOML. Registers set the alternating cycle for operating or halting VCOM. VCOMH O The high level of VCOM AC voltage. VCOML O The low level of VCOM AC voltage. TESTOSC TESTDA[5] TEST_MODE[2] DUMMYR-DUMMYR2 - DUMMY-DUMMY8 DUMMY I O These test pins for Driver vender test used. Please open these pins or fix to GND. These test pins for Driver vendor test used. Please open these pins. DUMMYR and DUMMYR2 are short-circuited within the chip for COG contact resistance measurement. Please leave them open when not used. - Dummy pins. During normal operation, leave these pads open. Liquid crystal power supply specifications Table No. Item Description TFT Source Driver 396 pins (32 x RGB) 2 TFT Gate Driver 62 pins 3 TFT Display s Capacitor Structure Cst structure only (Common VCOM) S ~ S396 V ~ V63 grayscales 4 Liquid Crystal Drive Output G ~ G62 VGH VGL VCOM VCOMH VCOML Amplitude = electronic volumes 5 Input Voltage VDDI.65 ~ 3.3V VCI 2.5 ~ 4.V AVDD 4.V ~ 6.V VGH V ~ 6V 6 Liquid Crystal Drive Voltages VGL -6V ~ -2V VCL -.V ~ -3.V VGH VGL Max. 3V VCI VCL Max. 6.V AVDD VCI x2 Internal Step-up Circuits VGH AVDD x2.5, x3 VGL AVDD -x2.5, -x3 VCL VCI x- Page 3 of 2

14 a-si TFT LCD Single Chip Driver 5. Pad Arrangement and Coordination 8 um 8 um Chip Size 99um x 67um Chip thickness 28 um (typ.)/3um Pad Location Pad Center. Coordinate Origin Chip Center Au bump height um um Alignment Mark -Left um 5um 5 um 8um (- 484, -22) 2 um 5um 5 um Alignment Mark- Right 5um 5 um 8um um ( 484, -22) um 2 um 5um 5 um 5um 5um 2um 5um 5um 5um 5um 2um 5um 5um 75 Face Up ( Bump View) Dummy VDDIO EXTC GNDO IM VDDIO IM GNDO P68 VDDIO RCM GNDO RCM VDDIO SRGB GNDO SMX VDDIO SMY GNDO IDM VDDIO REV GNDO RL VDDIO TB GNDO SHUT VDDIO LCM GNDO LCM VDDIO GM2 GNDO GM VDDIO GM GNDO SDA GS SPI4W VDDIO TESTMODE[2] TEST_IN[5] TEST_IN[4] TEST_IN[3] TESTOSC OSC VCI VCI VCI VCI VCI VCI AGND AGND AGND AGND AGND AGND RDX D/CX TESEL GNDO D7 D6 D5 D4 D3 D2 D D D 9 D 8 D D 3 D 5 D 7 TE RESX CSX D 6 D 4 D 2 IM2 D WRX PCLK DE HS VS TEST_IN[2] TEST_IN[] TEST_IN[] DGND DGND DGND DGND DGND DGND VDDI VDDI VDDI VDDI VDDI VDDI VCC VCC VCC VCI VCI VCI Dummy Dummy Dummy TESTMODE[] TESTMODE[] AVDD AVDD AVDD AVDD AVDD GVDD GVDD GVDD DUMMYR DUMMYR2 Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy AGND AGND AGND VCL VCL VCL Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy VGL VGL VGL VGH VGH VGH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOM VCOM VCOM DUMMY Chi p Cent er X 392 um Y DUMMY8 DUMMY7 G6 G59 G57 G55 G53 G5 G49 G47. G7 G5 G3 G DUMMY6 DUMMY5 Dummy4 DUMMY3 S S2 S3 S4 S5 S6 S7 S8 S89 S9 S9 S92 S93 S94 S95 S96 S97 S98 DUMMY2 DUMMY DUMMY DUMMY9 S99 S2 S2 S22 S23 S24 S25 S26 S27 S28. S389 S39 S39 S392 S393 S394 S395 S396 DUMMY8 DUMMY7 DUMMY6 DUMMY5 G2 G4 G6 G8.. G48 G5 G52 G54 G56 G58 G6 G62 DUMMY4 DUMMY3 Page 4 of 2

15 a-si TFT LCD Single Chip Driver VCOM IM IM IM IM P68 P68 VDD VDD RDX RDX DB7 DB7 DB5 DB5 DB3 DB3 DB DB DB9 DB9 DB DB DB5 DB5 TE TE CSX CSX DB4 DB4 PS PS WRX WRX DE DE VS VS VDDI VDDI D/CX D/CX DB6 DB6 DB4 DB4 DB2 DB2 DB DB DB8 DB8 DB3 DB3 DB7 DB7 RESX RESX DB6 DB6 DB2 DB2 DB DB PCLK PCLK HS HS.uF/6 3V.uF/6.3V 28x6.uF/6 3V.uF/6.3V (Optional).uF/ 5V Dummy < ohm VDDIO Dummy < ohm EXTC VDDIO < ohm ohm GNDO EXTC < < ohm IM GNDO < < ohm VDDIO IM < < ohm VDDIO IM < ohm ohm GNDO IM < ohm PGNDO 68 < < ohm VDDIO P68 < < ohm RCM VDDIO < < ohm GNDO RCM ohm RCM GNDO < < ohm VDDIO RCM < < ohm SRGB VDDIO < < ohm GNDO SRGB < ohm ohm SMX GNDO < ohm VDDIO SMX < < ohm VDDIO SMY < < ohm GNDO SMY < ohm ohm IDM GNDO < < ohm ohm VDDIO IDM < ohm REV VDDIO < < ohm GNDO REV < < ohm GNDO RL < ohm VDDIO RL < ohm VDDIO TB < < ohm GNDO TB < < ohm SHUT GNDO < ohm VDDIO SHUT < < ohm ohm LCM VDDIO < ohm GNDO LCM < < ohm LCM GNDO < ohm VDDIO LCM < ohm ohm GM2 VDDIO < < ohm GNDO GM2 < < ohm GM GNDO < ohm VDDIO GM < ohm GM VDDIO < < ohm GNDO GM < < ohm SDA GNDO < < ohm GS SDA ohm SPI4W GS < < ohm VDDIO SPI4W < ohm TESTDA[6] VDDIO TEST_MODE[2] TESTDA[5] TESTDA[4] TEST_IN [5] TESTDA[3] TEST_IN [4] TESTOSC TEST_IN [3] TESTOSC VPNL OSC VPNL VPNL VPNL < ohm VPNL < ohm VPNL VPNL VPNL AGND VPNL AGND AGND AGND < ohm AGND < ohm AGND AGND < ohm RDX AGND < < ohm D /CX RDX < < ohm TESEL D/CX < ohm GNDO TESEL < ohm ohm D7 GNDO < < ohm D 6 D7 < < ohm D 5 D6 < < ohm D 4 D5 < < ohm D 3 D4 ohm D 2 D3 < < ohm D D2 < < ohm D D < ohm D9 D < ohm D8 D9 < < ohm D D 8 < < ohm D3 D < ohm ohm D5 D 3 < ohm D7D 5 < < ohm TE D 7 < < ohm RESX TE < ohm ohm CSX RESX < ohm D6 CSX < < ohm D4 D 6 < ohm D2 D 4 < ohm IM2 D 2 < < ohm D IM2 < < ohm WRX D < < ohm PCLK WRX < < ohm DE PCLK < < ohm HS DE < ohm VS HS < ohm TESTDA[2] VS TESTDA[] TEST_IN [2] TESTDA[] TEST_IN [] TEST_IN GND [] DGND DGND < ohm DGND D < ohm DGND DGND VDDI DGND VDDI VDDI < ohm VDDI VDDI < ohm VDDI VDDI VDDI VDDI VDDI VDDI VCC VDDI < ohm VCC VCC < ohm VCC VCC VCI VCC < ohm VCI VCI < ohm VCI VCI VREF VCI VREF Dummy VREF Dummy TEST Dummy TEST_MODE[ VPRER_OUT ] TEST_MODE[] AVDD AVDD AVDD < ohm AVDD < ohm AVDD AVDD GVDD AVDD < ohm GVDD < ohm GVDD ohm DUMMYR GVDD < < ohm DUMMYR2 DUMMYR < ohm DUMMYR2 CA < ohm CA Dummy CA Dummy CA Dummy CB Dummy CB Dummy < ohm CB Dummy CB Dummy C2A Dummy C2A Dummy < ohm C2A Dummy Dummy C2A Dummy C2B Dummy C2B < ohm Dummy C2B Dummy C2B AGND Dummy < ohm AGND AGND < ohm AGND AGND VCL AGND < ohm VCL VCL < ohm VCL VCL C2A VCL < C2A Dummy C2A Dummy C2B Dummy < ohm C2B Dummy C2B Dummy C22A Dummy < ohm C22A Dummy C22A Dummy C22B Dummy < ohm CDummy B C22B Dummy C23A Dummy < ohm C23A Dummy C23A Dummy C23B Dummy < ohm C23B Dummy C23 Dummy Dummy < ohm VGL VGL < ohm VGL VGL VGH VGL < ohm VGH VGH < ohm VGH VGH VCOMH VGH < ohm VCOMH < ohm VCOMH VCOML VCOMH < ohm VCOML < ohm VCOML VCOM VCOML < ohm VCOM VCOM < ohm VCOM VCOM DUMMY2 VCOM DUMMY Chip Chip Center Center X um 392u m Y DUMMY8 DUMMY7 DUMMY8 G6 DUMMY7 G59 G 6 G57 G 59 G55 G 57 G53 G 55 G5 G 53 G49 G 5 G47 G 49 G 47.. G7 G5G 7 G3G 5 GG 3 DUMMY6 G DUMMY5 DUMMY6 Dummy4 DUMMY5 DUMMY3 Dummy4 SDUMMY3 S2S S3S2 S4S3 S5S4 S6S5 S7S6 S8S7 S8 S89 S9 S89 S9 S9 S92 S9 S93 S92 S94 S93 S95 S94 S96 S95 S97 S96 S98 S97 DUMMY2 S98 DUMMY DUMMY2 DUMMY DUMMY DUMMY9 DUMMY S99 DUMMY9 S2 S99 S2 S2 S22 S2 S23 S22 S24 S23 S25 S24 S26 S25 S27 S26 S28 S27 S28.. S389 S39 S389 S39 S39 S392 S39 S393 S392 S394 S393 S395 S394 S396 S395 DUMMY8 S396 DUMMY7 DUMMY8 DUMMY6 DUMMY7 DUMMY5 DUMMY6 G2 DUMMY5 G4G 2 G6G 4 G8G 6 G G48 G5 G 48 G52 G 5 G54 G 52 G56 G 54 G58 G 56 G6 G 58 G62 G 6 DUMMY4 G 62 DUMMY3 DUMMY4 DUMMY3 VCOM Page 5 of 2

16 No. Name X Y No. Name X Y No. Name X Y No. Name X Y No. Name X Dummy AGND AVDD VCOML G VDDIO AGND AVDD VCOM G EXTC RDX AVDD VCOM G GNDO D/CX AVDD VCOM G IM TESEL GVDD DUMMY G VDDIO GNDO GVDD DUMMY G IM D GVDD DUMMY G GNDO D DUMMYR G G P D DUMMYR G G VDDIO D Dummy G G RCM D Dummy G G GNDO D Dummy G G RCM D Dummy G G VDDIO D Dummy G G SRGB D Dummy G G GNDO D Dummy G G SMX D Dummy G G VDDIO D Dummy G G SMY D Dummy G G GNDO D Dummy G G IDM TE Dummy G G VDDIO RESX Dummy G G REV CSX Dummy G G GNDO D Dummy G G RL D Dummy G G VDDIO D AGND G G TB IM AGND G G GNDO D AGND G G SHUT WRX VCL G DUMMY VDDIO PCLK VCL G DUMMY LCM DE VCL G DUMMY GNDO HS Dummy G DUMMY LCM VS Dummy G S VDDIO TESTDA[2] Dummy G S GM TESTDA[] Dummy G S GNDO TESTDA[] Dummy G S GM DGND Dummy G S VDDIO DGND Dummy G S GM DGND Dummy G S GNDO DGND Dummy G S SDA DGND Dummy G S GS DGND Dummy G S SPI4W VDDI Dummy G S VDDIO VDDI Dummy G S TESTMODE[2] VDDI Dummy G S TESTDA[5] VDDI Dummy G S TESTDA[4] VDDI Dummy G S TESTDA[3] VDDI Dummy G S TESTOSC VCC Dummy G S OSC VCC VGL G S VCI VCC VGL G S VCI VCI VGL G S VCI VCI VGH G S VCI VCI VGH G S VCI Dummy VGH G S VCI Dummy VCOMH G S AGND Dummy VCOMH G S AGND TEST_MODE[] VCOMH G S AGND TEST_MODE[] VCOML G S AGND AVDD VCOML G S Page 6 of 2

17 No. Name X Y No. Name X Y No. Name X Y No. Name X Y No. Name X Y 3 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S Dummy S S S S Dummy S S S S Dummy S S S S Dummy S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S Page 7 of 2

18 No. Name X Y No. Name X Y No. Name X Y 6 S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S Dummy G S Dummy G S Dummy G S Dummy G S G G S G G S G G S G G S G G S G G S G G S G G S G G S G G S G G S G G S G G S G G S G G S G G S G G S G G S G G S G G S G G S G Dummy S G Dummy S G S G ALK-R S G ALK-L S G S G S G S G S G S G S G S G S G S G S G S G S G S G S G S G S G S G Page 8 of 2

19 S ~ S396 G ~ G Input Pad Page 9 of 2

20 6. Function Description 6. MCU Interface Type Selection The selection of a given interfaces are done by setting P68, IM2, IM, and IM pins as show in below tables. Table 6.. MCU Interface Type Selection P68 IM2 IM IM Interface Read back selection Via the read instruction (8-bit, 24-bit and 32-bit read Serial interface parameter) 88 MCU 8-bit RDX strobe(8-bit read data and 8-bit read parameter) Parallel 88 MCU 6-bit RDX strobe(6-bit read data and 8-bit read parameter) Parallel 88 MCU 9-bit RDX strobe(9-bit read data and 8-bit read parameter) Parallel 88 MCU 8-bit RDX strobe(8-bit read data and 8-bit read parameter) Parallel 68 MCU 8-bit E strobe(8-bit read data and 8-bit read parameter) Parallel 68 MCU 6-bit E strobe(9-bit read data and 8-bit read parameter) Parallel 68 MCU 9-bit E strobe(6-bit read data and 8-bit read parameter) Parallel 68 MCU 8-bit E strobe(8-bit read data and 8-bit read parameter) Parallel Page 2 of 2

21 6.2 Serial Interface The Module uses a 3-wire 9-bit serial interface or 4-pins/8-bit bi-directional interface for communication between the micro controller and the LCD driver chip. The 3-pins serial use CSX (chip enable), SCL(serial clock) and SDA(serial data input/output) and the 4-pins serial use CSX(chip enable), D/CX(data/ command select), SCL(serial clock), and SDA(serial data input/output). Table 6.2. Serial Interface Type Selection IM2 4WSPI Interface Read back selection 3-Pins Serial Interface Via the read instruction(8-bit, 24-bit and 32-bit read parameter) 4-Pins Serial Interface Via the read instruction(8-bit, 24-bit and 32-bit read parameter) 6.2. Command Write The write mode of the interface means the micro controller writes commands and data to the LCD driver. 3-pins serial data packet contains a control bit D/CX and a transmission byte and in 4-pins serial case, data packet contains just transmission byte and control bit D/CX is transferred by the D/CX pin. If D/CX is low, the transmission byte is interpreted as a command byte. If D/CX is high, the transmission byte is stored in the display data RAM (Memory write command), or command register as parameter. Any instruction can be sent in any orders to the Driver. The MSB is transmitted first. The serial interface is initialized when CSX is high status. In this state, SCL clock pulse or SDA data have no effect. A falling edge on CSX enables the serial interface and indicated the start of data transmission. Figure 3-pins Serial Data Stream Format Transmission byte(tb) may be a command or a date MSB LSB D/CX D7 D6 D5 D4 D3 D2 D D D/CX TB D/CX TB D/CX TB Figure2 4-pins Serial Data Stream Format Transmission byte(tb) may be a command or a date MSB LSB D7 D6 D5 D4 D3 D2 D D TB TB TB When CSX is high, SCL clock is ignored. At the falling edge of CSX, SCL can be high or low. SDA is sampled at the rising edge of CSX. D/CX indicates, whether the byte is command code (D/CX= ) or parameter/ram data (D/CX= ). If CSX stays low after the last bit of command/data byte, the serial interface expects the D/CX bit (3-pin serial interface) or D7(4-pins serial interface) of the next byte at the next rising edge of SCL. Page 2 of 2

22 3-line Serial Interface Protocol CSX S TB TB P Host (MCU to Driver) SDA SCL D7 D6 D5 D4 D3 D2 D D D/C D7 D6 D5 D4 D3 D2 D D Command Data / Command / The CSX can be high level between the data and next command.the SDA and SCL are invalid during CSX is high level 4 -lin e S e ria l Inte rfa ce P ro toc o l S TB TB P CS X D /C X T B D /C S C L SD A D 7 D 6 D 5 D 4 D 3 D 2 D D D 7 D6 D 5 D 4 D 3 D 2 D D C om m a nd D ata / Com m and / Pa ram eter C S X ca n b e "H " b e tw e e n c o m m a n d / co m m a n d an d p a ra m e te r / com m a n d. S C L a n d S D A d u r in g C S X =" H " is in va lid Read Function CSX S TB TB P S Driver Host SCL SDA (SDI) SDA (SDP) D/CX D7 D6 D5 D4 D3 D2 D D Hi-Z Hi-Z D7 D6 D5 D4 D3 D2 D D D/CX Figure3 3-Pins Serial Protocol (for DAH/DBH/DCH/Ah/Bh/Ch/Dh/Eh/Fh command 8-bit read) Page 22 of 2

23 S TB TB P S CSX Driver Host SCL SDA (SDI) SDA (SDP) D/CX D7 D6 D5 D4 D3 D2 D D Hi-Z Hi-Z D23 D22 D2 D2 D9 D3 D2 D D Dummy Clock Cycle D/CX Figure4 3-Pins Serial Protocol (for 4H command 24-bit read) S TB TB P S CSX Driver Host SCL SDA (SDI) SDA (SDP) D/CX D7 D6 D5 D4 D3 D2 D D Hi-Z Hi-Z D3 D3 D29 D28 D27 D3 D2 D D Dummy Clock Cycle D/CX Figure5 3-Pins Serial Protocol (for 9H command 32-bit read) Page 23 of 2

24 S TB TB P S CSX Host (MCU to Driver) SCL D/CX SDA (SDI) D7 D6 D5 D4 D3 D2 D D Hi-Z D7 Host (Driver to MCU) SDA (SDO) Hi-Z D7 D6 D5 D4 D3 D2 D D Figure6 4-pins Serial Protocol (for DAH/DBH/DCH/AH/BH/CH/DH/EH/FH command 8-bit read) S TB TB P S CSX Host (MCU to Driver) SCL D/CX Host (Driver to MCU) SDA (SDI) SDA (SDO) D7 D6 D5 D4 D3 D2 D D Hi-Z Hi-Z D23 D22 D2 D2 D D Dummy Clock Cycle Figure7 4-pins Serial Protocol (for 4H command 24-bit read) D7 S TB TB P S CSX Host (MCU to Driver) SCL D/CX SDA (SDI) D7 D6 D5 D4 D3 D2 D D Hi-Z D7 Host (Driver to MCU) SDA (SDO) Hi-Z D3 D3 D29 D28 D27 D26 D2 D D Dummy Clock Cycle Figure8 4-pins Serial Protocol (for 9H command 32-bit read) Page 24 of 2

25 Series Parallel Interface (P68= ) The MCU uses a -wires 8-data parallel interface or 2-wires 9-data parallel interface or 9-wires 6-data parallel interface or 2-wires 8-data parallel interface. The chip-select CSX (active low) enables and disables the parallel interface. RESX (active low) is an external reset signal. WRX is the parallel data write, RDX is the parallel data read and D[7] is parallel data. The graphics controller chip reads the data at the rising edge of WRX signal. The D/CX is the data/command flag. When D/CX=, D[7,] bits are display RAM data or command parameters. When D/C=, D[7,] bits are commands. The 88-series bi-direction interface can be used for communication between the micro controller and LCD driver chip. The selection of this interface is done when P68 pin is low state (GND). Interface bus width can be selected with IM2, IM and IM. The interface function of 88-series parallel interface are given in Table Table 6.3.The function of 88-series parallel interface P68 IM2 IM IM Interface D/CX RDX WRX Function Write 8-bit command(d7 to D) Write 8-bit display data or 8-bit parameter(d7 to 8-bit Parallel D) Read 8-bit display data(d7 to D) Read 8-bit parameter or status(d7 to D) Write 8-bit command(d7 to D) Write 6-bit display data or 8-bit parameter(d5 6-bit to D) Parallel Read 6-bit display data(d5 to D) Read 8-bit parameter or status(d7 to D) Write 8-bit command(d7 to D) Write 9-bit display data or 8-bit parameter(d8 to 9-bit Parallel D) Read 9-bit display data (D8 to D) Read 8-bit parameter or status(d7 to D) Write 8-bit command(d7 to D) 8-bit Parallel Write 8-bit display data or 8-bit parameter(d7 to D) Read 8-bit display data(d7 to D) Read 8-bit parameter or status(d7 to D) Note Reading operation applied for command code DAh, DBh, DCh, 4h, 9h, Ah, Bh, Ch, Dh, Eh, Fh 6.3. Write Cycle/Sequence The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write cycle (WRX high-low-high sequence) consists of 3 control (D/CX, RDX, WRX) and data signals (D[7 ]). D/CX bit is a control signal, which tells if the data is a command or a data. The data signals are a command if the control signal is low (= ) and vice versa it is data (= ). The write cycle is described in the following figure. Page 25 of 2

26 WRX D[7], D[8] or D[5], D[7] The host asserts D[7], D[5], D[8] or D[7] lines when there is falling edge of WRX The display read D[7], D[5], D[8] or D[7] lines when there is rising edge of WRX The host negates D[7], D[5], D[8] or D[7] lines. Note WRX is an unsynchronized signal (it can be stopped) Figure9 88-Series WRX Protocol -byte command 2-byte command n-byte command (number of parameter = n- CMD CMD PA CMD PA Pa n-2 Pa n- P CSX D/CX RDX WRX D[7] Host D[7] (MPU to LCD) Driver D[7] (LCD to MPU) CMD CMD PA CMD PA Pa n-2 CMD CMD PA CMD Pa n-2 PA Hi-Z CMD Write command code PA Write parameter or RAM data Signals on D[7], D/CX and WRX pins during CSX= H are ignore Figure 88-Series Parallel bus protocol (write to register or display RAM) Page 26 of 2

27 6.3.2 Read Cycle/Sequence The read cycle (RDX high-low-high sequence) means that the host reads information from the display via interface. The display sends data (D[7 ]) to the host when there is a falling edge of RDX and the host reads data when there is a rising edge of RDX. RDX D[7], D[8] or D[5], D[7] The display asserts D[7], D[5], D[8] or D[7] lines when there is a falling edge of RDX. The host reads D[7], D[5], D[8] or D[7] lines when there is a rising edge of RDX. The display negates D[7], D[5], D[8] or D[7] lines Note RDX is an unsynchronized signal (It can be stopped). Figure 88-Series RDX Protocol Read command Read display RAM data CMD DM PA CMD DM Data Data P CSX D/CX RDX WRX D[7] CMD DM PA CMD Hi-Z DM PA PA Host D[7] (MPU to LCD) CMD CMD Hi-Z Driver D[7] (LCD to MPU) Hi-Z DM PA Hi-Z DM PA PA CMD Write command code PA Write parameter or RAM data Signals on D[7], D/CX, RDX and WRX pins during CSX= H are ignore Figure2 88-Series parallel bus protocol (Read from register or display RAM) Page 27 of 2

28 Series Parallel Interface (P68= ) The MCU uses a -wires 8-data parallel interface or 2-wires 9-data parallel interface or 9-wires 6-data parallel interface or 2-wires 8-data parallel interface. The chip-select CSX(active low) enables and disables the parallel interface. RESX(active low) is an external reset signal. WRX is the parallel data write, RDX is the parallel data read and D[7] is parallel data. The Graphics Controller Chip reads the data at the falling edge of E signal when R/WX= and writes the data at the falling of the E signal when R/WX=. The D/CX is the data/command flag. When D/CX=, D[7,] bits are display RAM data or command parameters. When D/C=, D[7,] bits are commands. The 68-series bi-direction interface can be used for communication between the micro controller and LCD driver chip. The selection of this interface is done when P68 pin is high state (VDDI). Interface bus width can be selected with IM2, IM and IM. The interface function of 68-series parallel interface are given in Table Table 6.4. The function of 68-series parallel interface P68 IM2 IM IM Interface D/CX RDX E Function Write 8-bit command(d7 to D) Write 8-bit display data or 8-bit parameter(d7 to D) 8-bit Parallel Read 8-bit display data(d7 to D) Read 8-bit parameter or status(d7 to D) Write 8-bit command(d7 to D) Write 6-bit display data or 8-bit parameter(d5 to D) 6-bit Parallel Read 6-bit display data(d5 to D) Read 8-bit parameter or status(d7 to D) Write 8-bit command(d7 to D) Write 9-bit display data or 8-bit parameter(d8 to D) 9-bit Parallel Read 9-bit display data (D8 to D) Read 8-bit parameter or status(d7 to D) Write 8-bit command(d7 to D) Write 8-bit display data or 8-bit parameter(d7 to D) 8-bit Parallel Read 8-bit display data(d7 to D) Read 8-bit parameter or status(d7 to D) Note Reading operation applied for command code DAh, DBh, DCh, 4h, 9h, Ah, Bh, Ch, Dh, Eh, Fh Page 28 of 2

29 6.4. Write Cycle/Sequence The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write cycle (E low-high-low sequence) consists of 3 control (D/CX, E, R/WX) and data signals (D[7 ]). D/CX bit is a control signal, which tells if the data is a command or a data. The data signals are a command if the control signal is low (= ) and vice versa it is data (= ). The write cycle is described in the following figure. R/WX = E D[7], D[8] or D[5], D[7] The host asserts D[7], D[5], D[8] or D[7] lines when there is falling edge of E The display read D[7], D[5], D[8] or D[7] lines when there is rising edge of E The host negates D[7], D[5], D[8] or D[7] lines. Note E is unsynchronized signal (it can be stopped) Figure3 68-Series Write Protocol -byte command 2-byte command N-byte command (number of parameter = N- D[7] S CMD CMD PA CMD PA PA N-2 PA N- P RESX CSX D/CX R/WX E D[7] Host [7] Host to LCD Driver [7] LCD to Host S CMD CMD PA CMD PA N-2 P PA PA N- S CMD CMD PA CMD PA N-2 P PA PA N- CMD Write command code PA Write parameter or RAM data Signals on D[7], D/CX, R/WX, E pins during CSX= are ignore Figure4 68-Series parallel bus protocol (write to register or display RAM) Page 29 of 2

30 6.4.2 Read Cycle/Sequence The read cycle means that the host reads information (commend or/and data) to the display via the interface. Each read cycle (E low-high-low sequence) consists of 3 control (D/CX, E, R/WX) and data (D[7 ]). D/CX bit is control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is low (= ) and vice versa it is data (= ) R/WX = RDX D[7], D[8] or D[5], D[7] The display asserts D[7], D[5], D[8] or D[7] lines when there is a falling edge of E The host reads D[7], D[5], D[8] or D[7] lines when there is a rising edge of E The display negates D[7], D[5], D[8] or D[7] lines Note E is an unsynchronized signal (It can be stopped). Figure5 68-Series Read Protocol D[7] Read S CMD CMD PA CMD Read display RAM data DM data data P RESX CSX D/CX R/WX E D[7] Host [7] Host to LCD Driver [7] LCD to Host S CMD CMD PA CM D DM data data P S Hi-Z Hi-Z CMD CM D Hi-Z S DM PA DM data data P P CMD Write command code PA Write parameter or RAM data Signals on D[7], D/CX, R/WX, E pins during CSX= are ignored Figure6 68-Series Parallel bus protocol (Read from register or display RAM) Page 3 of 2

31 6.5 Display Data Transfer Recovery If there is a break in data transmission by RESX pulse, while transferring a Command or Frame Memory Data or Multiple command Data, before Bit D of the byte has been completed, then DRIVER will reject the previous its and have reset the interface such that it will be ready to receive command data again when the chip select line (CSX) is next activated after RESX have been High state. See the following example. CSX S TB TB P Host (MCU to Driver) RESX SCL Wait for more than us SDA D/CX D7 D6 D5 D4 D3 D2 D/CX D7 D6 D5 D4 D3 D2 D D Command/parameter/Data SCL and SDA during RESX=L is invalid and next byte becomes command Figure7 Serial bus protocol, write mode interrupted by RESX If there is a break in data transmission by CSX pulse, while transferring a Command or Frame Memory Data or Multiple command data, before Bit D of the byte has been completed. Then the DRIVER will reject the previous bits and have reset the interface such that it will be ready to receive the same byte re-transmitted when the chip select line(csx) is next activated. See the following example. CSX S TB TB P Host (MCU to Driver) SCL SDA D/CX D7 D6 D5 D4 D/CX D7 D6 D5 D4 D3 D2 D D Command/parameter/ Data Break Command/parameter/Data Figure8 Serial bus protocol, write mode interrupted by CSX If, 2 or more parameter command is being sent and a break occurs while sending any parameter before the last one and if the host then sends a new command rather than re-transmitting the parameter that was interrupted, then the parameters that were successfully sent are stored and the parameter where the break occurred is rejected. The inter face is ready to receive next byte as show below. Note Break can be e.g. another command or noise pulse. Page 3 of 2

32 Break PARA is sucessfully sent but the PARA2 is breaked and need to be transferred again CMD PARA PARA2 CMD2 CMD PARA PARA2 PARA3 Command with st parameter(para) should be executed again to write remained parameter(para2 and PARA3) Figure9 Write interrupts recovery (serial interface) Break PARA is sucessfully sent but the other parameters are not sent and break ha CMD PARA CMD2 CMD PARA PARA2 PARA3 Command with st parameter(para) should be executed again to write remained parameter(para2 and PARA3) Figure2 Write interrupts recovery (both serial and parallel interface) Page 32 of 2

33 6.6 Display Data Transfer Pause It will be possible when transferring a Command, Frame Memory Data or Multiple Data to invoke a pause in the data transmission. If the Chip Select Line is released after a whole byte of a Frame Memory Data or Multiple Data has been completed, then the Display Module will wait and continue the Frame Memory Data or Data Transmission from the point where it was paused. If the Chip Select Line is released after a whole byte of a command has been completed, then the Display Module will receive either the command s parameters (if appropriate) or a new command when the Chip Select Line is next enabled as shown below SCEX S TB TB P Host (MCU to Driver) SCL SDA D/CX D7 D7 D5 D4 D3 D2 D D D/CX D7 D6 D5 D4 D3 D2 D D Command/parameter/Data Command/parameter/Data SCL and SDA during CSX=H is invalid Figure2 Serial interface Pause Protocol (pause by CSX) CSX D/CX RDX WRX D[7] D7 to D Command/ parameter Pause D7 to D Command/ parameter Figure22 Parallel bus Pause Protocol (paused by CSX) This applies to the following 4 conditions. Command-Pause-Command 2. Command-Pause- 3. -Pause-Command 4. -Pause- Page 33 of 2

34 6.7 Display Data Transfer Mode The data format is described for each interface. Data can be downloaded to the Frame Memory by 2 methods. Method The Image data is sent to the Frame Memory in successive Frame writes, each time the Frame Memory is filled, the Frame Memory pointer is reset to the start point and the next Frame is written. Method 2 Image Data is sent and at the end of each Frame Memory download, a command is sent to stop Frame Memory Write. Then Start Memory Write command is sent, and a new Frame is downloaded. Note. These apply to this Data Transfer Color mode on both Serial and Parallel interfaces. 2. The Frame Memory can contain both odd and even number of pixels for both Methods. Only complete pixel data will be stored in the Frame Memory. Page 34 of 2

35 6.8 RGB Interface 6.8. RGB Interface Selection The RGB interface mode is available for and the interface is selected by setting the VIPF[3] bits as following table. VIPF[3] RGB Interface Data Bus 8-bit RGB interface D[7] 6-bit RGB interface D[73], D[] 6-bitRGB interface D[72] Others Setting prohibited The display operation via RGB interface is synchronized with the VS, HS and PCLK signals. The RGB interface transfers the updated data to GRAM and the update area is defined by the window address function. The back porch and back porch are used to set the RGB interface timing. Parallel RGB Interface Set Table 8-bit data bus interface (D[7] is used), VIPF[3] = D7 D6 D5 D4 D3 D2 D D D9 D8 D7 D6 D5 D4 D3 D2 D D 8bpp Frame Memory Write R[5] R[4] R[3] R[2] R[] R[] G[5] G[4] G[3] G[2] G[] G[] B[5] B[4] B[3] B[2] B[] B[] 6-bit data bus interface (D[73] and D[] are used), VIPF[3] = D7 D6 D5 D4 D3 D D D9 D8 D7 D6 D5 D4 D3 D2 D 6bpp Frame Memory Write R[4] R[3] R[2] R[] R[] G[5] G[4] G[3] G[2] G[] G[] B[4] B[3] B[2] B[] B[] 6-bit data bus interface (D[72] is used), VIPF[3] = First Transfer Second Transfer Third Transfer D7 D6 D5 D4 D3 D2 D7 D6 D5 D4 D3 D2 D7 D6 D5 D4 D3 D2 8bpp Frame Memory Write R[5] R[4] R[3] R[2] R[] R[] G[5] G[4] G[3] G[2] G[] G[] B[5] B[4] B[3] B[2] B[] B[] Pixel clock (PCLK) is running all the time without stopping and it is used to entering VS, HS, EN and D[7] states when there is a rising edge of the PCLK. The PCLK can not be used as continues internal clock for other functions of the display module. Vertical synchronization (VS) is used to tell when there is received a new frame of the display. This is high enable and its state is read to the display module by a rising edge of the PCLK signal. Horizontal synchronization (HS) is used to tell when there is received a new line of the frame. This is low enable and its state is read to the display module by a rising edge of the PCLK signal. Page 35 of 2

36 Data Enable (EN) is used to tell when there is received RGB information that should be transferred on the display. This is a high enable and its state is read to the display module by a rising edge of the PCLK signal. D[7] are used to tell what is the information of the image that is transferred on the display (When EN= and there is a rising edge of PCLK). D[7] can be (low) or (high). These lines are read by a rising edge of the PCLK signal. VS Back porch period RAM data display area Moving picture display area Display period Front porch period HS PCLK EN D[7] Note Front porch period continues until the next input of VS. Note 2 Input PCLK throughout the operation. Note 3 Supply the VS, HS and PCLK with frequency that can meet the resolution requirement of panel. Figure23 GRAM Access Area by RGB Interface Page 36 of 2

37 6.8.2 RGB Interface Timing The timing chart of 8-/6-bit RGB interface mode is shown as below. Back porch frame Front porch VS VLW>=H HS PCLK EN D[7] HLW>=3DOTCLKs HS H PCLK EN DTST>=HLW D[7] Valid data VLW VS Low Width HLW HS Low Width DTST Data Transfer Startup Time Figure24 Timing Chart of Signals in 8-/6-bit RGB Interface Mode Page 37 of 2

38 The timing chart of 6-bit RGB interface mode is shown as below Back porch frame Front porch VS VLW>=H HS PCLK EN D[72] HLW>=3DOTCLKs HS H PCLK EN DTST>=HLW D[72] R G B R G B B R G B Valid data VLW VS Low Width HLW HS Low Width DTST Data Transfer Startup Time Note In 6-bit RGB interface mode, each dot of one pixel (R, G and B) is transferred in synchronization with PCLK. Note 2 In 6-bit RGB interface mode, set the cycles of VS, HS and EN to 3 multiples of PCLK. Figure25 Timing Chart of Signals in 6-bit RGB Interface Mod Page 38 of 2

39 6.8.3 RGB Interface Mode Set supplies a RGB interface with DE mode and can be controlled by external RCM[] pins. RCM RCM Resolution selection X MCU interface mode RGB interface() RGB interface(2) There are 2-kinds of RGB mode which is selected by RCM & RCM hardware pins. In RGB interface (RCM, RCM = ), writing data to frame memory is done by PCLK and Video Data Bus, when DE is high state. The external synchronization signals (PCLK, VS and HS) are used for internal display signals. So, controller (host) must always transfer PCLK, VS, HS and DE signals to driver. In RGB interface 2 (RCM, RCM = ), blanking porch setting of VS and HS signals are defined by RGBBPCTR (B5h)command. DE pin is used for data making. When DE pin is high, valid data is directly stored to frame memory. In the contrast, if DE pin is low, valid data will becomes and stored to frame memory. Page 39 of 2

40 6.9 Display Data Color Coding 6.9. Serial Interface Different display data formats are available for three colors depth supported by the LCM listed below. 4k colors, RGB bits input 65K colors, RGB bits input 262K colors, RGB bits input 3-pin 9-bit data protocol RESX ' IM2 CSX SPI4W =, IM[] = xx SDA Pixel n Pixel n+ D8 D7 D6 D5 D4 D3 D2 D D D8 D7 D6 D5 D4 D3 D2 D D D8 D7 D6 D5 D4 D3 D2 D D R R R R G G G G B B B B R2 R2 R2 R2 G2 G2 G2 G2 B2 B2 B2 B SCL 2-bit 2-bit Loo-Up Table for 496 Colors mapping (2-bit to 8 bit) 8-bit 8-bit Frame memory R G B R2 G2 B2 R3 G3 B3 Note pixel data with the 2-bits color depth information. Note 2 The most significant bits are Rx[3], Gx 3 and Bx 3 Note 3 The least significant bits arerx, Gx and Bx Note 4 X = don t care Can be set to or Figure26 Write data for RGB4-4-4 bits input 4-pin 8-bit Series data protocol RESX ' IM2 CSX SPI4W =, IM[]= xx SDA SCL Pixel n Pixel n+ D8 D7 D6 D5 D4 D3 D2 D D D8 D7 D6 D5 D4 D3 D2 D D D8 D7 D6 D5 D4 D3 D2 D D R 4 R 3 R 2 R R G 5 G 4 G 3 6-bit G 2 G G B 4 B 3 Loo-Up Table for 65k Colors mapping (6-bit to 8 bit) B 2 B B R2 4 R2 3 R2 2 R2 R2 G2 5 G2 4 G2 3 8-bit Frame memory R G B R2 G2 B2 R3 G3 B3 Note pixel data with the 6-bits color depth information. Page 4 of 2

41 Note 2 The most significant bits are Rx4, Gx5 and Bx4 Note 3 The least significant bits arerx, Gx and Bx Note 4 X = Don t care Can be set to or Figure27 Write data for RGB bits input 3-pin 9-bit Series data protocol RESX ' IM2 SPI4W =, IM[]= xx CSX Pixel n D8 D7 D6 D5 D4 D3 D2 D D D8 D7 D6 D5 D4 D3 D2 D D D8 D7 D6 D5 D4 D3 D2 D D SDA R 5 R 4 R 3 R 2 R R - - G 5 G 4 G 3 G 2 G G - - B 5 B 4 B 3 B 2 B B - - SCL 8-bit Frame memory R G B R2 G2 B2 R3 G3 B3 Figure28 Write data for RGB bits input 4-pin 8-bit Series data protocol RESX ' IM2 SPI4W =, IM[]= xx CSX D/CX Pixel n Pixel n+ D7 D6 D5 D4 D3 D2 D D D7 D6 D5 D4 D3 D2 D D D7 D6 D5 D4 D3 D2 D D SDA R 4 R 3 R 2 R R G 5 G 4 G 3 G 2 G G B 4 B 3 B 2 B B R2 4 R2 3 R2 2 R2 R2 G2 5 G2 4 G2 3 SCL 6-bit Loo-Up Table for 65k Colors mapping (6-bit to 8 bit) 8-bit Frame memory R G B R2 G2 B2 R3 G3 B3 Note pixel data with the 8-bits color depth information. Note 2 The most significant bits are Rx 5, Gx 5 and Bx 5 Note 3 The least significant bits arerx, Gx and Bx Note 4 X = Don t care Can be set to or Page 4 of 2

42 Read data for 3-W SPI RGB Host CSX (SPI CSX) RESX ' IM2 SPI4W =, IM[]= xx SCL SDA - R2Eh High-Z Driver SDA High-Z D23 D22 D2 D2 D9 D8 D7 D6 D23 D2 D D D22 D2 D2 D9 9 Dummy Clock -Pixel data Read Data format as below D23 D22 D2 D2 D9 D8 R R R R R R D7 D6 D5 D4 D3 D2 D D D9 D8 D7 D6 D5 D4 D3 D2 D D G G R R R R B B B B B B Note X = Don t care Can be set to or Read data for 4-W SPI RGB RESX ' IM2 SPI4W =, IM. IM= xx CSX Host SCL D/CX Driver SDA SDA - R2Eh High-Z High-Z D23 D22 D2 D2 D9 D8 D7 D6 D23 D2 D D D22 D2 D2 D9 8 Dummy Clock -Pixel data Read Data format as below D23 D22 D2 D2 D9 D8 D7 D6 D5 D4 D3 D2 D D D9 D8 D7 D6 D5 D4 D3 D2 D D R R R R R R G G R R R R B B B B B B Note X = Don t care Can be set to or Figure29 Read data for SPI RGB bits Page 42 of 2

43 bit Parallel Interface (IM2=, IM[] = ) Different display data formats are available for three colors depth supported by listed below 4k colors, RGB4-4-4-bits input 65K colors, RGB5-6-5-bits input 262K colors, RGB6-6-6-bits input 2 pixels (6 sub-pixels) per 3 transfer RESX IM/IM IM, IM = CSX D/CX WRX RDX R/WX 88-Series control pins 68-Series control pins E D7 R, Bit3 B, Bit3 G2, Bit3 R3, Bit3 D6 R, Bit2 B, Bit2 G2, Bit2 R3, Bit2 D5 R, Bit B, Bit G2, Bit R3, Bit D4 R, Bit B, Bit G2, Bit R3, Bit D3 G, Bit3 R2, Bit3 B2, Bit3 G3, Bit3 D2 G, Bit2 R2, Bit2 B2, Bit2 G3, Bit2 D G, Bit R2, Bit B2, Bit G3, Bit D G, Bit R2, Bit B2, Bit G3, Bit Pixel n Pixel n+ 2-bit 2-bit Loo-Up Table for 496 Colors mapping (2-bit to 8-bit) 8-bit 8-bit Frame Memoy R G B R 2 G 2 B 2 R 3 G 3 B 3 Note The data order is as follows, MSB=D7, LSB=D and picture data is MSB=Bit3, LSB=Bit for Red, Green and Blue data. Note 2 3-times transfer is used to transmit 2 pixels data with the 2-bits color depth information. Note 3 - = Don t care Can be set to or Figure3 Write 8-bit data for RGB bits input Page 43 of 2

44 There is pixel (3 sub-pixels) per 2 transfer IM, IM = 88-Series control pins 68-Series control pins R, Bit4 G, Bit2 R2, Bit4 G2, Bit2 R, Bit3 G, Bit R2, Bit3 G2, Bit R, Bit2 G, Bit R2, Bit2 G2, Bit R, Bit B, Bit4 R2, Bit B2, Bit4 R, Bit B, Bit3 R2, Bit B2, Bit3 G, Bit5 B, Bit2 G2, Bit5 B2, Bit2 G, Bit4 B, Bit G2, Bit4 B2, Bit G, Bit3 B, Bit G2, Bit3 B2, Bit Pixel n Pixel n+ 6-bit 6-bit Loo-Up Table for 65k Colors mapping (6-bit to 8-bit) 8-bit 8-bit Frame Memoy R G B R 2 G 2 B 2 R 3 G 3 B 3 Note The data order is as follows, MSB=D7, LSB=D and picture data is MSB=Bit5, LSB=Bit for Green and MSB=Bit4, LSB=Bit for Red and Blue data. Note 2 2-times transfer is used to transmit pixel data with the 6-bits color depth information. Note 3 - = Don t care Can be set to or Figure3 Write 8-bits data for RGB bits input Page 44 of 2

45 pixel (3 sub-pixels) per 3 transfer RESX IM/IM IM, IM = CSX D/CX WRX RDX R/WX E 88-Series control pins 68-Series control pins D7 R, Bit5 G, Bit5 B, Bit5 R2, Bit5 D6 R, Bit4 G, Bit4 B, Bit4 R2, Bit4 D5 R, Bit3 G, Bit3 B, Bit3 R2, Bit3 D4 R, Bit2 G, Bit2 B, Bit2 R2, Bit2 D3 R, Bit G, Bit B, Bit R2, Bit D2 R, Bit G, Bit B, Bit R2, Bit D D Pixel n Pixel n+ 8-bit 8-bit Frame Memoy R G B R 2 G 2 B 2 R 3 G 3 B 3 Note The data order is as follows, MSB=D7, LSB=D and picture data is MSB=Bit5, LSB=Bit for Red, Green and Blue data. Note 2 3-times transfer is used to transmit pixel data with the 8-bits color depth information. Note 3 - = Don t care Can be set to or Figure32 Write 8-bit data for RGB bits input Page 45 of 2

46 bit Parallel Interface (IM2=, IM, IM= ) Different display data formats are available for three colors depth supported by listed below 4k colors, RGB bits input 65K colors, RGB bits input 262K colors, RGB bits input pixels (3 sub-pixels) per transfer, 2-bits/pixel RESX IM/IM IM, IM = CSX D/CX WRX RDX R/WX E 88-Series control pins 68-Series control pins D D D D D - R, Bit3 R2, Bit3 R3, Bit3 R4, Bit3 D - R,Bit2 R2, Bit2 R3, Bit2 R4, Bit2 D9 - R,Bit R2, Bit R3, Bit R4, Bit D8 - R,Bit R2, Bit R3, Bit R4, Bit D7 G, Bit3 G2, Bit3 G3, Bit3 G4, Bit3 D6 G, Bit2 G2, Bit2 G3, Bit2 G4, Bit2 D5 G, Bit G2, Bit G3, Bit G4, Bit D4 G, Bit G2, Bit G3, Bit G4, Bit D3 B, Bit3 B2, Bit3 B3, Bit3 B4, Bit3 D2 B, Bit2 B2, Bit2 B3, Bit2 B4, Bit2 D B, Bit B2, Bit B3, Bit B4, Bit D B, Bit B2, Bit B3, Bit B4, Bit Pixel n Pixel n+ Pixel n+2 Pixel n+3 2-bit 2-bit Loo-Up Table for 496 Colors mapping (2-bit to 8-bit) 8-bit 8-bit Frame Memoy R G B R 2 G 2 B 2 R 3 G 3 B 3 Note The data order is as follows, MSB = D5, LSB = D and picture data is MSB = Bit3, LSB = Bit for Red, Green and Blue data. Note 2 = Don t care Can be set to or Figure33 Write 6-bit data for RGB4-4-4-bits input (4k-color) Page 46 of 2

47 pixel (3 sub-pixels) per transfer, 6-bits/pixel RESX IM/IM IM[] = CSX D/CX WRX RDX R/WX E 88-Series control pins 68-Series control pins D5 - R, Bit4 R2, Bit4 R3, Bit4 R4, Bit4 D4 - R, Bit3 R2, Bit3 R3, Bit3 R4, Bit3 D3 - R,Bit2 R2, Bit2 R3, Bit2 R4, Bit2 D2 - R,Bit R2, Bit R3, Bit R4, Bit D - R,Bit R2, Bit R3, Bit R4, Bit D - G, Bit5 G2, Bit5 G3, Bit5 G4, Bit5 D9 - G, Bit4 G2, Bit4 G3, Bit4 G4, Bit4 D8 - G, Bit3 G2, Bit3 G3, Bit3 G4, Bit3 D7 G, Bit2 G2, Bit2 G3, Bit2 G4, Bit2 D6 G, Bit G2, Bit G3, Bit G4, Bit D5 G, Bit G2, Bit G3, Bit G4, Bit D4 B, Bit4 B2, Bit4 B3, Bit4 B4, Bit4 D3 B, Bit3 B2, Bit3 B3, Bit3 B4, Bit3 D2 B, Bit2 B2, Bit2 B3, Bit2 B4, Bit2 D B, Bit B2, Bit B3, Bit B4, Bit D B, Bit B2, Bit B3, Bit B4, Bit Pixel n Pixel n+ Pixel n+2 Pixel n+3 6-bit 6-bit Loo-Up Table for 496 Colors mapping (6-bit to 8-bit) 8-bit 8-bit Frame Memoy R G B R 2 G 2 B 2 R 3 G 3 B 3 Note The data order is as follows, MSB = D5, LSB = D and picture data is MSB = Bit5, LSB = Bit for Red and Blue and MSB=Bit5, LSB=Bit for Green data. Note 2 = Don t care Can be set to or Figure34 Write 6-bit data for RGB bits input (65k colors) Page 47 of 2

48 2 pixels (6 sub-pixels) per 2 transfer, 8-bits/pixel RESX IM/IM IM, IM = CSX D/CX WRX RDX R/WX E 88-Series control pins 68-Series control pins D5 - R, Bit5 B, Bit5 G2, Bit5 R3, Bit5 D4 - R, Bit4 B, Bit4 G2, Bit4 R3, Bit4 D3 - R, Bit3 B, Bit3 G2, Bit3 R3, Bit3 D2 - R,Bit2 B, Bit2 G2, Bit2 R3, Bit2 D - R,Bit B, Bit G2, Bit R3, Bit D - R,Bit B, Bit G2, Bit R3, Bit D9 D D7 G, Bit5 R2, Bit5 B2, Bit5 G3, Bit5 D6 G, Bit4 R2, Bit4 B2, Bit4 G3, Bit4 D5 G, Bit3 R2, Bit3 B2, Bit3 G3, Bit3 D4 G, Bit2 R2, Bit2 B2, Bit2 G3, Bit2 D3 G, Bit R2, Bit B2, Bit G3, Bit D2 G, Bit R2, Bit B2, Bit G3, Bit D D Pixel n Pixel n+ 8-bit 8-bit Frame Memoy R G B R 2 G 2 B 2 R 3 G 3 B 3 Note The data order is as follows, MSB = D5, LSB = D and picture data is MSB = Bit5, LSB = Bit for Red and Green and Blue. Note 2 = Don t care Can be set to or Figure35 Write 6-bit data for RGB bits input (262K colors) Page 48 of 2

49 bit Parallel Interface (IM2= 2, IM, IM= ) Different display data formats are available for three colors depth supported by listed below 262K colors, RGB6-6-6-bits input 2 pixels (6 sub-pixels) per 4 transfer, 8-bits/pixel RESX IM/IM IM, IM = CSX D/CX WRX RDX R/WX E 88-Series control pins 68-Series control pins D8 - R, Bit5 G, Bit2 R2, Bit5 G2, Bit2 D7 R, Bit4 G, Bit R2, Bit4 G2, Bit D6 R, Bit3 G, Bit R2, Bit3 G2, Bit D5 R, Bit2 B, Bit5 R2, Bit2 B2, Bit5 D4 R, Bit B, Bit4 R2, Bit B2, Bit4 D3 R, Bit B, Bit3 R2, Bit B2, Bit3 D2 G, Bit5 B, Bit2 G2, Bit5 B2, Bit2 D G, Bit4 B, Bit G2, Bit4 B2, Bit D G, Bit3 B, Bit G2, Bit3 B2, Bit Pixel n Pixel n+ 8-bit 8-bit Frame Memoy R G B R 2 G 2 B 2 R 3 G 3 B 3 Note The data order is as follows, MSB = D8, LSB = D and picture data is MSB = Bit5, LSB = Bit for Red and Green and Blue data. Note 2 = Don t care Can be set to or Figure36 Write 9-bit data for RGB bits input(262k-color) Page 49 of 2

50 bit Parallel Interface (IM2=, IM, IM= ) Different display data formats are available for three colors depth supported by listed below 4k colors, RGB bits input 65K colors, RGB bits input 262K colors, RGB bits input pixel (3 sub-pixels) per transfer, 2-bits/pixel RESX IM/IM IM, IM = CSX D/CX WRX RDX R/WX E 88-Series control pins 68-Series control pins D D D D - R, Bit3 R2, Bit3 R3, Bit3 R4, Bit3 D - R,Bit2 R2, Bit2 R3, Bit2 R4, Bit2 D9 - R,Bit R2, Bit R3, Bit R4, Bit D8 - R,Bit R2, Bit R3, Bit R4, Bit D7 D6 G, Bit3 G2, Bit3 G3, Bit3 G4, Bit3 G, Bit2 G2, Bit2 G3, Bit2 G4, Bit2 D5 G, Bit G2, Bit G3, Bit G4, Bit D4 G, Bit G2, Bit G3, Bit G4, Bit D3 B, Bit3 B2, Bit3 B3, Bit3 B4, Bit3 D2 B, Bit2 B2, Bit2 B3, Bit2 B4, Bit2 D B, Bit B2, Bit B3, Bit B4, Bit D B, Bit B2, Bit B3, Bit B4, Bit Pixel n Pixel n+ Pixel n+2 Pixel n+3 2-bit 2-bit Loo-Up Table for 496 Colors mapping (2-bit to 8-bit) 8-bit 8-bit Frame Memoy R G B R 2 G 2 B 2 R 3 G 3 B 3 Note The data order is as follows, MSB = D, LSB = D and picture data is MSB = Bit3, LSB = Bit for Red, Green and Blue data. Note 2 = Don t care Can be set to or Figure37 Write 8-bits data for RGB bits input (4k colors) Page 5 of 2

51 Note The data order is as follows, MSB = D5, LSB = D and picture data is MSB = Bit5, LSB = Bit for Green and MSB=Bit 4, LSB=Bit for Blue data. Note 2 = Don t care Can be set to or Figure38 Write 8-bits data for RGB bits input (65k-color) Page 5 of 2

52 Note The data order is as follows, MSB = D7, LSB = D and picture data is MSB = Bit5, LSB = Bit for Red, Green and Blue data. Note 2 = Don t care Can be set to or Figure39 Write 8-bit data for RGB bits input (262K colors) Page 52 of 2

53 7. Display Data RAM a-si TFT LCD Single Chip Driver 7. Configuration The display data RAM stores display dots and consists of 384,54 bits (32x8x62 bits). There is no restriction on access to the RAM even when the display data on the same address is loaded to DAC. There will be no abnormal visible effect on the display when there is a simultaneous Panel Read and Interface Read or Write to the same location of the Frame Memory. Display Data RAM Organization LCD Glass (32 x RGB x 62) MPU I/F Look-up table Row Address Counter Latch Display Data RAM (32 x 62 x 8-bit) Liner Address Counter Column Address Counter Scan Address Counter Host Interface Page 53 of 2

54 7.2 Memory to Display Address Mapping RGB x 32 resolution (GM[2] =, SMX=SMY=SRGB= ) Pixel Pixel Piexel3 Piexel32 Gate Source Out S S2 S3 S4 S5 S S39 S392 S393 S394 S395 S396 RGB RA SA Order MY=MY= ML= ML= 32 R G B R2 G2 B R3 G3 B3 R32 G32 B RGB= RGB= RGB= RGB= CA MX MX RGB= RGB= RGB= RGB= Page 54 of 2

55 RGB x 3 resolution(gm[2] =, SMX=SMY=SRGB= ) Pixel Pixel Piexel29 Piexel3 Gate Source Out S7 S8 S9 S S S S39 S392 S393 S394 S395 S396 RGB RA SA Order MY=MY= ML= ML= 3 R G B R2 G2 B R29 G29 B29 R3 G3 B RGB= RGB= RGB= RGB= CA MX MX RGB= RGB= RGB= RGB= Page 55 of 2

56 RGB x 6 resolution (GM[2] =, SMX=SMY=SRGB= ) Note RA = Row Address CA = Column Address SA = Scan Address MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command ML = Scan direction parameter, D4 parameter of MADCTL command RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command Page 56 of 2

57 RGB x 6 resolution (GM[2] =, SMX=SMY=SRGB= ) Note RA = Row Address CA = Column Address SA = Scan Address MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command ML = Scan direction parameter, D4 parameter of MADCTL command RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command Page 57 of 2

58 RGB x 28 resolution (GM[2] =, SMX=SMY=SRGB= ) Note RA = Row Address CA = Column Address SA = Scan Address MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command ML = Scan direction parameter, D4 parameter of MADCTL command RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command Page 58 of 2

59 RGB x 62 resolution (GM[2] =, SMX=SMY=SRGB= ) Note RA = Row Address CA = Column Address SA = Scan Address MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command ML = Scan direction parameter, D4 parameter of MADCTL command RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command Page 59 of 2

60 7.3 MCU to memory write/read direction (Address Counter) The address counter set the addresses of the display data RAM for writing and reading. Data is written pixel-wise into the RAM matrix of DRIVER. The data for one pixel or two pixels is collected(rgb bit), according to the data formats. As soon as this pixel-data information is complete the Write access is activated on the RAM. The locations of RAM are addressed by the address pointers. When GM=, 32RGB x 62, the address ranges are X= to X=3 (83h) and Y= to Y=6 (Ah). Addresses outside these ranges are not allowed. Before writing to the RAM a window must be defined into which will be written. The window is programmable via the command register XS, YS designating the start address and XE, YE designating the end address. For example the whole display contents will be written, the window is defined by the following values XS=(h) YS=(h) and XE=3(83h), YE=6(Ah) In vertical addressing mode (MV=), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps around to YS and X increments to address the next column. In horizontal addressing mode (V=), the X-address increments after each byte, after the last X-address(X=XE), X wraps around to XS and Y increments to address the next row. After the every last address (X=XE and Y=YE) the address pointers wrap around to address (X=XS and Y=YS) For flexibility in handling a wide variety of display architectures, the commands CASET, RASET and MADCTR, define flags MX and MY, which allows mirroring of the X-address and Y-address. All combinations of flags are allowed. Below table shows the available combinations of writing to the display RAM. When MX, MY and MV will be changed the data bust be rewritten to the display RAM. For each image orientation, the controls for the column and page counters apply as below - Condition Column Counter Row Counter When RAMWR/RAMRD command is accepted Return to Start Column (XS) Return to Start Row (YS) Complete Pixel Read/Write action Increment by No change The Column counter value is larger than End Column(XE) Return to Start Increment by Column (XS) The Column counter value is larger than End Column (XE) and the Row counter value is larger than End Row(YE) Return to Start Column (XS) Return to Start Row (YS) Page 6 of 2

61 Figure4 Frame Data Write Direction According to the MADCTR parameters (MV, MX and MY) Display Data Direction MADCTR MV MX MY Image in the Memory (MPU) Image in the Driver (DDRAM) B H/W position(,) B Normal E X-Y address (,) X CASET Y RASET E B H/W position(,) E Y-Mirror E X-Y address (,) X CASET Y RASET B X-Mirror B H/W position(,) B X-Y address (,) X CASET Y RASET E E B H/W position(,) E X-Mirror Y-Mirror E B X-Y address (,) X CASET Y RASET B H/W position(,) B X-Y Exchange E X-Y address (,) X CASET Y RASET E X-Y Exchange Y-Mirror B E H/W position(,) X-Y address (,) X CASET Y RASET B E XY Exchange B H/W position(,) B X-Y address (,) X CASET Y RASET E E XY Exchange B E H/W position(,) E B X-Y address (,) X CASET Y RASET Page 6 of 2

62 8. Tearing Effect Output Line a-si TFT LCD Single Chip Driver The Tearing Effect output line supplies to the MCU a Panel synchronization signal. This signal can be enabled or disabled by the Tearing Effect Line Off & On commands. The mode of the Tearing Effect Signal is defined by the of the Tearing Effect Line On command. The signal can be used by the MCU to synchronize Frame Memory Writing when displaying video images. 8. Tearing Effect Line Modes Mode, the Tearing Effect Output signal consists of V-Sync information only tvdl tvdh Vertical Time Scale tvdh = The LCD display is not updated from the Frame Memory. Tvdl = The LCD display is updated from the Frame Memory (except Invisible Line see below). Mode 2, the Tearing Effect Output signal consists of V-Sync and H-Sync information, There is one V-sync and 62 H-sync pulses per field tvdh tvdl V-Sync Invisible Line st Line 62th Line V-Sync t hdh = The LCD display is not updated from the Frame Memory. T hdl = The LCD display is updated from the Frame Memory (except Invisible Line see above). Bottom Line st Line 2 nd Line TE (mode 2) TE (mode ) Note During Sleep In Mode, the Tearing Effect Output Pin is active Low. Page 62 of 2

63 8.2 Tearing Effect Line Timing The Tearing Effect signal is described below t vdl t vdh Vertical Timing Horizontal Timing t hdl t hdh Table 8.2. AC characteristics of Tearing Effect Signal Idle Mode Off/On (Frame Rate = 58.9Hz) Symbol min max unit descritpion tvdl Vertical Timing Low Duration 3 - Ms tvdh Vertical Timing High Duration - µs thdl Horizontal Timing Low Duration 33 - µs thdh Horizontal Timing High Duration 25 5 µs Notes. The timings in Table 8.2. apply when MADCTL B4= and B4= 2. The signal s rise and fall times (tf, tr) are stipulated to be equal to or less than 5ns. Figure4 Rise and fall times t r t f 8% 8% 2% 2% The Tearing Effect Output Line is fed back to the MCU and should be used as shown below to avoid Tearing Effect Page 63 of 2

64 8.2. Example MCU Write is Faster than Panel Read Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of the Tearing Effect Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame refresh has a complete new image Example 2 MCU Write is slower than Panel Read The MCU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync Page 64 of 2