ILI9335. a-si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color. Datasheet

Transcription

1 a-si TFT LC Single Chip river atasheet Version: V008 ocument No: S_V008pdf ILI TECHNOLOGY CORP 8F, No38, Taiyuan St, Jhubei City, Hsinchu County 302, Taiwan, ROC Tel ; Fax

2 Table of Contents Section Page 1 Introduction 7 2 Features 8 3 Block iagram 10 4 Pin escriptions 11 5 Pad Arrangement and Coordination 6 Block escription 25 7 System Interface Interface Specifications Input Interfaces i80/18-bit System Interface i80/-bit System Interface i80/9-bit System Interface i80/8-bit System Interface Serial Peripheral Interface (SPI) VSYNC Interface RGB Input Interface RGB Interface RGB Interface Timing Moving Picture Mode bit RGB Interface bit RGB Interface bit RGB Interface47 76 Interface Timing 49 8 Register escriptions Registers Access Instruction escriptions Index (IR) I code (R00h) river Output Control (R01h) LC riving Wave Control (R02h) Entry Mode (R03h) bits ata Format Selection (R05h) isplay Control 1 (R07h) isplay Control 2 (R08h) isplay Control 3 (R09h) isplay Control 4 (R0Ah) RGB isplay Interface Control 1 (R0Ch) 65 Page 2 of 1 Version: 008

3 82 Frame Marker Position (R0h) RGB isplay Interface Control 2 (R0Fh) Power Control 1 (R10h) Power Control 2 (R11h) Power Control 3 (Rh) Power Control 4 (Rh) GRAM Horizontal/Vertical Address Set (R20h, R21h) Write ata to GRAM (R22h) Read ata from GRAM (R22h) Power Control 7 (R29h) Frame Rate and Color Control (R2Bh) Gamma Control (R30h ~ R3h) Horizontal and Vertical RAM Address Position (R50h, R51h, R52h, R53h) Gate Scan Control (R60h, R61h, R6Ah) Partial Image 1 isplay Position (R80h) Partial Image 1 RAM Start/End Address (R81h, R82h) Partial Image 2 isplay Position (R83h) Partial Image 2 RAM Start/End Address (R84h, R85h) Panel Interface Control 1 (R90h) Panel Interface Control 2 (R92h) Panel Interface Control 4 (R95h) Panel Interface Control 5 (R97h) OTP VCM Programming Control (RA1h) OTP VCM Status and Enable (RA2h) OTP Programming I Key (RA5h) eep stand by control (RE6h) 82 9 OTP Programming Flow GRAM Address Map & Read/Write Window Address Function 90 Gamma Correction 91 Application 99 1 Configuration of Power Supply Circuit 99 2 isplay ON/OFF Sequence Standby and Sleep Mode Power Supply Configuration Voltage Generation Applied Voltage to the TFT panel Partial isplay Function Electrical Characteristics 107 Page 3 of 1 Version: 008

4 141 Absolute Maximum Ratings C Characteristics Reset Timing Characteristics AC Characteristics i80-system Interface Timing Characteristics Serial ata Transfer Interface Timing Characteristics RGB Interface Timing Characteristics 110 Revision History 1 Page 4 of 1 Version: 008

5 Figures FIGURE1 SYSTEM INTERFACE AN RGB INTERFACE CONNECTION 28 FIGURE2 18-BIT SYSTEM INTERFACE ATA FORMAT 29 FIGURE3 -BIT SYSTEM INTERFACE ATA FORMAT 30 FIGURE4 9-BIT SYSTEM INTERFACE ATA FORMAT 31 FIGURE5 8-BIT SYSTEM INTERFACE ATA FORMAT 32 FIGURE 6 ATA FORMAT OF SPI INTERFACE 34 FIGURE7 ATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI) 35 FIGURE8 ATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI), TRI= 1 AN FM= 10 ) 36 FIGURE9 ATA TRANSMISSION THROUGH VSYNC INTERFACE) 37 FIGURE10 MOVING PICTURE ATA TRANSMISSION THROUGH VSYNC INTERFACE 37 FIGURE11 OPERATION THROUGH VSYNC INTERFACE 38 FIGURE TRANSITION FLOW BETWEEN VSYNC AN INTERNAL CLOCK OPERATION MOES 40 FIGURE RGB INTERFACE ATA FORMAT 41 FIGURE14 GRAM ACCESS AREA BY RGB INTERFACE 42 FIGURE TIMING CHART OF SIGNALS IN 18-/-BIT RGB INTERFACE MOE 43 FIGURE TIMING CHART OF SIGNALS IN 6-BIT RGB INTERFACE MOE 44 FIGURE EXAMPLE OF UPATE THE STILL AN MOVING PICTURE 45 FIGURE18 INTERNAL CLOCK OPERATION/RGB INTERFACE MOE SWITCHING 48 FIGURE19 GRAM ACCESS BETWEEN SYSTEM INTERFACE AN RGB INTERFACE 48 FIGURE20 RELATIONSHIP BETWEEN RGB I/F SIGNALS AN LC RIVING SIGNALS FOR PANEL 50 FIGURE21 REGISTER SETTING WITH SERIAL PERIPHERAL INTERFACE (SPI) 51 FIGURE22 REGISTER SETTING WITH I80 SYSTEM INTERFACE 52 FIGURE 23 REGISTER REA/WRITE TIMING OF I80 SYSTEM INTERFACE 53 FIGURE24 GRAM ACCESS IRECTION SETTING 58 FIGURE25 -BIT MPU SYSTEM INTERFACE ATA FORMAT 59 FIGURE26 8-BIT MPU SYSTEM INTERFACE ATA FORMAT 60 FIGURE 27 ATA REA FROM GRAM THROUGH REA ATA REGISTER IN 18-/-/9-/8-BIT INTERFACE MOE 72 FIGURE 28 GRAM ATA REA BACK FLOW CHART 73 FIGURE 29 GRAM ACCESS RANGE CONFIGURATION 76 FIGURE30 GRAM REA/WRITE TIMING OF I80-SYSTEM INTERFACE 85 FIGURE31 I80-SYSTEM INTERFACE WITH 18-/-/9-BIT ATA BUS (SS= 0, BGR= 0 ) 87 FIGURE32 I80-SYSTEM INTERFACE WITH 8-BIT ATA BUS (SS= 0, BGR= 0 ) 88 FIGURE 33 I80-SYSTEM INTERFACE WITH 18-/9-BIT ATA BUS (SS= 1, BGR= 1 ) 89 FIGURE 34 GRAM ACCESS WINOW MAP 90 FIGURE 35 GRAYSCALE VOLTAGE GENERATION 91 FIGURE 36 GRAYSCALE VOLTAGE AJUSTMENT 92 FIGURE 37 GAMMA CURVE AJUSTMENT 93 FIGURE 38 EXAMPLE OF RMP(N)0~5 EFINITION 95 Page 5 of 1 Version: 008

6 FIGURE 39 RELATIONSHIP BETWEEN SOURCE OUTPUT AN VCOM 98 FIGURE 40 RELATIONSHIP BETWEEN GRAM ATA AN OUTPUT LEVEL 98 FIGURE 41 POWER SUPPLY CIRCUIT BLOCK 100 FIGURE 42 ISPLAY ON/OFF REGISTER SETTING SEQUENCE 101 FIGURE 43 STANY/SLEEP MOE REGISTER SETTING SEQUENCE 102 FIGURE 44 POWER SUPPLY ON/OFF SEQUENCE 103 FIGURE 45 VOLTAGE CONFIGURATION IAGRAM 104 FIGURE 46 VOLTAGE OUTPUT TO TFT LC PANEL 105 FIGURE 47 PARTIAL ISPLAY EXAMPLE 106 FIGURE 48 I80-SYSTEM BUS TIMING 109 FIGURE 49 SPI SYSTEM BUS TIMING 110 FIGURE50 RGB INTERFACE TIMING111 Page 6 of 1 Version: 008

7 1 Introduction a-si TFT LC Single Chip river is a 262,144-color one-chip SoC driver for a-tft liquid crystal display with resolution of 240RGBx320 dots, comprising a 720-channel source driver, a 320-channel gate driver, 2,800 bytes RAM for graphic data of 240RGBx320 dots, and power supply circuit has four kinds of system interfaces which are i80-system MPU interface (8-/9-/-/18-bit bus width), VSYNC interface (system interface + VSYNC, internal clock, [:0]), serial data transfer interface (SPI), RGB 6-/-/18-bit interface (OTCLK, VSYNC, HSYNC, ENABLE, [:0]) In RGB interface and VSYNC interface mode, the combined use of high-speed RAM write function and widow address function enables to display a moving picture at a position specified by a user and still pictures in other areas on the screen simultaneously, which makes it possible to transfer display the refresh data only to minimize data transfers and power consumption can operate with 5V I/O interface voltage, and an incorporated voltage follower circuit to generate voltage levels for driving an LC The also supports a function to display in 8 colors and a sleep mode, allowing for precise power control by software and these features make the an ideal LC driver for medium or small size portable products such as digital cellular phones, smart phone, PA and PMP where long battery life is a major concern Page 7 of 1 Version: 008

8 2 Features a-si TFT LC Single Chip river Single chip solution for a liquid crystal QVGA TFT LC display 240RGBx320-dot resolution capable with real 262,144 display color Support MVA (Multi-domain Vertical Alignment) wide view display Incorporate 720-channel source driver and 320-channel gate driver Internal 2,800 bytes graphic RAM System interfaces i80 system interface with 8-/ 9-/-/18-bit bus width Serial Peripheral Interface (SPI) RGB interface with 6-/-/18-bit bus width (VSYNC, HSYNC, OTCLK, ENABLE, [:0]) VSYNC interface (System interface + VSYNC) Internal oscillator and hardware reset Reversible source/gate driver shift direction Window address function to specify a rectangular area for internal GRAM access Bit operation function for facilitating graphics data processing Bit-unit write data mask function Pixel-unit logical/conditional write function Abundant functions for color display control γ-correction function enabling display in 262,144 colors Line-unit vertical scrolling function Partial drive function, enabling partially driving an LC panel at positions specified by user Incorporate step-up circuits for stepping up a liquid crystal drive voltage level up to 6 times (x6) Power saving functions 8-color mode standby mode sleep mode deep stand by mode Low -power consumption architecture Low operating power supplies: IOVcc = 5V ~ 36 V (interface I/O) VCI = 25V ~ 36 V (analog) LC Voltage drive: Source/VCOM power supply voltage VH - GN = 45V ~ 60 VCL GN = -20V ~ -30V VCI VCL 60V Gate driver output voltage VGH - GN = 10V ~ 20V VGL GN = -5V ~ -V Page 8 of 1 Version: 008

9 VGH VGL 30V VCOM driver output voltage VCOMH = (VCI+02)V ~ (VH-02)V VCOML = (VCL+02)V ~ 0V VCOMH-VCOML 60V a-tft LC storage capacitor: Cst only Page 9 of 1 Version: 008

10 3 Block iagram IOVCC IM[3:0] nreset Index Register (IR) ncs nwr/scl n RS SI SO MPU I/F 18-bit -bit 9-bit 8-bit 18 7 Control Register (CR) Address Counter (AC) LC Source river S[720:1] [:0] SPI I/F HSYNC VSYNC OTCLK ENABLE TEST1 TEST2 TEST3 TS[8:0] RGB I/F 18-bit -bit 6-bit VSYNC I/F Graphics Operation Read Latch Write Latch 18 V63 ~ 0 Grayscale Reference Voltage VREG1OUT VGS Graphics RAM (GRAM) UMMY20~27 VCC V GN Regulator RC-OSC Timing Controller LC Gate river G[320:1] UMMY1~ VCI VCI1 Charge-pump Power Circuit VCOM Generator VCOM GN C11A C11B VH CA CB CA CB VCL C21A C21B C22A C22B VGH VGL VCOMH VCOML Page 10 of 1 Version: 008

11 4 Pin escriptions Pin Name I/O Type escriptions Input Interface Select the MPU system interface mode IM3 IM2 IM1 IM0 MPU-Interface Mode Pin in use Setting invalid Setting invalid i80-system -bit interface [:10], [8:1] i80-system 8-bit interface [:10] IM3, IM2, IM1, IM0/I I IOVcc I Serial Peripheral Interface (SPI) SI, SO * Setting invalid Setting invalid Setting invalid i80-system 18-bit interface [:0] i80-system 9-bit interface [:9] 1 1 * * Setting invalid When the serial peripheral interface is selected, IM0 pin is used for the device code I setting A chip select signal ncs I MPU IOVcc Low: the is selected and accessible High: the is not selected and not accessible Fix to the GN level when not in use A register select signal RS I MPU IOVcc Low: select an index or status register High: select a control register Fix to either IOVcc or GN level when not in use A write strobe signal and enables an operation to write data when the signal is low nwr/scl I MPU IOVcc Fix to either IOVcc or GN level when not in use SPI Mode: Synchronizing clock signal in SPI mode n I MPU IOVcc A read strobe signal and enables an operation to read out data when the signal is low Fix to either IOVcc or GN level when not in use nreset I MPU IOVcc A reset pin Initializes the with a low input Be sure to execute a power-on reset after supplying power SI I MPU IOVcc SPI interface input pin The data is latched on the rising edge of the SCL signal SO O MPU IOVcc SPI interface output pin The data is outputted on the falling edge of the SCL signal Let SO as floating when not used An 18-bit parallel bi-directional data bus for MPU system interface mode 8-bit I/F: [:10] is used 9-bit I/F: [:9] is used -bit I/F: [:10] and [8:1] is used [:0] I/O MPU IOVcc 18-bit I/F: [:0] is used 18-bit parallel bi-directional data bus for RGB interface operation 6-bit RGB I/F: [:] are used -bit RGB I/F: [:] and [11:1] are used 18-bit RGB I/F: [:0] are used Unused pins must be fixed to GN level ENABLE I MPU IOVcc ata ENEABLE signal for RGB interface operation Low: Select (access enabled) Page 11 of 1 Version: 008

12 Pin Name I/O Type escriptions High: Not select (access inhibited) The EPL bit inverts the polarity of the ENABLE signal Fix to either IOVcc or GN level when not in use ot clock signal for RGB interface operation OTCLK I Fix to the GN level when not in use MPU PL = 0 : Input data on the rising edge of OTCLK IOVcc PL = 1 : Input data on the falling edge of OTCLK VSYNC I Frame synchronizing signal for RGB interface operation Fix to the GN level when not in use MPU VSPL = 0 : Active low IOVcc VSPL = 1 : Active high HSYNC I Line synchronizing signal for RGB interface operation Fix to the GN level when not in use MPU HSPL = 0 : Active low IOVcc HSPL = 1 : Active high FMARK O Output a frame head pulse signal MPU The FMARK signal is used when writing RAM data in synchronization with frame Leave IOVcc the pin open when not in use LC riving signals Source output voltage signals applied to liquid crystal To change the shift direction of signal outputs, use the SS bit S720~S1 O LC SS = 0, the data in the RAM address h00000 is output from S1 SS = 1, the data in the RAM address h00000 is output from S720 S1, S4, S7, display red (R), S2, S5, S8, display green (G), and S3, S6, S9, display blue (B) (SS = 0) G320~G1 O LC Gate line output signals VGH: the level selecting gate lines VGL: the level not selecting gate lines VCOM O TFT common A supply voltage to the common electrode of TFT panel electrode VCOM is AC voltage alternating signal between the VCOMH and VCOML levels VCOMH O Stabilizing capacitor The high level of VCOM AC voltage Connect to a stabilizing capacitor VCOML O Stabilizing The low level of VCOM AC voltage Adjust the VCOML level with the VV bits capacitor Connect to a stabilizing capacitor VGS I GN or Reference level for the grayscale voltage generating circuit The VGS level can be external changed by connecting to an external resistor resistor Charge-pump and Regulator Circuit VCI I Power A supply voltage to the analog circuit Connect to an external power supply of 25 ~ supply 36V VCC I Power A supply voltage to the digital circuit Connect to an external power supply of 25 ~ supply 36V VCI1 O An internal reference voltage for the step-up circuit1 within the respective specification Stabilizing The amplitude between VCI and GN is determined by the VC[2:0] bits capacitor Make sure to set the VCI1 voltage so that the VH, VGH and VGL voltages are set VH O Stabilizing capacitor Power supply for the source driver and Vcom drive VGH O Stabilizing capacitor Power supply for the gate driver VGL O Stabilizing capacitor Power supply for the gate driver VCL O Stabilizing VCOML driver power supply capacitor VCL = 05 ~ VCI Place a stabilizing capacitor between GN C11A, C11B I/O Step-up Capacitor connection pins for the step-up circuit 1 Page of 1 Version: 008

13 Pin Name I/O Type escriptions CA, CB capacitor CA, CB Step-up C21A, C21B I/O capacitor C22A, C22B Capacitor connection pins for the step-up circuit 2 Output voltage generated from the reference voltage VREG1OUT I/O Stabilizing The voltage level is set with the VRH bits capacitor VREG1OUT is (1) a source driver grayscale reference voltage, (2) VcomH level reference voltage, and (3) Vcom amplitude reference voltage Connect to a stabilizing capacitor VREG1OUT = 30 ~ (VH 05)V Power Pads A supply voltage to the interface pins: IOVCC I IM[3:0], nreset, ncs, nwr, n, RS, [:0], VSYNC, HSYNC, OTCLK, Power ENABLE, SCL, SI, SO supply IOVcc = 5 ~ 36V In case of COG, connect to Vcc on the FPC if IOVcc=Vcc, to prevent noise V O Power igital circuit power pad Connect these pins with the 1uF capacitor GN I Power GN for the digital side: GN = 0V In case of COG, connect to GN on the FPC supply to prevent noise AGN I Power AGN for the analog side: AGN = 0V In case of COG, connect to GN on the FPC supply to prevent noise VGMMA1, 62 O - Test pad Leave these pins as open VGLMY1~4 O Unused gate lines Connect unused gate lines to fix the level at VGL Test Pads UMMY3, 5~27,30, ummy pad Leave these pins as open Short circuited within the chip for COG contact resistance measurement UMMYR UMMYR1,2, 28, pins are short circuited as below: UMMYR1 and UMMYR29 UMMYR2 and UMMYR28 UMMY - - ummy pad and no output (no gold bump) IOVCCUM O Connect unused interface and test pins to these pins on the glass to fix voltage AGNUM1~6 O - levels Leave open when not used GNUM1~7 O - TESTO1~ O Open Test pins Leave them open TEST1, 2, 3 I IOGN Test pins (internal pull low) Connect to GN or leave these pins as open TS0~8 I OPEN Test pins (internal pull low) Leave them open TSO O OPEN Test pins Leave it open or short to ground TEST_EN I OPEN Test pins Leave it open or short to ground Page of 1 Version: 008

14 Liquid crystal power supply specifications Table 1 No Item escription 1 TFT Source river 720 pins (240 x RGB) 2 TFT Gate river 320 pins 3 TFT isplay s Capacitor Structure Cst structure only (Common VCOM) S1 ~ S720 V0 ~ V63 grayscales 4 Liquid Crystal rive Output G1 ~ G320 VGH - VGL VCOM VCOMH - VCOML: Amplitude = electronic volumes 5 Input Voltage IOVcc 5 ~ 360V VCI 250 ~ 360V VH 45V ~ 60V VGH 10V ~ 20V 6 Liquid Crystal rive Voltages VGL -5V ~ -V VCL -19V ~ -30V VGH - VGL Max 30V VCI - VCL Max 60V VH VCI1 x2 7 Internal Step-up Circuits VGH VCI1 x4, x5, x6 VGL VCI1 x-3, x-4, x-5 VCL VCI1 x-1 Page 14 of 1 Version: 008

15 5 Pad Arrangement and Coordination Page of 1 Version: 008

16 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 1 GNUM IOVCC VGS UMMYR IOVCC AGN UMMYR IOVCC AGN TESTO[1] IOVCC AGN TESTO[2] IOVCC AGN TESTO[3] IOVCC AGN TESTO[4] IOVCC AGN TESTO[5] IOVCC AGN TESTO[6] [8] AGN TESTO[7] [7] VCOMH TESTO[8] [6] VCOMH UMMY TS[4] VCOMH UMMY TS[3] VCOMH TESTO[9] [5] VCOMH TESTO[10] [4] VCOMH TESTO[11] [3] VCOM TESTO[] TS[2] VCOM GN TS[1] VCOM GN [2] VCOM GN [1] VCOM GN [0] VCOM GN TS[0] VCOML GN TSO VCOML GN GNUM VCOML GN ncs VCOML GN RS VCOML GN nwr/scl VCOML TESTO[] n VCOML TESTO[14] nreset C11A GNUM SO C11A IM0/I SI C11A IM GNUM C11A IM UMMY C11A IM UMMY C11B IOVCCUM UMMY C11B TESTO[] UMMY C11B TESTO[] UMMY C11B TEST GNUM C11B TEST VCC CB TEST VCC CB GNUM VCC CB FMARK VCC CB VSYNC VCC CB HSYNC VCC CA OTCLK V CA ENABLE V CA TEST_EN V CA [] V CA [] V VH [] V VH TS[8] V VH TS[7] V VH [14] GN VH [] GN VH [] GN VH TS[6] GN VH TS[5] GN VH [11] GN VH [10] GN UMMY [9] GN VREG1OUT Page of 1 Version: 008

17 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 181 UMMY AGN G[71] UMMY AGN G[73] AGNUM C21B G[75] AGNUM C21B G[77] VCI C21B G[79] VCI C21A G[81] VCI C21A G[83] VCI C21A G[85] VCI C22B G[87] VCI C22B G[89] VCI C22B G[91] VCI C22A G[93] VCI C22A G[95] VCI C22A G[97] VCI UMMY G[99] VCI UMMY G[101] VCI UMMY G[103] VCI UMMY G[105] VCI UMMY G[107] VCI AGNUM G[109] VCI UMMY G[111] AGNUM UMMY G[1] VGH UMMY G[1] VGH UMMY G[1] VGH VGLMY G[119] VGH G[1] G[1] VGH G[3] G[3] VGH G[5] G[5] AGNUM G[7] G[7] VGL G[9] G[9] VGL G[11] G[1] VGL G[] G[3] VGL G[] G[5] VGL G[] G[7] VGL G[19] G[9] VGL G[21] G[141] VGL G[23] G[143] VGL G[25] G[145] VGL G[27] G[147] AGNUM G[29] G[149] VCL G[31] G[1] VCL G[33] G[3] VCL G[35] G[5] VCL G[37] G[7] CB G[39] G[9] CB G[41] G[1] CB G[43] G[3] CB G[45] G[5] CA G[47] G[7] CA G[49] G[9] CA G[51] G[1] CA G[53] G[3] AGN G[55] G[5] AGN G[57] G[7] AGN G[59] G[9] AGN G[61] G[181] AGN G[63] G[183] AGN G[65] G[185] AGN G[67] G[187] AGN G[69] G[189] Page of 1 Version: 008

18 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 361 G[191] G[311] S[669] G[193] G[3] S[668] G[195] G[3] S[667] G[197] G[3] S[666] G[199] G[319] S[665] G[201] VGLMY S[664] G[203] UMMY S[663] G[205] UMMY S[662] G[207] UMMY S[661] G[209] S[720] S[660] G[211] S[719] S[659] G[2] S[718] S[658] G[2] S[7] S[657] G[2] S[7] S[656] G[219] S[7] S[655] G[221] S[714] S[654] G[223] S[7] S[653] G[225] S[7] S[652] G[227] S[711] S[651] G[229] S[710] S[650] G[231] S[709] S[649] G[233] S[708] S[648] G[235] S[707] S[647] G[237] S[706] S[646] G[239] S[705] S[645] G[241] S[704] S[644] G[233] S[703] S[643] G[245] S[702] S[642] G[247] S[701] S[641] G[249] S[700] S[640] G[251] S[699] S[639] G[253] S[698] S[638] G[255] S[697] S[637] G[257] S[696] S[636] G[259] S[695] S[635] G[261] S[694] S[634] G[263] S[693] S[633] G[265] S[692] S[632] G[267] S[691] S[631] G[269] S[690] S[630] G[271] S[689] S[629] G[273] S[688] S[628] G[275] S[687] S[627] G[277] S[686] S[626] G[233] S[685] S[625] G[281] S[684] S[624] G[283] S[683] S[623] G[285] S[682] S[622] G[287] S[681] S[621] G[289] S[680] S[620] G[291] S[679] S[619] G[293] S[678] S[618] G[295] S[677] S[6] G[297] S[676] S[6] G[299] S[675] S[6] G[301] S[674] S[614] G[303] S[673] S[6] G[305] S[672] S[6] G[307] S[671] S[611] G[309] S[670] S[610] Page 18 of 1 Version: 008

19 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 541 S[609] S[549] S[489] S[608] S[548] S[488] S[607] S[547] S[487] S[606] S[546] S[486] S[605] S[545] S[485] S[604] S[544] S[484] S[603] S[543] S[483] S[602] S[542] S[482] S[601] S[541] S[481] S[600] S[540] S[480] S[599] S[539] S[479] S[598] S[538] S[478] S[597] S[537] S[477] S[596] S[536] S[476] S[595] S[535] S[475] S[594] S[534] S[474] S[593] S[533] S[473] S[592] S[532] S[472] S[591] S[531] S[471] S[590] S[530] S[470] S[589] S[529] S[469] S[588] S[528] S[468] S[587] S[527] S[467] S[586] S[526] S[466] S[585] S[525] S[465] S[584] S[524] S[464] S[583] S[523] S[463] S[582] S[522] S[462] S[581] S[521] S[461] S[580] S[520] S[460] S[579] S[519] S[459] S[578] S[518] S[458] S[577] S[5] S[457] S[576] S[5] S[456] S[575] S[5] S[455] S[574] S[514] S[454] S[573] S[5] S[453] S[572] S[5] S[452] S[571] S[511] S[451] S[570] S[510] S[450] S[569] S[509] S[449] S[568] S[508] S[448] S[567] S[507] S[447] S[566] S[506] S[446] S[565] S[505] S[445] S[564] S[504] S[444] S[563] S[503] S[443] S[562] S[502] S[442] S[561] S[501] S[441] S[560] S[500] S[440] S[559] S[499] S[439] S[558] S[498] S[438] S[557] S[497] S[437] S[556] S[496] S[436] S[555] S[495] S[435] S[554] S[494] S[434] S[553] S[493] S[433] S[552] S[492] S[432] S[551] S[491] S[431] S[550] S[490] S[430] Page 19 of 1 Version: 008

20 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 721 S[429] S[369] S[311] S[428] S[368] S[310] S[427] S[367] S[309] S[426] S[366] S[308] S[425] S[365] S[307] S[424] S[364] S[306] S[423] S[363] S[305] S[422] S[362] S[304] S[421] S[361] S[303] S[420] VGMMA S[302] S[419] VGMMA S[301] S[418] S[360] S[300] S[4] S[359] S[299] S[4] S[358] S[298] S[4] S[357] S[297] S[414] S[356] S[296] S[4] S[355] S[295] S[4] S[354] S[294] S[411] S[353] S[293] S[410] S[352] S[292] S[409] S[351] S[291] S[408] S[350] S[290] S[407] S[349] S[289] S[406] S[348] S[288] S[405] S[347] S[287] S[404] S[346] S[286] S[403] S[345] S[285] S[402] S[344] S[284] S[401] S[343] S[283] S[400] S[342] S[282] S[399] S[341] S[281] S[398] S[340] S[280] S[397] S[339] S[233] S[396] S[338] S[278] S[395] S[337] S[277] S[394] S[336] S[276] S[393] S[335] S[275] S[392] S[334] S[274] S[391] S[333] S[273] S[390] S[332] S[272] S[389] S[331] S[271] S[388] S[330] S[270] S[387] S[329] S[269] S[386] S[328] S[268] S[385] S[327] S[267] S[384] S[326] S[266] S[383] S[325] S[265] S[382] S[324] S[264] S[381] S[323] S[263] S[380] S[322] S[262] S[379] S[321] S[261] S[378] S[320] S[260] S[377] S[319] S[259] S[376] S[318] S[258] S[375] S[3] S[257] S[374] S[3] S[256] S[373] S[3] S[255] S[372] S[314] S[254] S[371] S[3] S[253] S[370] S[3] S[252] Page 20 of 1 Version: 008

21 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 901 S[251] S[191] S[1] S[250] S[190] S[0] S[249] S[189] S[9] S[248] S[188] S[8] S[247] S[187] S[7] S[246] S[186] S[6] S[245] S[185] S[5] S[244] S[184] S[4] S[233] S[183] S[3] S[242] S[182] S[2] S[241] S[181] S[1] S[240] S[180] S[0] S[239] S[9] S[119] S[238] S[8] S[118] S[237] S[7] S[1] S[236] S[6] S[1] S[235] S[5] S[1] S[234] S[4] S[114] S[233] S[3] S[1] S[232] S[2] S[1] S[231] S[1] S[111] S[230] S[0] S[110] S[229] S[9] S[109] S[228] S[8] S[108] S[227] S[7] S[107] S[226] S[0] S[106] S[225] S[5] S[105] S[224] S[4] S[104] S[223] S[3] S[103] S[222] S[2] S[102] S[221] S[1] S[101] S[220] S[0] S[100] S[219] S[9] S[99] S[218] S[8] S[98] S[2] S[7] S[97] S[2] S[6] S[96] S[2] S[5] S[95] S[214] S[4] S[94] S[2] S[3] S[93] S[2] S[2] S[92] S[211] S[1] S[91] S[210] S[0] S[90] S[209] S[149] S[89] S[208] S[148] S[88] S[207] S[147] S[87] S[206] S[146] S[86] S[205] S[145] S[85] S[204] S[144] S[84] S[203] S[143] S[83] S[202] S[142] S[82] S[201] S[141] S[81] S[200] S[140] S[80] S[199] S[9] S[79] S[198] S[8] S[78] S[197] S[7] S[77] S[196] S[6] S[76] S[195] S[5] S[75] S[194] S[4] S[74] S[193] S[3] S[73] S[192] S[2] S[72] Page 21 of 1 Version: 008

22 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 1081 S[71] S[11] G[230] S[70] S[10] G[228] S[69] S[9] G[226] S[68] S[8] G[224] S[67] S[7] G[222] S[66] S[6] G[220] S[65] S[5] G[218] S[64] S[4] G[2] S[63] S[3] G[214] S[62] S[2] G[2] S[61] S[1] G[210] S[60] UMMY G[208] S[59] UMMY G[206] S[58] UMMY G[204] S[57] VGLMY G[202] S[56] G[320] G[200] S[55] G[318] G[198] S[54] G[3] G[196] S[53] G[314] G[194] S[52] G[3] G[192] S[51] G[310] G[190] S[50] G[308] G[188] S[49] G[306] G[186] S[48] G[304] G[184] S[47] G[302] G[182] S[46] G[300] G[180] S[45] G[298] G[8] S[44] G[296] G[6] S[43] G[294] G[4] S[42] G[292] G[2] S[41] G[290] G[0] S[40] G[288] G[8] S[39] G[286] G[0] S[38] G[284] G[4] S[37] G[282] G[2] S[36] G[280] G[0] S[35] G[278] G[8] S[34] G[276] G[6] S[33] G[274] G[4] S[32] G[272] G[2] S[31] G[270] G[0] S[30] G[268] G[148] S[29] G[266] G[146] S[28] G[264] G[144] S[27] G[262] G[142] S[26] G[260] G[140] S[25] G[258] G[8] S[24] G[256] G[6] S[23] G[254] G[4] S[22] G[252] G[2] S[21] G[250] G[0] S[20] G[248] G[8] S[19] G[246] G[6] S[18] G[244] G[4] S[] G[242] G[2] S[] G[240] G[0] S[] G[238] G[118] S[14] G[236] G[1] S[] G[234] G[114] S[] G[232] G[1] Page 22 of 1 Version: 008

23 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 61 G[110] G[70] G[30] G[108] G[68] G[28] G[106] G[66] G[26] G[104] G[64] G[24] G[102] G[62] G[22] G[100] G[60] G[20] G[98] G[58] G[18] G[96] G[56] G[] G[94] G[54] G[14] G[92] G[52] G[] G[90] G[50] G[10] G[88] G[48] G[8] G[86] G[46] G[6] G[84] G[44] G[4] G[82] G[42] G[2] G[80] G[40] VGLMY G[78] G[38] UMMYR G[76] G[36] UMMYR G[74] G[34] UMMY G[72] G[32] UMMY S1 ~ S720 G1 ~ G320 UMMY18~31 VGMMA1, 62 VGLMY1~ Unit: um Page 23 of 1 Version: 008

24 I/O Pads Pad Pump Pad Pump 80 Min 70 Unit: um Alignment mark Alignment mark X Y Page 24 of 1 Version: 008

25 6 Block escription MPU System Interface supports three system high-speed interfaces: i80-system high-speed interfaces to 8-, 9-, -, 18-bit parallel ports and serial peripheral interface (SPI) The interface mode is selected by setting the IM[3:0] pins has a -bit index register (IR), an 18-bit write-data register (R), and an 18-bit read-data register (R) The IR is the register to store index information from control registers and the internal GRAM The R is the register to temporarily store data to be written to control registers and the internal GRAM The R is the register to temporarily store data read from the GRAM ata from the MPU to be written to the internal GRAM are first written to the R and then automatically written to the internal GRAM in internal operation ata are read via the R from the internal GRAM Therefore, invalid data are read out to the data bus when the read the first data from the internal GRAM Valid data are read out after the performs the second read operation Registers are written consecutively as the register execution time Registers selection by system interface (8-/9-/-/18-bit bus width) I80 Function RS nwr n Write an index to IR register Write to control registers or the internal GRAM by R register Read from the internal GRAM by R register Registers selection by the SPI system interface Function R/W RS Write an index to IR register 0 0 Write to control registers or the internal GRAM by R register 0 1 Read from the internal GRAM by R register 1 1 Parallel RGB Interface supports the RGB interface and the VSYNC interface as the external interface for displaying a moving picture When the RGB interface is selected, display operations are synchronized with externally supplied signals, VSYNC, HSYNC, and OTCLK In RGB interface mode, data (-0) are written in synchronization with these signals according to the polarity of enable signal (ENABLE) to prevent flicker on display while updating display data In VSYNC interface mode, the display operation is synchronized with the internal clock except frame synchronization, where the operation is synchronized with the VSYNC signal isplay data are written to the internal GRAM via the system interface In this case, there are constraints in speed and method in writing data to the internal RAM For details, see the External isplay Interface section The allows for switching between the external display interface and the system interface by instruction so that the optimum interface is selected for the kind of picture to be displayed on the screen (still and/or moving picture(s)) The RGB interface, by writing all display data to the internal RAM, allows for transferring data only when updating the frames of a moving picture, contributing to low power requirement for moving picture display Page 25 of 1 Version: 008

26 Bit Operation The supports a write data mask function for selectively writing data to the internal RAM in units of bits and a logical/compare operation to write data to the GRAM only when a condition is met as a result of comparing the data and the compare register bits For details, see Graphics Operation Functions Address Counter (AC) The address counter (AC) gives an address to the internal GRAM When the index of the register for setting a RAM address in the AC is written to the IR, the address information is sent from the IR to the AC As writing data to the internal GRAM, the address in the AC is automatically updated plus or minus 1 The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM Graphics RAM (GRAM) GRAM is graphics RAM storing bit-pattern data of 2,800 (240 x 320x 18/8) bytes with 18 bits per pixel Grayscale Voltage Generating Circuit The grayscale voltage generating circuit generates a liquid crystal drive voltage according to grayscale data set in the γ-correction register to display in 262,144 colors For details, see the γ-correction Register section Timing Controller The timing generator generates a timing signal for operation of internal circuits such as the internal GRAM The timing for the display operation such as RAM read operation and the timing for the internal operation such as access from the MPU are generated in the way not to interfere each other Oscillator (OSC) generates RC oscillation with an internal oscillation resistor The frame rate is adjusted by the register setting LC river Circuit The LC driver circuit of consists of a 720-output source driver (S1 ~ S720) and a 320-output gate driver (G1~G320) isplay pattern data are latched when the 720 th bit data are input The latched data control the source driver and generate a drive waveform The gate driver for scanning gate lines outputs either VGH or VGL level The shift direction of 720 source outputs from the source driver is set with the SS bit and the shift direction of gate outputs from the gate driver is set with the GS bit The scan mode by the gate driver is set with the SM bit These bits allow setting an appropriate scan method for an LC module LC river Power Supply Circuit The LC drive power supply circuit generates the voltage levels VREG1OUT, VGH, VGL and Vcom for driving an LC Page 26 of 1 Version: 008

27 7 System Interface 71 Interface Specifications has the system interface to read/write the control registers and display graphics memory (GRAM), and the RGB Input Interface for displaying a moving picture User can select an optimum interface to display the moving or still picture with efficient data transfer All display data are stored in the GRAM to reduce the data transfer efforts and only the updating data is necessary to be transferred User can only update a sub-range of GRAM by using the window address function also has the RGB interface and VSYNC interface to transfer the display data without flicker the moving picture on the screen In RGB interface mode, the display data is written into the GRAM through the control signals of ENABLE, VSYNC, HSYNC, OTCLK and data bus [:0] In VSYNC interface mode, the internal display timing is synchronized with the frame synchronization signal (VSYNC) The VSYNC interface mode enables to display the moving picture display through the system interface In this case, there are some constraints of speed and method to write data to the internal RAM operates in one of the following 4 modes The display mode can be switched by the control register When switching from one mode to another, refer to the sequences mentioned in the sections of RGB and VSYNC interfaces Operation Mode RAM Access Setting (RM) isplay Operation Mode (M[1:0]) Internal operating clock only (isplaying still pictures) RGB interface (1) (isplaying moving pictures) RGB interface (2) (Rewriting still pictures while displaying moving pictures) VSYNC interface (isplaying moving pictures) System interface (RM = 0) RGB interface (RM = 1) System interface (RM = 0) System interface (RM = 0) Internal operating clock (M[1:0] = 00) RGB interface (M[1:0] = 01) RGB interface (M[1:0] = 01) VSYNC interface (M[1:0] = 01) Note 1) Registers are set only via the system interface Note 2) The RGB-I/F and the VSYNC-I/F are not available simultaneously Page 27 of 1 Version: 008

28 System System Interface 18//6 ncs RS nwr n [:0] RGB Interface ENABLE VSYNC HSYNC OTCLK Figure1 System Interface and RGB Interface connection 72 Input Interfaces The following are the system interfaces available with the The interface is selected by setting the IM[3:0] pins The system interface is used for setting registers and GRAM access IM3 IM2 IM1 IM0/I Interface Mode Pin Setting invalid Setting invalid i80-system -bit interface [:10], [8:1] i80-system 8-bit interface [:10] I Serial Peripheral Interface (SPI) SI, SO ([1:0]) * Setting invalid Setting invalid Setting invalid i80-system18-bit interface [:0] i80-system 9-bit interface [:9] 1 1 * * Setting invalid Page 28 of 1 Version: 008

29 721 i80/18-bit System Interface The i80/18-bit system interface is selected by setting the IM[3:0] as 1010 levels System ncs A2 nwr n [31:0] 18 ncs RS nwr n [:0] 18-bit System Interface (262K colors) TRI=0, FM[1:0]=00 Input ata Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Figure2 18-bit System Interface ata Format Page 29 of 1 Version: 008