ILI9221. a-si TFT LCD Single Chip Driver 176RGBx220 Resolution and 262K color. Datasheet Preliminary

Transcription

1 a-si TFT LC Single Chip river atasheet Preliminary Version: V ocument No: S_Vdoc ILI TECHNOLOGY CORP 4F, No, Tech 5 th Rd, Hsinchu Science Park, Taiwan 3, ROC Tel ; Fax

2 Table of Contents Section Page Introduction 7 Features 7 3 Block iagram 9 4 Pin escriptions 5 Pad Arrangement and Coordination 4 6 Block escription 7 System Interface 3 7 Interface Specifications 3 7 Input Interfaces 4 7 i8/8-bit System Interface 5 7 i8/-bit System Interface 6 73 i8/9-bit System Interface 7 74 i8/8-bit System Interface 7 73 Serial Peripheral Interface (SPI) 9 74 VSYNC Interface RGB Input Interface RGB Interface RGB Interface Timing Moving Picture Mode bit RGB Interface bit RGB Interface bit RGB Interface44 76 Interface Timing 47 8 Register escriptions 48 8 Registers Access 48 8 Instruction escriptions 5 8 Index (IR) 54 8 Status Read (RS) Start Oscillation (Rh)54 84 river Output Control (Rh) LC riving Waveform Control (Rh) Entry Mode (R3h) 6 87 Compare Registers (R4h, R5h) isplay Control (R7h) isplay Control (R8h) 66 8 isplay Control 3 (R9h) 66 8 Frame Cycle Control (RBh) 67 8 RGB Input Interface Control (RCh) 69 Page of 9 Version:

3 8 Power Control (Rh) 7 84 Power Control (Rh) 7 8 Power Control 3 (Rh) 7 8 Power Control 4 (Rh) 74 8 RAM Address Set (Rh) Write ata to GRAM (Rh) Read ata from GRAM (Rh) 75 8 RAM Write Mask (R3h, R4h) 77 8 Gamma Control (R3h ~ R39h) 79 8 Gate Scan Control (R4h) Vertical Scroll Control (R4h) 8 84 st Screen rive Position (R4h) and nd Screen rive Position (R43h) 8 85 Horizontal and Vertical RAM Address Position (R44h, R45h) 8 9 Reset Function 83 GRAM Address Map & Read/Write 84 Window Address Function 88 Graphics Operation Function 89 Write ata Mask Function 9 Graphics Operation Processing 9 Gamma Correction 4 Application 4 Configuration of Power Supply Circuit 4 isplay ON/OFF Sequence 43 Standby and Sleep Mode 44 Power Supply Configuration 4 45 Voltage Generation 46 Applied Voltage to the TFT panel 47 Oscillator 48 Frame Rate Adjustment 49 Partial isplay Function 4 8-color isplay Electrical Characteristics Absolute Maximum Ratings C Characteristics 3 3 Clock Characteristics 3 4 Reset Timing Characteristics 3 5 LC river Output Characteristics 4 6 AC Characteristics 4 6 i8-system Interface Timing Characteristics 4 6 M68-System Interface Timing Characteristics 6 Page 3 of 9 Version:

4 63 Serial ata Transfer Interface Timing Characteristics 7 64 RGB Interface Timing Characteristics 8 Revision History 9 Page 4 of 9 Version:

5 Figures FIGURE SYSTEM INTERFACE AN RGB INTERFACE CONNECTION 4 FIGURE 8-BIT SYSTEM INTERFACE ATA FORMAT 5 FIGURE3 -BIT SYSTEM INTERFACE ATA FORMAT 6 FIGURE4 9-BIT SYSTEM INTERFACE ATA FORMAT 7 FIGURE5 8-BIT SYSTEM INTERFACE ATA FORMAT 8 FIGURE6 ATA TRANSFER SYNCHRONIZATION IN 8/9-BIT SYSTEM INTERFACE 9 FIGURE 7 ATA FORMAT OF SPI INTERFACE 3 FIGURE8 ATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI) 3 FIGURE9 ATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI), TRI= AN FM= ) 33 FIGURE ATA TRANSMISSION THROUGH VSYNC INTERFACE) 34 FIGURE MOVING PICTURE ATA TRANSMISSION THROUGH VSYNC INTERFACE 34 FIGURE OPERATION THROUGH VSYNC INTERFACE 35 FIGURE TRANSITION FLOW BETWEEN VSYNC AN INTERNAL CLOCK OPERATION MOES 37 FIGURE4 RGB INTERFACE ATA FORMAT 38 FIGURE GRAM ACCESS AREA BY RGB INTERFACE 39 FIGURE TIMING CHART OF SIGNALS IN 8-/-BIT RGB INTERFACE MOE 4 FIGURE TIMING CHART OF SIGNALS IN 6-BIT RGB INTERFACE MOE 4 FIGURE8 EXAMPLE OF UPATE THE STILL AN MOVING PICTURE 4 FIGURE9 INTERNAL CLOCK OPERATION/RGB INTERFACE MOE SWITCHING 45 FIGURE GRAM ACCESS BETWEEN SYSTEM INTERFACE AN RGB INTERFACE 46 FIGURE RELATIONSHIP BETWEEN RGB I/F SIGNALS AN LC RIVING SIGNALS FOR PANEL 47 FIGURE REGISTER SETTING WITH SERIAL PERIPHERAL INTERFACE (SPI) 48 FIGURE3 REGISTER SETTING WITH I8/M68 SYSTEM INTERFACE 49 FIGURE 4 REGISTER REA/WRITE TIMING OF I8 SYSTEM INTERFACE 5 FIGURE 5 REGISTER REA/WRITE TIMING OF M68 SYSTEM INTERFACE 5 FIGURE 6 N-LINE INVERSION AC RIVE 58 FIGURE7 INTERLACE SCAN OF AC RIVE 59 FIGURE8 OUTPUT TIMING OF INTERLACE GATE SIGNALS (THREE-FIEL IS SELECTE) 59 FIGURE9 AC RIVING ALTERNATING TIMING 6 FIGURE3 GRAM ACCESS IRECTION SETTING 6 FIGURE3 ATA OPERATION WITH MASK AN COMPARE FUNCTION 6 FIGURE3 -BIT MPU SYSTEM INTERFACE ATA FORMAT 6 FIGURE33 8-BIT MPU SYSTEM INTERFACE ATA FORMAT 63 FIGURE34 SPI SYSTEM INTERFACE ATA FORMAT 63 FIGURE35 ATA OPERATION WITH MASK AN COMPARE FUNCTION 64 FIGURE 36 ATA REA FROM GRAM THROUGH REA ATA REGISTER IN 8-/-/9-/8-BIT INTERFACE MOE 76 FIGURE 37 GRAM ATA REA BACK FLOW CHART 77 FIGURE 38 GRAM WRITE WITH 8-BIT ATA MASK 78 FIGURE 39 GRAM ATA MAP WITH MASK AN BGR CONVERSION 78 Page 5 of 9 Version:

6 FIGURE 4 SCANNING START POSITION FOR GATE RIVER 79 FIGURE 4 GRAM ACCESS RANGE CONFIGURATION 8 FIGURE4 GRAM REA/WRITE TIMING OF I8-SYSTEM INTERFACE 84 FIGURE 43 GRAM REA/WRITE TIMING OF M68-SYSTEM INTERFACE 85 FIGURE44 I8-SYSTEM INTERFACE WITH 8-/9-BIT ATA BUS (SS=, BGR= ) 86 FIGURE 45 I8-SYSTEM INTERFACE WITH 8-/9-BIT ATA BUS (SS=, BGR= ) 87 FIGURE 46 GRAM ACCESS WINOW MAP 88 FIGURE 47 -/8-BIT ATA MASK FUNCTION 9 FIGURE 48 WRITE OPERATION OF WRITE MOE 9 FIGURE 49 WRITE OPERATION OF WRITE MOE 93 FIGURE 5 WRITE OPERATION OF WRITE MOE 3 94 FIGURE 5 WRITE OPERATION OF WRITE MOE 4 95 FIGURE 5 WRITE OPERATION OF REA/WRITE MOE 96 FIGURE 53 WRITE OPERATION OF REA/WRITE MOE 97 FIGURE 54 WRITE OPERATION OF REA/WRITE MOE 3 98 FIGURE 55 WRITE OPERATION OF REA/WRITE MOE 4 99 FIGURE 56 GRAYSCALE MAPPING FIGURE 57 GRAYSCALE VOLTAGE GENERATION FIGURE 58 GRAYSCALE VOLTAGE AJUSTMENT FIGURE 59 GAMMA CURVE AJUSTMENT 3 FIGURE 6 RELATIONSHIP BETWEEN SOURCE OUTPUT AN VCOM 9 FIGURE 6 RELATIONSHIP BETWEEN GRAM ATA AN OUTPUT LEVEL 9 FIGURE 6 POWER SUPPLY CIRCUIT BLOCK FIGURE 63 ISPLAY ON/OFF REGISTER SETTING SEQUENCE FIGURE 64 STANY/SLEEP MOE REGISTER SETTING SEQUENCE FIGURE 65 POWER SUPPLY ON/OFF SEQUENCE 4 FIGURE 66 VOLTAGE CONFIGURATION IAGRAM FIGURE 67 VOLTAGE OUTPUT TO TFT LC PANEL FIGURE 68 OSCILLATION CONNECTION FIGURE 69 PARTIAL ISPLAY EXAMPLE 8 FIGURE 7 PARTIAL ISPLAY SETTING FLOW FIGURE7 8-COLOR ISPLAY MOE FIGURE 7 I8-SYSTEM BUS TIMING 5 FIGURE 73 M68-SYSTEM BUS TIMING 5 FIGURE74 M68-SYSTEM INTERFACE TIMING 6 FIGURE 75 SPI SYSTEM BUS TIMING 7 FIGURE76 RGB INTERFACE TIMING8 Page 6 of 9 Version:

7 Introduction a-si TFT LC Single Chip river is a 6,44-color one-chip SoC driver for a-tft liquid crystal display with resolution of 6RGBx dots, comprising a 58-channel source driver, a -channel gate driver, 87 bytes RAM for graphic data of 6RGBx dots, and power supply circuit has five kinds of system interfaces which are i8/m68-system MPU interface (8-/9-/-/8-bit bus width), VSYNC interface (system interface + VSYNC, internal clock, [:]), serial data transfer interface (SPI) and RGB 6-/-/8-bit interface (OTCLK, VSYNC, HSYNC, ENABLE, [:]) In RGB interface and VSYNC interface mode, the combined use of high-speed RAM write function and widow address function enables to display a moving picture at a position specified by a user and still pictures in other areas on the screen simultaneously, which makes it possible to transfer display the refresh data only to minimize data transfers and power consumption can operate with low I/O interface power supply up to 5V, with an incorporated voltage follower circuit to generate voltage levels for driving an LC The also supports a function to display in 8 colors and a standby mode, allowing for precise power control by software These features make the an ideal LC driver for medium or small size portable products such as digital cellular phones or small PA, where long battery life is a major concern Features Single chip solution for a liquid crystal QCIF+ TFT LC display 6RGBx-dot resolution capable of graphics display in 6,44 color Incorporate 58-channel source driver and -channel gate driver Internal 87, bytes graphic RAM High-speed RAM burst write function System interfaces i8 system interface with 8-/ 9-/-/8-bit bus width M68 system interface with 8-/ 9-/-/8-bit bus width Serial Peripheral Interface (SPI) RGB interface with 8-/-/8-bit bus width (VSYNC, HSYNC, OTCLK, ENABLE, [:]) VSYNC interface (System interface + VSYNC) n-line liquid crystal AC drive: invert polarity at an interval of arbitrarily n lines (n: ~ 64) Internal oscillator and hardware reset Reversible source/gate driver shift direction Window address function to specify a rectangular area for internal GRAM access Bit operation function for facilitating graphics data processing Bit-unit write data mask function Pixel-unit logical/conditional write function Abundant functions for color display control γ-correction function enabling display in 6,44 colors Line-unit vertical scrolling function Page 7 of 9 Version:

8 Partial drive function, enabling partially driving an LC panel at positions specified by user Incorporate step-up circuits for stepping up a liquid crystal drive voltage level up to 6 times (x6) Power saving functions 8-color mode standby mode sleep mode Low -power consumption architecture Low operating power supplies: IOVcc = 5 ~ 33 V (interface I/O) Vcc = 4 ~ 33 V (internal logic) Vci = 5 ~ 33 V (analog) Low voltage drive: VH = 45 ~ 55 V Page 8 of 9 Version:

9 3 Block iagram IOVCC IM[3:] nreset ncs nwr n RS [:] SI SO SCL HSYNC VSYNC MPU I/F 8-bit -bit 9-bit 8-bit SPI I/F RGB I/F 8-bit -bit 6-bit 8 8 Index Register (IR) 7 Control Register (CR) Graphics Operation 8 Address Counter (AC) V63 ~ LC Source river S[58:] OTCLK TEST TEST TS[7:] VSYNC I/F 8 Read Latch 7 Write Latch 7 Grayscale Reference Voltage VGAMOUT VGS VCC VCORE GN Regulator Graphics RAM (GRAM) OSC AGN RC-OSC Timing Controller LC Gate river G[:] VCI VCI VCILVL AGN Charge-pump Power Circuit VCOM Generator VCOM CA CB VH CA CB VCL CA CB CA CB VGH VGL VCOMR VCOMH VCOML Page 9 of 9 Version:

10 4 Pin escriptions a-si TFT LC Single Chip river Pin Name I/O Type escriptions Input Interface Select the MPU system interface mode IM3, IM, IM, IM/I ncs RS nwr/e/scl n/rw nreset [:] I I I I I I I/O IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc IM3 IM IM IM MPU-Interface Mode Pin in use M68-system -bit interface [:], [8:] M68-system 8-bit interface [:] i8-system -bit interface [:], [8:] i8-system 8-bit interface [:] I Serial Peripheral Interface (SPI) SI, SO Setting invalid M68-system 8-bit interface [:] M68-system 9-bit interface [:9] i8-system 8-bit interface [:] i8-system 9-bit interface [:9] Setting invalid When the serial peripheral interface is selected, IM pin is used for the device code I setting A chip select signal Low: the is selected and accessible High: the is not selected and not accessible Fix to the GN level when not in use A register select signal Low: select an index or status register High: select a control register Fix to either IOVcc or GN level when not in use A write strobe signal and enables an operation to write data when the signal is low Fix to either IOVcc or GN level when not in use SPI Mode: A synchronizing clock signal in SPI mode A read strobe signal and enables an operation to read out data when the signal is low Fix to either IOVcc or GN level when not in use A reset pin Initializes the with a low input Be sure to execute a power-on reset after supplying power An 8-bit parallel bi-directional data bus for MPU system interface mode 8-bit I/F: [:] is used 9-bit I/F: [:9] is used -bit I/F: [:] and [8:] is used 8-bit I/F: [:] is used Unused pins must be fixed either IOVcc or GN level Serial data input (SI) pin in serial interface operation The data is SI I MPU IOVcc latched on the rising edge of the SCL signal When the SPI interface is not used, the SI shall be connected to either IOVcc or GN level Page of 9 Version:

11 SO Pin Name I/O Type escriptions O MPU IOVcc Serial data output (SO) pin in serial interface operation The data is outputted on the falling edge of the SCL signal When the SPI interface is not used, please let SO as floating OTCLK I A dot clock signal Fix to the IOVcc level when not in use MPU PL = : Input data on the rising edge of OTCLK IOVcc PL = : Input data on the falling edge of OTCLK VSYNC I A frame synchronizing signal Fix to the IOVcc level when not in use MPU VSPL = : Active low IOVcc VSPL = : Active high HSYNC I A line synchronizing signal Fix to the IOVcc level when not in use MPU HSPL = : Active low IOVcc HSPL = : Active high ENABLE I A data ENEABLE signal in RGB interface mode Low: Select (access enabled) MPU High: Not select (access inhibited) IOVcc The EPL bit inverts the polarity of the ENABLE signal Fix to either IOVcc or GN level when not in use FLM O Output a frame head pulse signal MPU The FLM signal is used when writing RAM data in synchronization with IOVcc frame Leave the pin open when not in use LC riving signals Source output voltage signals applied to liquid crystal To change the shift direction of signal outputs, use the SS bit S58~S O LC SS =, the data in the RAM address h is output from S SS =, the data in the RAM address h is output from S58 S, S4, S7, display red (R), S, S5, S8, display green (G), and S3, S6, S9, display blue (B) (SS = ) G~G O LC Gate line output signals VGH: the level selecting gate lines VGL: the level not selecting gate lines VCOM O TFT common electrode A supply voltage to the common electrode of TFT panel VCOM is AC voltage alternating signal between the VCOMH and VCOML levels Charge-pump and Regulator Circuit VCOMH O Stabilizing The high level of VCOM AC voltage Connect to a stabilizing capacitor capacitor VCOML O The low level of VCOM AC voltage Adjust the VCOML level with the not necessary Stabilizing VV bits Connect to a stabilizing capacitor To fix the VCOML level capacitor to AGN and set VCOMG = In this case, capacitor connection is VCOMR CA, CB - CA, CB CA, CB CA, CB OSC I - I Variable resistor or open Step-up capacitor Step-up capacitor Oscillation resistor A reference level to generate the VCOMH level either with an externally connected variable resistor or by setting the register of the When using a variable resistor, halt the internal VCOMH adjusting circuit by setting the register and place the resister between VGAMOUT and AGN When generating the VCOMH level by setting the register, leave this pin open Pins to connect capacitors for the internal step-up circuit Leave the pins open when not using the step-up circuit Pins to connect capacitors for the internal step-up circuit Connect a capacitor according to step-up rate Leave the pins open when not using the step-up circuit Connect an external resistor for generating internal clock by internal R-C oscillation, or an external clock signal is supplied through OSC Page of 9 Version:

12 VciLVL VCI Pin Name I/O Type escriptions VH VGH VGL VCL VGAMOUT VGS VCC IOVCC VCI I O O O O O I/O I I I I Power supply Stabilizing capacitor Vci Stabilizing capacitor, VH Stabilizing capacitor, VGH Stabilizing capacitor, VGL Stabilizing capacitor, VCL Stabilizing capacitor or power supply AGN or external resistor Power supply Power supply Power supply VCORE O Power GN AGN I Power supply Power supply IOVCCUM~ O P IOVSSUM~ O P I A reference level to generate the VCI/REGP level according to the step-up rate set with the VC[:] bits Be sure to connect VciLVL with Vci on the FPC to prevent noise An internal reference voltage for the step-up circuit The amplitude between Vci and GN is determined by the VC[:] bits When not using an internal reference voltage, please connect this pin to a external voltage (less than 75V) An output voltage from the step-up circuit, twice the Vci level Place a stabilizing capacitor between AGN Place a shottkey diode between Vci and VH See Configurations of Power supply circuit VH = 45 ~ 55V An output voltage from the step-up circuit, 4 ~ 6 times the Vci level The step-up rate is set with the BT bits Place a stabilizing capacitor between AGN Place a shottkey diode between Vci See Configurations of Power supply circuit VGH = max 5V An output voltage from the step-up circuit, -3 ~ -5 times the Vci level The step-up rate is set with the BT bits Place a stabilizing capacitor between AGN Place a shottkey diode between Vci See Configurations of Power supply circuit VGL = min 5V An output voltage from the step-up circuit, time the Vci level Connect to a stabilizing capacitor VCLC = ~ 33V A voltage level of VH-AGN, generated from the reference level of Vci-AGN according to the rate set with the VRH[3:] bits VGAMOUT is () a source driver grayscale reference voltage VH, () a VCOMH level reference voltage, and (3) a VCOM amplitude reference voltage Connect to a stabilizing capacitor VGAMOUT = 3 ~ (VH 5)V A reference level for the grayscale voltage generating circuit The VGS level can be changed by connecting to an external resistor Power Pads A supply voltage to the internal logic: Vcc = 4~33V A supply voltage to the interface pins (IOVcc = 5 ~ 33V) IOVcc and the internal logic voltage Vcc must be supplied in the same condition In case of COG, connect to Vcc on the FPC if IOVcc=Vcc, to prevent noise A supply voltage to the analog circuit Connect to an external power supply of 5 ~ 33V igital core power pad Connect them with the uf capacitor GN for the logic side: GN = V AGN for the analog side: AGN = V In case of COG, connect to GN on the FPC to prevent noise Output the IOVcc voltage level When adjacent pins are needed to pull high, tie these pins to IOVCCUM and IOVCCUM Output the GN voltage level When adjacent pins are needed to pull low, tie these pins to IOVSSUMand IOVSSUM Test Pads TEST I Open A test pin This pin is internal pull down to GN TEST I Open A test pin This pin is internal pull down to GN TS[7:] O Open Test pins, disconnect them Page of 9 Version:

13 Pin Name I/O Type escriptions UMMY~ 4 O Open ummy pads Leave them open UMMYR~ O Open ummy pads Leave them open NCPA - Open No connected pad Leave them open POSC[:] - Open Test pins Leave them open TESTO[5:3] - Open Test pins Leave them open VGLMY[4:] - Open Test pins Leave them open TESTO[5:3] - Open Test pins Leave them open Liquid crystal power supply specifications Table No Item escription TFT data lines 58 pins (6 x RGB) TFT gate lines pins 3 TFT display s capacitor structure Cst structure only (Common VCOM) 4 Liquid crystal drive output 5 Input voltage 6 Internal step-up circuits S ~ S58 V ~ V63 grayscales G ~ G VGH - VGL VCOM VCOMH - VCOML: Amplitude = electronic volumes VCOMH=VCOMR: Adjusted with an external resistor IOVcc 5 ~ 33V Vcc 4 ~ 33V Vci 5 ~ 33V VH Vci x VGH Vci x 4, x 5, x 6 VGL Vci x -3, x -4, x -5 VCL Vci x - Page of 9 Version:

14 a-si TFT LC Single Chip river 5 Pad Arrangement and Coordination Chip Size: um x 5um Chip thickness : 4 um (typ) Pad Location: Pad Center Coordinate Origin: Not chip center (, 655um) Au bump height: um (typ) Au Bump Size: 9um x um (No 4 ~ 3) Gate: G ~ G Source: S ~ S58 5um x 8um (No ~ 36) Input Pads Pad to um x 5um No: 37~ 4 and 6~ Alignment Marks Alignment Mark: -a, -b um Alignment Mark: -a Alignment Mark: -b Alignment Mark: 3-a, 3-b 53um 5 5 7um UMMY UMMY UMMY3 UMMY4 UMMY5 UMMY5 UMMY6 UMMY7 UMMY8 UMMYR UMMYR NCPA IOVSSUM NCPA TEST TEST UMMY9 IM IM IM IM3 NCPA IOVCCUM NCPA nreset VSYNC HSYNC OTCLK ENABLE NCPA IOVSSUM OPEN SO SI n/rw nwr/e/scl RS ncs FLM TS IOVCCUM TS TS POSC[] POSC[] OSC POSC[] GN AGN UMMY UMMY UMMYR3 UMMYR4 GN GN GN GN GN GN GN IOVCC IOVCC IOVCC IOVCC VCC VCC VCC VCC VCC VCC VCORE VCORE VCORE VCORE VCORE VCORE VCORE VCORE VCORE VCORE VCORE VCORE VCORE VCORE VCORE VCORE UMMY TS3 UMMY TS4 UMMY TS5 UMMY3 AGN AGN AGN AGN AGN AGN AGN AGN AGN AGN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN TS6 UMMY4 TS7 VGS UMMY5 UMMY6 VCOM VCOM VCOM VCOM VCOM VCOMH VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VCOML UMMY7 UMMY8 VGAMOUT UMMY8A UMMY9 UMMY3 VCOMR UMMY3 VCL VCL VCL VH VH VH VH VH VH VH VH VCI VCI VCI VCI VCI VCI VCI VCILVL VCI VCI VCI VCI VCI VCI VCI VCI CB CB CB CB CB CA CA CA CA CA AGNUM VGL VGL VGL VGL VGL VGL VGL VGL UMMY3 CB CB UMMY33 CA CA UMMY34 CB CB CA CA CB CB CA CA VGH VGH VGH VGH VGH UMMY35 UMMYR5 UMMYR6 (-a) (-b) (3-a) (3-b) X Face Up (Bump View) (, 655um) Chip Center um Y um (-a) 3 (-b) TESTO3 TESTO3 UMMYR UMMYR9 VGLMY4 G G3 G5 G7 G9 G G G G G9 VGLMY3 TESTO3 TESTO9 S S S3 S4 S5 S6 S7 S8 S9 S5 S5 S5 S53 S54 S55 S56 S57 S58 TESTO8 TESTO7 VGLMY G G8 G G4 G G G8 G6 G4 G VGLMY UMMYR8 UMMYR7 TESTO6 TESTO5 Page 4 of 9 Version:

15 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y UMMY TS AGN VCI TESTO UMMY POSC[] GN VCI UMMYR UMMY POSC[] GN VCI UMMYR UMMY OSC GN VCI VGLMY UMMY POSC[] GN VCI G UMMY GN GN VCILVL G UMMY AGN GN VCI G UMMY UMMY GN VCI G UMMY UMMY GN VCI G 8 4 UMMYR UMMYR GN VCI G UMMYR UMMYR GN VCI G OPEN GN GN VCI G IOVSSUM GN GN VCI G OPEN GN GN VCI G TEST GN GN CB G TEST GN GN CB G UMMY GN GN CB G IM GN GN CB G IM IOVCC TS CB G IM IOVCC UMMY CA G IM IOVCC TS CA G OPEN IOVCC VGS CA G IOVCCUM VCC UMMY CA G OPEN VCC UMMY CA G nreset VCC VCOM AGNUM G VSYNC VCC VCOM VGL G HSYNC VCC VCOM VGL G OTCLK VCC VCOM VGL G ENABLE VCORE VCOM VGL G VCORE VCOMH VGL G VCORE VCOMH VGL G VCORE VCOMH VGL G VCORE VCOMH VGL G VCORE VCOMH UMMY G VCORE VCOML CB G VCORE VCOML CB G VCORE VCOML UMMY G VCORE VCOML CA G VCORE VCOML CA G OPEN VCORE UMMY UMMY G IOVSSUM VCORE UMMY CB G OPEN VCORE VGAMOUT CB G VCORE UMMY8A CA G VCORE UMMY CA G UMMY UMMY CB G TS VCOMR CB G UMMY UMMY CA G TS VCL CA G UMMY VCL VGH G TS VCL VGH G SO UMMY VH VGH G SI AGN VH VGH G n/rw AGN VH VGH G nwr/e/scl AGN VH UMMY G RS AGN VH UMMYR G NCS AGN VH UMMYR G FLM AGN VH G TS AGN VH G IOVCCUM AGN VCI G TS AGN VCI TESTO G Page of 9 Version:

16 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 3 G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S VGLMY S S S S TESTO S S S S TESTO S S S S S S S S S S S S S S S S S S S Page of 9 Version:

17 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 6 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S TESTO S S S S TESTO S S S S VGLMY S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G Page of 9 Version:

18 No Name X Y No Name X Y 9 G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G VGLMY G UMMYR G UMMYR G TESTO G TESTO G G G G G G G G a G b G a G b G a G b G G G G Page 8 of 9 Version:

19 9 S ~ S58 G ~ G VGLMY~4 TESTO5~3 UMMYR7~R 35 Unit: um Pad: ~ I/O Pads Pad Pump Pad Pump 8 7 Page 9 of 9 Version:

20 6 Block escription MPU System Interface supports three system high-speed interfaces: i8/m68-system high-speed interfaces to 8-, 9-, -, 8-bit parallel ports and serial peripheral interface (SPI) The interface mode is selected by setting the IM[3:] pins has a -bit index register (IR), an 8-bit write-data register (R), and an 8-bit read-data register (R) The IR is the register to store index information from control registers and the internal GRAM The R is the register to temporarily store data to be written to control registers and the internal GRAM The R is the register to temporarily store data read from the GRAM ata from the MPU to be written to the internal GRAM are first written to the R and then automatically written to the internal GRAM in internal operation ata are read via the R from the internal GRAM Therefore, invalid data are read out to the data bus when the read the first data from the internal GRAM Valid data are read out after the performs the second read operation Registers are written consecutively as the register execution time except starting oscillator takes clock cycle Registers selection by system interface (8-/9-/-/8-bit bus width) I8 M68 Function RS nwr n E RW Write an index to IR register Read an internal status Write to control registers or the internal GRAM by R register Read from the internal GRAM by R register Registers selection by the SPI system interface Function R/W RS Write an index to IR register Read an internal status Write to control registers or the internal GRAM by R register Read from the internal GRAM by R register Parallel RGB Interface supports the RGB interface and the VSYNC interface as the external interface for displaying a moving picture When the RGB interface is selected, display operations are synchronized with externally supplied signals, VSYNC, HSYNC, and OTCLK In RGB interface mode, data (-) are written in synchronization with these signals according to the polarity of enable signal (ENABLE) to prevent flicker on display while updating display data In VSYNC interface mode, the display operation is synchronized with the internal clock except frame synchronization, where the operation is synchronized with the VSYNC signal isplay data are written to the internal GRAM via the system interface In this case, there are constraints in speed and method in writing data to the internal RAM For details, see the External isplay Interface section The allows for switching Page of 9 Version:

21 between the external display interface and the system interface by instruction so that the optimum interface is selected for the kind of picture to be displayed on the screen (still and/or moving picture(s)) The RGB interface, by writing all display data to the internal RAM, allows for transferring data only when updating the frames of a moving picture, contributing to low power requirement for moving picture display Bit Operation The supports a write data mask function for selectively writing data to the internal RAM in units of bits and a logical/compare operation to write data to the GRAM only when a condition is met as a result of comparing the data and the compare register bits For details, see Graphics Operation Functions Address Counter (AC) The address counter (AC) gives an address to the internal GRAM When the index of the register for setting a RAM address in the AC is written to the IR, the address information is sent from the IR to the AC As writing data to the internal GRAM, the address in the AC is automatically updated plus or minus The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM Graphics RAM (GRAM) GRAM is graphics RAM storing bit-pattern data of 87, (6 x x 8/8) bytes, using 8 bits for each pixel Grayscale Voltage Generating Circuit The grayscale voltage generating circuit generates a liquid crystal drive voltage according to grayscale data set in the γ-correction register to display in 6,44 colors For details, see the γ-correction Register section Timing Controller The timing generator generates a timing signal for operation of internal circuits such as the internal GRAM The timing for the display operation such as RAM read operation and the timing for the internal operation such as access from the MPU are generated in the way not to interfere each other Oscillator (OSC) generates RC oscillation with an external oscillation resistor placed between the OSC and OSC pins The oscillation frequency is changed according to the value of an external resistor Adjust the oscillation frequency in accordance to the operating voltage or the frame frequency An operating clock can be input externally uring standby mode, RC oscillation is halted to reduce power consumption For details, see Oscillator LC river Circuit The LC driver circuit of consists of a 58-output source driver (S ~ S58) and a -output gate driver (G~G) isplay pattern data are latched when the 58th bit data are input The latched data control Page of 9 Version:

22 the source driver and generate a drive waveform The gate driver for scanning gate lines outputs either VGH or VGL level The shift direction of 58-bit source outputs from the source driver is set with the SS bit and the shift direction of gate outputs from the gate driver is set with the GS bit The scan mode by the gate driver is set with the SM bit These bits allow setting an appropriate scan method for an LC module LC river Power Supply Circuit The LC drive power supply circuit generates the voltage levels VREGOUT, VGH, VGL and Vcom for driving an LC Page of 9 Version:

23 7 System Interface 7 Interface Specifications has the system interface to read/write the control registers and display graphics memory (GRAM), and the RGB Input Interface for displaying a moving picture User can select an optimum interface to display the moving or still picture with efficient data transfer All display data are stored in the GRAM to reduce the data transfer efforts and only the updating data is necessary to be transferred User can only update a sub-range of GRAM by using the window address function also has the RGB interface and VSYNC interface to transfer the display data without flicker the moving picture on the screen In RGB interface mode, the display data is written into the GRAM through the control signals of ENABLE, VSYNC, HSYNC, OTCLK and data bus [:] In VSYNC interface mode, the internal display timing is synchronized with the frame synchronization signal (VSYNC) The VSYNC interface mode enables to display the moving picture display through the system interface In this case, there are some constraints of speed and method to write data to the internal RAM operates in one of the following 4 modes The display mode can be switched by the control register When switching from one mode to another, refer to the sequences mentioned in the sections of RGB and VSYNC interfaces Operation Mode Internal operating clock only (isplaying still pictures) RGB interface () (isplaying moving pictures) RGB interface () (Rewriting still pictures while displaying moving pictures) VSYNC interface (isplaying moving pictures) RAM Access Setting (RM) System interface (RM = ) RGB interface (RM = ) System interface (RM = ) System interface (RM = ) isplay Operation Mode (M[:]) Internal operating clock (M[:] = ) RGB interface (M[:] = ) RGB interface (M[:] = ) VSYNC interface (M[:] = ) Note ) Registers are set only via the system interface Note ) The RGB-I/F and the VSYNC-I/F are not available simultaneously Page 3 of 9 Version:

24 System System Interface 8//6 ncs RS nwr n [:] ILI9 RGB Interface ENABLE VSYNC HSYNC OTCLK Figure System Interface and RGB Interface connection 7 Input Interfaces The following are the system interfaces available with the The interface is selected by setting the IM[3:] pins The system interface is used for setting instructions and RAM access IM3 IM IM IM/I Interface Mode Pin M68-system -bit interface [:], [8:] M68-system 8-bit interface [:] i8-system -bit interface [:], [8:] i8-system 8-bit interface [:] I Serial Peripheral Interface (SPI) SI, SO ([:]) Setting invalid M68-system8-bit interface [:] M68-system 9-bit interface [:9] i8-system8-bit interface [:] i8-system 9-bit interface [:9] Setting invalid Page 4 of 9 Version:

25 7 i8/8-bit System Interface The i8/8-bit system interface is selected by setting the IM[3:] as levels System ncs A nwr n [3:] 8 ncs RS nwr n [:] 8-bit System Interface (6K colors) TRI=, FM[:]= Input ata Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Figure 8-bit System Interface ata Format Page 5 of 9 Version:

26 7 i8/-bit System Interface The i8/-bit system interface is selected by setting the IM[3:] as levels System ncs A nwr n [:] ncs RS nwr n [:], [8:] -bit System Interface (65K colors) TRI=, FM[:]= Input ata Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B -bit System Interface MSB Mode (6K colors, Transfers/pixel) TRI= ", FM[:]= " Input ata 4 st Transfer nd Transfer Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B -bit System Interface LSB Mode (6K colors, Transfers/pixel) TRI= ", FM[:]= " Input ata st Transfer 4 nd Transfer Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Figure3 -bit System Interface ata Format Page 6 of 9 Version:

27 73 i8/9-bit System Interface The i8/9-bit system interface is selected by setting the IM[3:] as and the ~9 pins are used to transfer the data When writing the -bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first The display data is also divided in upper byte (9 bits) and lower byte, and the upper byte is transferred first The unused [8:] pins must be tied to either Vcc or AGN System ncs A nwr n [8:] 9 ncs RS nwr n [:9] 9-bit System Interface (6K colors) TRI=, FM[:]= Input ata st Transfer (Upper bits) 4 9 nd Transfer (Lower bits) 4 9 Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Figure4 9-bit System Interface ata Format 74 i8/8-bit System Interface The i8/8-bit system interface is selected by setting the IM[3:] as and the ~ pins are used to transfer the data When writing the -bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first The display data is also divided in upper byte (8 bits) and lower byte, and the upper byte is transferred first The written data is expanded into 8 bits internally (see the figure below) and then written into GRAM The unused [9:] pins must be tied to either Vcc or AGN Page 7 of 9 Version:

28 8-bit System Interface (65K colors) TRI=, FM[:]= Input ata st Transfer (Upper bits) 4 nd Transfer (Lower bits) 4 Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B 8-bit System Interface (496 colors) TRI=, FM[:]= Input ata 4 4 Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B 8-bit System Interface (6K colors) TRI=, FM[:]= Input ata st Transfer 4 nd Transfer 4 3rd Transfer 4 Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B 8-bit System Interface (65K colors) TRI=, FM[:]= Input ata st Transfer 4 nd Transfer 4 3rd Transfer 4 Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Figure5 8-bit System Interface ata Format Page 8 of 9 Version:

29 ata transfer synchronization in 8/9-bit bus interface mode supports a data transfer synchronization function to reset upper and lower counters which count the transfers number of upper and lower byte in 8/9-bit interface mode If a mismatch arises in the numbers of transfers between the upper and lower byte counters due to noise and so on, the h register is written 4 times consecutively to reset the upper and lower counters so that data transfer will restart with a transfer of upper byte This synchronization function can effectively prevent display error if the upper/lower counters are periodically reset RS nwr [:9] Upper/ Lower h h h h Upper Lower 8-/9-bit transfer synchronization Figure6 ata Transfer Synchronization in 8/9-bit System Interface 73 Serial Peripheral Interface (SPI) The Serial Peripheral Interface (SPI) is selected by setting the IM[3:] pins as x level The chip select pin (ncs), the serial transfer clock pin (SCL), the serial data input pin (SI) and the serial data output pin (SO) are used in SPI mode The I pin sets the least significant bit of the identification codethe [:] pins, which are not used, must be tied to either IOVcc or GN The SPI interface operation enables from the falling edge of ncs and ends of data transfer on the rising edge of ncs The start byte is transferred to start the SPI interface and the read/write operation and RS information are also included in the start byte When the start byte is matched, the subsequent data is received by The seventh bit of start byte is RS bit When RS =, either index write operation or status read operation is executed When RS =, either register write operation or RAM read/write operation is executed The eighth bit of the start byte is used to select either read or write operation (R/W bit) ata is written when the R/W bit is and read back when the R/W bit is After receiving the start byte, starts to transfer or receive the data in unit of byte and the data transfer starts from the MSB bit All the registers of the are -bit format and receive the first and the second Page 9 of 9 Version:

30 byte datat as the upper and the lower eight bits of the -bit register respectively In SPI mode, 5 bytes dummy read is necessary and the valid data starts from 6 th byte of read back data Start Byte Format Transferred bits S Start byte format Transfer start evice I code RS R/W I / / Note: I bit is selected by setting the IM/I pin RS and R/W Bit Function RS R/W Function Set an index register Read a status Write a register or GRAM data Read a register or GRAM data Page 3 of 9 Version: