SPF-2086T Low Noise phemt GaAs FET GHz Operation

Transcription

1 Product Description Sirenza Microdevices SPF2086T is a high performance 0.25µm phemt Gallium Arsenide FET with Schottky barrier gates. This 300µm device is ideally biased at 3V,20mA for lowest noise performance and battery powered requirements. At 5V,40mA the device delivers excellent output TOI of 32 m. It provides ideal performance as driver stages in many commercial, industrial and military LNA applications. SPF2086T Low Noise phemt GaAs FET GHz Operation Gain, Gmax () Typical Gain Performance 3v, 20mA 5v, 40mA Gmax Gain Frequency (GHz) Product Features 22 Gmax at 1.9 GHz 0.4 F MIN at 1.9 GHz +32 m Output IP3 +20 m Output Power at 1 Compression Applications LNA for Analog and Digital Wireless Systems 3G, Cellular, PCS Fixed Wireless, Pager Systems Driver Stage for low power applications Symbol Gmax Device Characteristics, T 25 C 3V, I (unless otherwise noted ) D Maximum Available Gain *, Z Z * L L Insertion Gain S 21 Z 50 F MIN OIP3 P1 IDS S L Ohms Minimum Noise Γ, Z Z L O PT Output Third Order Z, Z Z L SOPT Figure Intercept Point Output 1 Compression Point Z, Z Z L SOPT Saturated Drain Current V V 0V, DSP Tranconductance : g m V V 0.25V, DSP V PinchOff Voltage: P V, I 15 µa BV BV GD Rth 0 DS GatetoSource Breakdown Voltage 0.3mA, drain open I GatetoDrain Breakdown Voltage 0.3mA, V 3.0V I GD Test Condition [1] 100% Tested f 0.9 GHz f 1.9 GHz f GHz [1] f 1 GHz [1] f 1.9 GHz f 1 GHz f 2 GHz f 4 GHz f 6 GHz 5.0V, ID 3.0V, ID 5.0V, ID 3.0V, ID [1] U nits M in. T yp. Max m m m m ma ms 112 V V 17 8 V 17 8 o Thermal Resistance, junctiontolea d C/ W 110 The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in lifesupport devices and/or systems. Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved. Phone: (800) SMIMMIC 1 EDS Rev E

2 Operation of this device beyond any one of these parameters may cause permanent damage. MTTF is inversely proportional to the device junction temperature. For junction temperature and MTTF considerations the operating conditions should also satisfy the following experssions: where: P DC P OUT < (T J T L ) / R TH P DC I DS * (W) P OUT RF Output Power (W) T J Junction Temperature ( C) T L Lead Temperature (pin 4) ( C) R TH Thermal Resistance ( C/W) Absolute Maximum Ratings Drain C Forward Parameter urrent SPF2086T Low Noise FET Symbol Gate Current I SF Reverse Gate Current I SR DraintoSource GatetoDrain V GatetoSource RF Input Power Operating Storage Voltage oltage Voltage Temperature Temperature Range Power Dissipation Value I DS ID SS. 3 G. 3 G Unit ma 0 ma 0 ma + 7 V V GD 8 V V 5 or > 0 P IN 00 < V T OP 40 to mw C T stor 40 to +150 P DISS 00 C 6 mw Channel Temperature T J C Noise parameters, at typical operating frequencies Bias 3.0V, I DS FRE GHZ FMIN d B G OPT G OPT ANG r N W G A FRE Bias 5.0V, I DS GHZ FMIN d B G OPT G OPT ANG r N W G A Phone: (800) SMIMMIC 2 EDS Rev E

3 SPF2086T Low Noise FET Scattering Parameters: Typical Sparameters 3.0V, I DS 20 ma F req GHz S11 S 11 Ang S21 S 21 Ang S12 S 12 Ang S22 S22 Ang Note : Deembedded to device pins Phone: (800) SMIMMIC 3 EDS Rev E

4 SPF2086T Low Noise FET Scattering Parameters: Typical Sparameters 5.0V, I DS 40 ma F req GHz S11 S 11 Ang S21 S 21 Ang S12 S 12 Ang S22 S22 Ang Note : Deembedded to device pins Phone: (800) SMIMMIC 4 EDS Rev E

5 SPF2086T Low Noise FET Caution: ESD sensitive Appropriate precautions in handling, packaging and testing devices must be observed. Part Number Ordering Information Part Number Reel Size Devices/Reel S PF2086T 7" 1000 PCB Pad Layout Part Symbolization The part will be symbolized with the P2T designator and a dot signifying pin 1 on the top surface of the package. P2T Pin Designation 1 Gate 2 Source 3 Drain 4 Source Package Dimensions P2T Phone: (800) SMIMMIC 5 EDS Rev E