Overview of Syllabus and Class Policies. Chapter 0

Transcription

1 Overview of Syllabus and Class Policies 1 Chapter 0

2 2 Syllabus and Class Policies Instructor Hao Zhang Assistant Professor Department of Computer Science Office: BB URL: Office hours: 4:00-6:00 PM Thursdays at BB 250 Lunches on Tuesdays and Thursdays through the CS FUNCH Program Other hours available by appointment

3 3 Syllabus and Class Policies Teaching Assistant Sriram Siva Location: Alamode Lab (BB 136) Office hours: Mondays 3:30-4:30 pm Wednesdays 3:30-4:30 pm By appointment (through )

4 4 Syllabus and Class Policies Prerequisites CSCI 262 (Data Structure) CSCI 274 (Intro to Linux OS) CSCI 341 (Computer Organization) All prerequisites will be enforced.

5 5 Syllabus and Class Policies Textbook Operating Systems: Internals and Design Principles, 8th Edition (2014), by William Stallings, Prentice Hall (ISBN-13: ). 7th edition is okay, check this out: gs_operating_systems_7th_edition.pdf This edition is FREE!

6 6 Syllabus and Class Policies Communication Course website: For information purposes to the public Make sure to refresh the webpages every time you visit the course website! Project submission and grading through CANVAS

7 7 Syllabus and Class Policies

8 8 Syllabus and Class Policies Topic Overview Computer System Overview (Chapter 1) Operating System Overview (Chapter 2) Process Description and Control (Chapter 3) Threads (Chapter 4) Processor Scheduling (Chapter 9) Memory Management (Chapter 7) Virtual Memory (Chapter 8) Concurrency (Chapters 5 and 6)

9 9 Syllabus and Class Policies Workload Seven homework assignments (may vary) Three projects: A warm-up project and two main projects. Main projects can be time-consuming. Your code must run on the ALAMODE lab s Arch LINUX machines or in Ubuntu OS Midterm exam Final exam (accumulative, covering all materials, with more focus on the 2 nd half of the semester) Be prepared!!!

10 10 Syllabus and Class Policies Evaluation Grades (100 pt) will be assigned acc. to: Homework: 14 points Project: 41 ( ) points Midterm exam: 20 points Final exam: 25 points Course Eval: 1 extra point Final grades will be determined by A: B+: B: C+: C: D: F:

11 11 Syllabus and Class Policies Class Attendance will be taken It will not be officially a portion of your final grade. But decisions on borderline grades will be based upon class attendance and participation If you have a good reason to miss class (e.g., sickness, conference travel, job interview), then it is not a problem If you think you have a contagious illness, please don t come to class. The instructor will help keep you posted on class activities In any case, it is your responsibility to catch up (or keep up) with all course material and announcements covered in class

12 12 Syllabus and Class Policies Assignments Assignment write-ups will be posted on the course website, along with the due dates Submit paper copies of homework assignments before the class (i.e., 11:00 AM in the Fall 2018 Semester) on the due date. The project deadline is midnight, and due to Canvas.

13 13 Syllabus and Class Policies Due Dates and Late Assignments All assignments are due at the date and time stated, except for extenuating circumstances. No homework submission will be accepted FIVE (5) minutes after the due time (i.e., 11:05 AM, when solutions are handed over).

14 14 Syllabus and Class Policies Grading Corrections Bring any assignment grading correction requests to the instructor within ONE (1) week of receiving the grade, or before the end of the semester, whichever comes first After that, your grade will not be adjusted. If you find any mistake in grading, please let the instructor know. Your grade will not be lowered.

15 15 Syllabus and Class Policies Computer/phone use in class Please be respectful of your colleagues in class, by turning off your phones and using your computers only for taking notes or keeping up with the material covered in class. Checking your , working on other nonclass related materials, web-surfing, etc., are not allowed Discrimination and Harassment This will be NOT tolerated!!

16 16 Syllabus and Class Policies Collaboration Policy Discussing ideas is encouraged Reading through the Student Honor Code and the policy existing for all CS courses in the Department of Computer Science Cheating will be dealt with harshly! That homework or project will have a 0 score. All issues of misconduct are reported to the Dean of Student

17 17 Syllabus and Class Policies Accommodations If you need any accommodations, please let the instructor know, the early, the better A Last Note The slides and projects used in this semester is directly from (e.g., projects) or adapted from (e.g., slides) the course materials developed and/or used by multiple CS faculty in previous semesters. Many texts, figures, and almost all videos are from online resources.

18 18 Before we start the course, I want to know: What immediately comes in to your mind when you know the term Operating System for the first time?

19 19 What immediately comes in to your mind when you know the term Operating System for the first time?

20 20 What immediately comes in to your mind when you know the term Operating System for the first time? For example An Operating System (OS) makes the computing power available to users by controlling the hardware Let us manage computer hardware and software OS serves as an interface between user and hardware

21 Computer System Overview 21 Chapter 1

22 22 Computer Hardware Why should we care about hardware? Operating systems are the interface between the user and computer hardware OS design is influenced by available hardware OS design is also influenced by user needs Hardware evolves to meet the needs of operating systems

23 23 Basic Components Processor (CPU) Controls the operation of the computer Performs data processing functions Main Memory (real memory, or primary memory) Stores data and programs Non-persistent, lost on restart (volatile)

24 24 Basic Components I/O modules input / output : moves data between the computer and its external environments Examples: Hard disks, keyboard, monitors, printers, and network (e.g., Wifi) System interconnection (bus) Communication among processors, memory, and I/O modules

25 25 Basic Components

26 26 Processor The processor is the heart of a computer Known as a central processing unit (CPU) Performs general-purpose operations arithmetic operations (adding, subtracting, multiplying, ) logical operations (AND, OR, XO, ) control operations (jumps, branches, statesetting operations, )

27 27 Processor Having multiple cores and/or processors is now common On each core, instructions are still executed sequentially But multiple sets of instructions can be executed in parallel on different cores Modern processors can contain numerous other capabilities Onboard GPUs (graphical processing units), which are increasingly being used as heavyweight numerical compute units (not just for graphics) Specialized modules, e.g., for hardware audio and video transcoding or encryption

28 28 In most part of this class, we will focus on singleprocessor, single-core systems for simplicity to learn the concepts of OS

29 29 Registers The data on which a processor operates are stored in registers Registers are small and extremely fast data storage, built directly into the processor User-visible registers: program counter (PC): holds the address of the next instruction to be fetched instruction register (IR): contains the actual instruction to be executed program status word (PSW): contains multiple flag bits data registers: hold general-purpose values (such as program data) address registers: hold addresses used by instructions (e.g., addresses of operated data)

30 30 Registers Internal registers: memory address register (MAR): contains the address of the memory location to read or write memory buffer register (MBR): contains the data to write to, or that was read from, memory i/o address register (I/O AR) and i/o buffer register (I/O BR): the equivalents of the MAR and MBR, but used for general IO transfers

31 31 Main Memory Memory basics consists of many individually addressable slots each slot can store either data or instructions The CPU cannot use main memory directly data must first be transferred into CPU registers Instructions refer to memory addresses these addresses specify the data or instructions to fetch into registers once in registers, the CPU can directly act on the data

32 32 I/O Module Structure Data to/from system bus are buffered in data register(s)

33 33 System Bus

34 34 Basic Instruction Execution Computer execute programs programs consist of individual instructions these instructions, and the data on which they operate, are stored in memory Instruction cycle (high-level): Fetch the next instruction Execute the instruction Repeat

35 35 General Types of Instructions Transferring data between processor and memory processor may request data be loaded from memory into a CPU register processor may request processed data in a CPU register be written to memory Processor-I/O interactions data may be transferred to or from a peripheral device using I/O modules Data processing processor performs arithmetic or logical operation on data in registers Control instructions may specify that the sequence of execution be altered jumps and branching: function calls, loops, conditionals, etc. state-setting instructions: set privilege level, update status bits, etc.

36 36 Example of Execution Flow Hypothetical 16-bit Instruction Format

37 37 Example of Execution Flow Hypothetical 16-bit Instruction Format

38 38 Example of Execution Flow Hypothetical 16-bit Instruction Format

39 39 Example of Execution Flow Hypothetical 16-bit Instruction Format

40 40 Example of Execution Flow Hypothetical 16-bit Instruction Format

41 41 Example of Execution Flow Hypothetical 16-bit Instruction Format

42 42 Example of Execution Flow Hypothetical 16-bit Instruction Format How does this Execution Flow/Cycle work?

43 43 Example of Execution Flow

44 44 Example of Execution Flow

45 45 Example of Execution Flow

46 46 Example of Execution Flow

47 47 Example of Execution Flow

48 48 Example of Execution Flow

49 49

50 50 VidShow: History of Computers

51 51 Challenges of I/O Speed I/O operations are almost always much slower than CPU operations Example A 1 GHz processor is capable of executing 10^9 (1 billion) operations per second A 7200-RPM spinning hard drive has an average access time of roughly 4ms The hard drive is four million times slower than the processor CPU is super fast I/O is very slow

52 52 Challenges of I/O Speed

53 53 Challenges of I/O Speed Processors can t idle while waiting on I/O Computers would be impossibly slow, otherwise

54 54 Interrupts Interrupts A mechanism by which other modules can interrupt (loosely speaking, suspend and resume) normal CPU execution Why are they useful Interrupts allow the CPU to fire and forget As soon as the requested long-running I/O operation completes, it will fire an interrupt that notifies the CPU The CPU can be doing something else in the meantime, while an Interrupt Handler Routine (normally part of the OS) is dealing with the I/O

55 55 Interrupts

56 56 Interrupts Computers execute multiple programs at once If one program needs to block on an I/O operation, the processor can switch to working on a different program As soon as the I/O finishes, the original program can be resumed right where it left off after the interrupt Interrupts are used in all modern computers Multi-tasking computers rely on interrupts Hundreds of interrupts occur every second Generally, we can assume interrupts occur randomly

57 57 Instruction Cycle with Interrupts CPU checks for interrupts after each instruction If no interrupts, then fetch the next instruction for the current program If an interrupt is pending, then suspend execution of the current program, and execute the interrupt handler

58 58 Interrupt Handler Interrupt Handler is a program (a sequence of instructions/code) that determines nature of the interrupt and performs whatever actions are needed Control is transferred to this interrupt handler program Control must be transferred back to the interrupted program so that it can be resumed from the point of interruption Thus: must save the state of the program (content of PC + registers +...)

59 59 Interrupts Interrupts are transparent to user programs you can write code and never have to think about interrupts Interrupts can happen at any point in a program, at any time not all interrupts are the result of I/O requests issued by a given program the operating system uses interrupts to ensure that it maintains control of the computer hardware interrupts can happen as the result of program bugs and more

60 60 Interrupts Interrupts are transparent to user programs you can write code and never have to think about interrupts Interrupts can happen at any point in a program, at any time

61 61 Interrupt Processing Handling interrupts involves both hardware and software E.g., the interrupt flag is stored in a piece of register Hardware steps issuing the interrupt checking for the occurrence of an interrupt at the end of each/every instruction cycle processor pushes the PSW (program status word, a register) onto a control stack processor sets the PC to the first instruction in the appropriate interrupt handler

62 62 Interrupt Processing Software steps (by operating system) OS may needs to save additional context (e.g., process state info, such as process ID, the user it belongs to, how long it has run, among others) handle the interrupt as necessary restore the program s process state info restore the PSW (program status word) and PC of the program to resume

63 63 Interrupt A lot is happening in response to an interrupt However, considering the 4M speed difference between CPU and I/O, the benefits substantially outweigh the extra cost!

64 64 Handling Multiple interrupts We ve so far only discussed a single interrupt However, interrupts happen all the time A network device fires an interrupt every time it receives a package Reading from a file or performing other I/O will cause an interrupt Short Discussion: How to handle multiple interrupts? What are the key considerations?

65 65 Handling Multiple interrupts We ve so far only discussed a single interrupt However, interrupts happen all the time A network device fires an interrupt every time it receives a package Reading from a file or performing other I/O will cause an interrupt Multiple interrupts can be handled in two ways Sequential interrupt processing Nested interrupt processing

66 66 Sequential Processing Disable new interrupts during an ongoing interrupt New interrupts remain pending until the previous interrupt finishes After interrupt handler routine completes, the processor checks for additional interrupts

67 67 Nested Interrupt Processing New interrupts will be processed immediately Cause the currently running interrupt handler to be interrupted

68 68 Priority-based interrupt: Communication > Disk > Printer E.g.: when input arrives from communication devices, it needs to be absorbed quickly to make room for more input

69 69 Memory Hierarchy Providing the processor with the data it needs is critical (i.e., program instructions and operands) Without data, there s nothing for the processor to do Memory access is highly optimized, with multiple levels forming a hierarchy As you go up the hierarchy (closer to the processor) speed increases size decreases cost increases (more accurately, cost per unit)

70 70 Memory Hierarchy

71 71 Memory Hierarchy At the top of the hierarchy (inboard memory) registers (super fast, super small, super expensive) cache (fast, small, expensive) main memory (relatively fast, relatively large, relatively cheap) In the middle (outboard storage): hard disk (relatively slow, huge, super cheap) At the bottom (offline storage): tape, cloud storage, etc. (slow, beyond huge, and almost free)

72 72

73 73 Think-Pair-Share Q.01

74 74 Cache Memory For each instruction executed memory is accessed at least once to fetch the next instruction memory might be accessed additional times to fetch operands

75 75 Cache Memory The rate at which the CPU can execute is limited by memory speed (MHz level) this has been a problem because increases in CPU speed have historically drastically outpaced increases in memory speed ideally, all memory would be as fast as CPU registers, but that would be prohibitively expensive

76 76 Cache Memory Hardware has adapted by providing one or more levels of cache if the requested data is in the currently level of cache, no access to the next level is necessary cache hierarchy is transparent to the operating system

77 77 Cache Memory

78 78 Cache Read Operation

79 79 Short Discussion: 1. As caching introduces additional overhead, why does caching still work? 2. Clue: If memory access is completely random, do you think cache still works?

80 80 Locality of reference Memory reference for both instruction and operand data tend to cluster over a relatively long period of time. Example Once a loop is entered, there is frequent access to a small set of instructions Operations on arrays/matrix involve access to a cluster set of data that can be stored sequentially Hence: once a word gets referenced, it is likely that nearby words will get referenced often in the near future. Thus, the hit ratio will be close to 1 even for a small cache.

81 81 Spatial locality the tendency to access memory locations that are clustered Instructions are executed sequentially most of the time An array of data is stored sequentially Program execution tends to be sequential

82 82 Spatial locality the tendency to access memory locations that are clustered Instructions are executed sequentially most of the time An array of data is stored sequentially Program execution tends to be sequential

83 83 Spatial locality the tendency to access memory locations that are clustered Instructions are executed sequentially most of the time An array of data is stored sequentially Program execution tends to be sequential

84 84 Spatial locality the tendency to access memory locations that are clustered Instructions are executed sequentially most of the time An array of data is stored sequentially Program execution tends to be sequential

85 85 Spatial locality the tendency to access memory locations that are clustered Instructions are executed sequentially most of the time An array of data is stored sequentially Program execution tends to be sequential

86 86 Spatial locality the tendency to access memory locations that are clustered Instructions are executed sequentially most of the time An array of data is stored sequentially Certain data structures tend to be sequential

87 87 Spatial locality the tendency to access memory locations that are clustered Instructions are executed sequentially most of the time An array of data is stored sequentially Certain data structures tend to be sequential

88 88 Temporal locality The tendency to access memory locations that have been used recently E.g., when executing a loop, the same set of instructions are executed repeatedly Loops execute the same set of instructions repeatedly

89 89 Locality of reference Real programs frequently exhibit strong locality! With this property, even SMALL caches make a HUGE difference!

90 90 Effective Access Time (EAT) EAT measures the average time required by a memory access Calculation must consider: The access time (or speed ) of different memory levels The hit ratio, that is the probability that a given reference can be found in each level

91 91 Effective Access Time (EAT) In a two-level memory system (e.g. cache and main memory) From data perspective

92 92 Effective Access Time (EAT) In a two-level memory system (e.g. cache and main memory) From cache hierarchy perspective

93 93 Symmetric Multiprocessors Two or more similar processors of comparable capability same functions => symmetric processors share the same main memory and I/O facilities processors are interconnected by a bus or other internal connection scheme Benefits Availability: the failure of a single processor does not halt the machine Incremental growth: system performance can be enhanced of a system by adding additional processors Scaling: vendors can offer a range of products with different price and performance characteristics

94 94 Symmetric Multiprocessors

95 95 Multi-core Processors A multicore computer combines two or more cores on a single chip Historically: microprocessors have steadily increased exponentially in performance increases in clock frequency increasing miniaturization increases in complexity of processor pipelines Now: CPU designers are reaching practical limits! So, just wire up multiple processors and multiple cores, and add bigger caches!

96 96 Multi-core Processors Intel i7 Processor Notice the multiple SMALL caches

97 97 Multi-core Processors

98 98

99 99 Homework Assignment 1 Chapter 1 Problems 1.1, 1.10, 1.12, and an EAT problem. Detail is presented on course website: ment.html Write down your full name clearly. Note: Problems are NOT Review Questions in the text book! Turn in hard copy solutions before the beginning of the class.

100 100 Project 0: Warm-Up

101 101 Project 0: Warm-Up

102 102