μpd78f0711, 78F0712 User s Manual 8-Bit Single-Chip Microcontrollers Document No. U17890EJ2V0UD00 (2nd edition) Date Published October 2007 NS

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1 User s Manual μpd78f711, 78F712 8-Bit Single-Chip Microcontrollers μpd78f711 μpd78f712 Document No. U1789EJ2VUD (2nd edition) Date Published October 27 NS Printed in Japan 26

2 [MEMO] 2 User s Manual U1789EJ2VUD

3 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. User s Manual U1789EJ2VUD 3

4 EEPROM, IECUBE, and MINICUBE are registered trademarks of NEC Electronics Corporation in japan and Germany. Windows, Windows NT, and Windows XP are registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9 series 7 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. TRON is an abbreviation of The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash technology licensed from Silicon Storage Technology, inc. The information in this document is current as of August, 27. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E User s Manual U1789EJ2VUD

5 INTRODUCTION Readers This manual is intended for user engineers who wish to understand the functions of the μpd78f711, 78F712 and design and develop application systems and programs for this device. The target product is as follows. μpd78f711, 78F712 Purpose Organization This manual is intended to give users an understanding of the functions described in the Organization below. The μpd78f711, 78F712 manual is separated into two parts: this manual and the instructions edition (common to the 78K/ Series). μpd78f711, 78F712 User s Manual (This Manual) 78K/ Series User s Manual Instructions Pin functions Internal block functions Interrupts Other on-chip peripheral functions Electrical specifications CPU functions Instruction set Explanation of each instruction How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. To gain a general understanding of functions: Read this manual in the order of the CONTENTS. The mark <R> shows major revised points. The revised points can be easily searched by copying an <R> in the PDF file and specifying it in the Find what: field. How to interpret the register format: For a bit number enclosed in angle brackets, the bit name is defined as a reserved word in the RA78K, and is defined as an sfr variable using the #pragma sfr directive in the CC78K. To check the details of a register when you know the register name. See APPENDIX B REGISTER INDEX. To know details of the 78K/ Series instructions. Refer to the separate document 78K/ Series Instructions User s Manual (U12326E). Conventions Data significance: Higher digits on the left and lower digits on the right Active low representations: (overscore over pin and signal name) Note: Footnote for item marked with Note in the text. Caution: Information requiring particular attention Remark: Supplementary information Numerical representations: Binary... or B Decimal... Hexadecimal... H User s Manual U1789EJ2VUD 5

6 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. μpd78f711, 78F712 User s Manual This manual 78K/ Series Instructions User s Manual U12326E Documents Related to Development Tools (Software) (User s Manuals) Document Name Document No. RA78K Ver.3.8 Assembler Package CC78K Ver.3.7 C Compiler Operation Language Structured Assembly Language Operation Language U17199E U17198E U17197E U1721E U172E ID78K-QB Series Integrated Debugger Ver or Later Operation U1833E PM+ Ver. 5.2 U16934E Documents Related to Development Tools (Hardware) (User s Manuals) Document Name Document No. <R> QB In-Circuit Emulator QB-78KMINI On-Chip Debug Emulator QB-MINI2 On-Chip Debug Emulator with Programming Function U1781E U1729E U18371E Documents Related to Flash Memory Programming PG-FP4 Flash Memory Programmer User s Manual Document Name Document No. U1526E Other Documents Document Name SEMICONDUCTOR SELECTION GUIDE Products and Packages Semiconductor Device Mount Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Document No. X13769X Note C11531E C1983E C11892E Note See the Semiconductor Device Mount Manual website ( Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. 6 User s Manual U1789EJ2VUD

7 CONTENTS CHAPTER 1 OUTLINE Features Applications Ordering Information Pin Configuration (Top View) Block Diagram Outline of Functions CHAPTER 2 PIN FUNCTIONS Pin Function List Description of Pin Functions P to P3 (port ) P13, P14, P16, P17 (port 1) P2 to P23 (port 2) P5, P53, P54 (port 5) TWTO/RTP1 to TWTO5/RTP AVREF AVSS RESET X1 and X VDD VSS FLMD Pin I/O Circuits and Recommended Connection of Unused Pins CHAPTER 3 CPU ARCHITECTURE Memory Space Internal program memory space Internal data memory space Special function register (SFR) area Data memory addressing Processor Registers Control registers General-purpose registers Special function registers (SFRs) Instruction Address Addressing Relative addressing Immediate addressing Table indirect addressing Register addressing Operand Address Addressing Implied addressing Register addressing...48 User s Manual U1789EJ2VUD 7

8 3.4.3 Direct addressing Short direct addressing Special function register (SFR) addressing Register indirect addressing Based addressing Based indexed addressing Stack addressing CHAPTER 4 PORT FUNCTIONS Port Functions Port Configuration Port Port Port Port Registers Controlling Port Function Port Function Operations Writing to I/O port Reading from I/O port Operations on I/O port Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) CHAPTER 5 CLOCK GENERATOR Functions of Clock Generator Configuration of Clock Generator Registers Controlling Clock Generator System Clock Oscillator X1 oscillator Examples of Incorrect Resonator Connection Internal high-speed oscillator Internal low-speed oscillator Prescaler Clock Generator Operation Time Required to Switch Between Internal Low-speed Oscillation Clock and High-speed System Clock Time Required for CPU Clock Switchover Clock Switching Flowchart and Register Setting Switching from internal low-speed oscillation clock to high-speed system clock Switching from high-speed system clock to internal low-speed oscillation clock Register settings CHAPTER 6 1-BIT INVERTER CONTROL TIMER Outline of 1-Bit Inverter Control Timer Function of 1-Bit Inverter Control Timer Configuration of 1-Bit Inverter Control Timer User s Manual U1789EJ2VUD

9 6.4 Registers Controlling 1-Bit Inverter Control Timer Registers Controlling 1-Bit Inverter Control Timer CHAPTER 7 16-BIT TIMER/EVENT COUNTER Functions of 16-Bit Timer/Event Counter Configuration of 16-Bit Timer/Event Counter Registers Controlling 16-Bit Timer/Event Counter Operation of 16-Bit Timer/Event Counter Interval timer operation PPG output operations Pulse width measurement operations External event counter operation Square-wave output operation One-shot pulse output operation Cautions for 16-Bit Timer/Event Counter CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 5 AND Functions of 8-Bit Timer/Event Counters 5 and Configuration of 8-Bit Timer/Event Counters 5 and Registers Controlling 8-Bit Timer/Event Counters 5 and Operations of 8-Bit Timer/Event Counters 5 and Operation as interval timer Operation as external event counter (Timer 5 only) Square-wave output operation (Timer 5 only) PWM output operation (Timer 5 only) Cautions for 8-Bit Timer/Event Counters 5 and CHAPTER 9 WATCHDOG TIMER Functions of Watchdog Timer Configuration of Watchdog Timer Registers Controlling Watchdog Timer Operation of Watchdog Timer Watchdog timer operation when Internal low-speed oscillator cannot be stopped is selected by option byte Watchdog timer operation when Internal low-speed oscillator can be stopped by software is selected by option byte Watchdog timer operation in STOP mode (when Internal low-speed oscillation can be stopped by software is selected by option byte) Watchdog timer operation in HALT mode (when Internal low-speed oscillation can be stopped by software is selected by option byte) CHAPTER 1 REAL-TIME OUTPUT PORT Function of Real-Time Output Port Configuration of Real-Time Output Port User s Manual U1789EJ2VUD 9

10 1.3 Registers Controlling Real-Time Output Port Operation of Real-Time Output Port Using Real-Time Output Port Notes on Real-Time Output Port CHAPTER 11 DC INVERTER CONTROL FUNCTION CHAPTER 12 Hi-Z OUTPUT CONTROLLER Hi-Z Output Controller Functions Configuration of Hi-Z Output Controller Register for Controlling Hi-Z Output Controller Operation of Hi-Z Output Controller CHAPTER 13 A/D CONVERTER Functions of A/D Converter Configuration of A/D Converter Registers Used in A/D Converter Relationship Between Input Voltage and A/D Conversion Results A/D Converter Operations Basic operations of A/D converter Trigger modes Operation modes Power-fail monitoring function How to Read A/D Converter Characteristics Table Cautions for A/D Converter CHAPTER 14 SERIAL INTERFACE UART Functions of Serial Interface UART Configuration of Serial Interface UART Registers Controlling Serial Interface UART Operation of Serial Interface UART Operation stop mode Asynchronous serial interface (UART) mode Dedicated baud rate generator CHAPTER 15 MULTIPLIER/DIVIDER Functions of Multiplier/Divider Configuration of Multiplier/Divider Register Controlling Multiplier/Divider Operations of Multiplier/Divider Multiplication operation Division operation User s Manual U1789EJ2VUD

11 CHAPTER 16 INTERRUPT FUNCTIONS Interrupt Function Types Interrupt Sources and Configuration Registers Controlling Interrupt Functions Interrupt Servicing Operations Maskable interrupt request acknowledgement Software interrupt request acknowledgment Multiple interrupt servicing Interrupt request hold CHAPTER 17 STANDBY FUNCTION Standby Function and Configuration Standby function Registers controlling standby function Standby Function Operation HALT mode STOP mode CHAPTER 18 RESET FUNCTION Register for Confirming Reset Source CHAPTER 19 POWER-ON-CLEAR CIRCUIT Functions of Power-on-Clear Circuit Configuration of Power-on-Clear Circuit Operation of Power-on-Clear Circuit Cautions for Power-on-Clear Circuit CHAPTER 2 LOW-VOLTAGE DETECTOR Functions of Low-Voltage Detector Configuration of Low-Voltage Detector Registers Controlling Low-Voltage Detector Operation of Low-Voltage Detector Cautions for Low-Voltage Detector CHAPTER 21 OPTION BYTES CHAPTER 22 FLASH MEMORY Internal Memory Size Switching Register Writing with Flash Memory Programmer Programming Environment Communication Mode User s Manual U1789EJ2VUD 11

12 22.5 Processing of Pins on Board FLMD pin FLMD1 pin Serial interface pins RESET pin Port pins Other signal pins Power supply Programming Method Controlling flash memory Flash memory programming mode Selecting communication mode Communication commands Flash Memory Programming by Self-Writing Registers used for self-programming function CHAPTER 23 ON-CHIP DEBUG FUNCTION CHAPTER 24 INSTRUCTION SET Conventions Used in Operation List Operand identifiers and specification methods Description of operation column Description of flag operation column Operation List Instructions Listed by Addressing Type CHAPTER 25 ELECTRICAL SPECIFICATIONS CHAPTER 26 PACKAGE DRAWINGS CHAPTER 27 CAUTIONS FOR WAIT Cautions for Wait Peripheral Hardware That Generates Wait Example of Wait Occurrence APPENDIX A DEVELOPMENT TOOLS A.1 Software Package A.2 Language Processing Software A.3 Control Software A.4 Flash Memory Programming Tools A.4.1 When using flash memory programmer PG-FP5, FL-PR5, PG-FP4, FL-PR4, and PG-FPL A.4.2 When using on-chip debug emulator with programming function QB-MINI User s Manual U1789EJ2VUD

13 A.5 Debugging Tools (Hardware) A.5.1 When using in-circuit emulator QB A.5.2 When using on-chip debug emulator QB-78KMINI A.5.3 When using on-chip debug emulator with programming function QB-MINI A.6 Debugging Tools (Software) APPENDIX B REGISTER INDEX B.1 Register Index (In Alphabetical Order with Respect to Register Names) B.2 Register Index (In Alphabetical Order with Respect to Register Symbol) APPENDIX C REVISION HISTORY C.1 Major Revisions in This Edition User s Manual U1789EJ2VUD 13

14 CHAPTER 1 OUTLINE <R> The μpd78f711 and 78F712 are 8-bit single-chip microcontrollers which use a 78K/ CPU core and incorporate peripheral functions, such as ROM/RAM, a timer/counter, a serial interface, an A/D converter, and a watchdog timer. The μpd78f711 and 78F712 are products of a series developed for motor applications performing 2-chip control and which specializes in motor control. They incorporate a 1-bit inverter control timer (CHAPTER 6) that enables PWM output with dead time and a Hi-Z output controller (CHAPTER 12) that controls the high impedance (Hi-Z) of 6- phase PWM for fail-safe. Furthermore, they are equipped with a real-time output port (CHAPTER 1) for controlling a stepping motor or a DC inverter (12 excitation), and achieve a high cost performance for various motor applications. 14 User s Manual U1789EJ2VUD

15 CHAPTER 1 OUTLINE 1.1 Features Minimum instruction execution time can be changed from high speed (.1 2 MHz operation with) X1 input clock) to low-speed ( khz operation with internal low-speed oscillation clock) On-chip internal high-speed oscillator (8 MHz (TYP.)) General-purpose register: 8 bits 32 registers (8 bits 8 registers 4 banks) On-chip multiplier/divider 16 bits 16 bits = 32 bits (multiplication) 32 bits 16 bits = 32 bits, 16 bits remainder (division) ROM, RAM capacities Part Number Item Program Memory (ROM) Data Memory (Internal High-Speed RAM) μpd78f712 Flash memory 16 KB 768 bytes μpd78f711 8 KB On-chip single-power-supply flash memory Self-programming On-chip debug function On-chip power-on-clear (POC) circuit and low-voltage detector (LVI) Short startup is possible via the CPU default start using the internal low-speed oscillator On-chip watchdog timer (operable with internal low-speed oscillation clock) On-chip real-time output ports I/O ports: 15 Timer: 5 channels Serial interface: 1 channel (UART: 1 channel) 1-bit resolution A/D converter: 4 channels Supply voltage: VDD = 4. to 5.5 V Operating ambient temperature: TA = 4 to +85 C User s Manual U1789EJ2VUD 15

16 CHAPTER 1 OUTLINE 1.2 Applications Household electrical appliances Refrigerator (compressor) Washing machine, Dryer (drum) Air conditioner units (fan control) Industrial equipment Pumps control,etc. 1.3 Ordering Information Part Number Package μpd78f712mc-5a4-a 3-pin plastic SSOP (7.62 mm (3)) μpd78f711mc-5a4-a 3-pin plastic SSOP (7.62 mm (3)) Remark Products with -A at the end of the part number are lead-free products. 16 User s Manual U1789EJ2VUD

17 CHAPTER 1 OUTLINE 1.4 Pin Configuration (Top View) 3-pin plastic SSOP (7.62 mm (3)) ANI1/P ANI2/P22 ANI/P ANI3/P23 TWTO5/RTP AVSS TWTO4/RTP AVREF TWTO3/RTP P/INTP/TWTOFFP RESET 6 25 P1/INTP1 FLMD 7 24 P2/INTP2 X P3/INTP3/ADTRG X P17/FLMD1 VDD 1 21 P16 VSS 11 2 P14/TxD VDD P13/RxD TWTO2/RTP P54/TI1/TO TWTO1/RTP P53/TI/INTP5 TWTO/RTP P5/TI5/TO5 Caution Connect the AVSS pin to VSS. Pin Identification ADTRG: A/D trigger input ANI to ANI3: Analog input AVREF: AVSS: FLMD, FLMD1: INTP to INTP3: INTP5: P to P3: Port P13, P14, P16, P17: Port 1 P2 to P23: Port 2 P5, P53, P54: Port 5 RESET: Reset Analog reference voltage Analog ground Flash programming mode External interrupt input External interrupt input RTP1 to RTP15: Real-time output port RxD: Receive data TI, TI1: Timer input TI5: Timer input TO: Timer output TO5: Timer output TWTO to TWTO5: Timer output TWTOFFP: Timer output off TxD: Transmit data VDD: VSS: Power supply Ground X1, X2: Crystal oscillator (X1 input clock) User s Manual U1789EJ2VUD 17

18 CHAPTER 1 OUTLINE 1.5 Block Diagram TWTO to TWTO5 TWTOFFP/P 6 1-bit INVERTER CONTROL TIMER TW PORT 4 P to P3 TO/TI1/P54 TI/P53 16-bit TIMER/ EVENT COUNTER PORT 1 PORT P13, P14, P16, P17 P2 to P23 TI5/TO5/P5 8-bit TIMER/ EVENT COUNTER 5 PORT 5 3 P5, P53, P54 8-bit TIMER/ EVENT COUNTER 51 POWER ON CLEAR/ LOW VOLTAGE INDICATOR POC/LVI CONTROL RTP1 to RTP15 6 WATCHDOG TIMER REAL-TIME OUTPUT PORT 78K/ CPU CORE FLASH MEMORY RESET CONTROL INTERNAL OSCILLATOR SYSTEM CONTROL RESET X1 X2 RxD/P13 TxD/P14 SERIAL INTERFACE UART INTERNAL HIGH-SPEED RAM ADTRG/P3 ANI/P2 to ANI3/P23 AVREF AVSS 4 A/D CONVERTER INTP/P to INTP3/P3 INTP5/P53 4 INTERRUPT CONTROL MULTIPLIER & DIVIDER VDD VSS FLMD, FLMD1 18 User s Manual U1789EJ2VUD

19 CHAPTER 1 OUTLINE 1.6 Outline of Functions Item μpd78f711 μpd78f712 Internal memory Flash memory (selfprogramming supported) High-speed RAM 8 KB 16 KB 768 B Memory space X1 input clock (oscillation frequency) Internal high-speed oscillation clock Internal low-speed oscillation clock General-purpose registers Minimum instruction execution time 64 KB Ceramic oscillator/crystal resonator /external clock [2 MHz (VDD = 4. to 5.5 V)] Internal high-speed oscillator (8 MHz (TYP.)) Internal low-speed oscillator (24 khz (TYP.)) 8 bits 32 registers (8 bits 8 registers 4 banks).1 μs/.2 μs/.4 μs/.8 μs/1.6 μs (X1 input fxp = 2 MHz operation) 8.3 μs/16.6 μs/33.2 μs/66.4 μs/132.8 μs (TYP.) ( Internal low-speed oscillation frl = 24 khz (TYP.) operation) Instruction set 16-bit operation Multiply/divide (8 bits 8 bits, 16 bits 8 bits) Bit manipulate (set, reset, test, and Boolean operation) BCD adjust, etc. I/O ports Total: 15 CMOS I/O: 11 CMOS input: 4 Timers 1-bit inverter control timer: 1 channel 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 2 channels Watchdog timer: 1 channel Timer outputs 8 (inverter control output: 6) Real-time output ports 6 bits 1 or 4 bits 1 A/D converter Serial interface Multiplier/divider Vectored interrupt sources Reset Supply voltage 1-bit resolution 4 channels UART mode: 1 channel 16 bits 16 bits = 32 bits (multiplication) 32 bits 16 bits = 32 bits remainder of 16 bits (division) Internal 14 External 5 Reset using RESET pin Internal reset by watchdog timer Internal reset by power-on-clear Internal reset by low-voltage detector VDD = 4. to 5.5 V Operating ambient temperature TA = 4 to +85 C Package 3-pin plastic SSOP (7.62 mm (3)) User s Manual U1789EJ2VUD 19

20 CHAPTER 1 OUTLINE An outline of the timer is shown below. 1-Bit Inverter Control Timer 16-Bit Timer/ Event Counter 8-Bit Timer/ Event Counters 5 and 51 Watchdog Timer TM5 TM51 Operation mode Interval timer 1 channel 1 channel 1 channel 1 channel External event counter 1 channel 1 channel Function Timer output 6 outputs 1 output 1 output PPG output 1 output PWM output 6 outputs 1 output Pulse width measurement 2 inputs Square-wave output 1 output 1 output Watchdog timer 1 channel Interrupt source User s Manual U1789EJ2VUD

21 CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List There are two types of pin I/O buffer power supplies: AVREF, and VDD. The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply AVREF VDD P2 to P23 Note Corresponding Pins Pins other than P2 to P23 <R> Note Connect AVREF to VDD when port 2 is used as a digital port. (1) Port pins Pin Name I/O Function After Reset Alternate Function P P1 P2 P3 I/O Port. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input INTP/TWTOFFP INTP1 INTP2 INTP3/ADTRG P13 P14 P16 P17 I/O Port 1. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input RxD TxD FLMD1 P2 to P23 Input Port 2. 4-bit input-only port. Input ANI to ANI3 P5 I/O Port 5. Input TI5/TO5 P53 P54 3-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. TI/INTP5 TI1/TO User s Manual U1789EJ2VUD 21

22 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins Pin Name I/O Function After Reset Alternate Function INTP INTP1 INTP2 Input External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified Input P/TWTOFFP P1 P2 INTP3 P3/ADTRG INTP5 P53/TI RxD Input Serial data input to asynchronous serial interface Input P13 TxD Output Serial data output from asynchronous serial interface Input P14 TWTOFFP Input External input to stop 1-bit inverter control timer output Input P/INTP TWTO- TWTO5 Output 1-bit inverter control timer output Output RTP1-RTP15 TI Input External count clock input to 16-bit timer/event counter Capture trigger input to capture registers (CR, CR1) of 16-bit timer/event counter Input P53/INTP5 TI1 Capture trigger input to capture register (CR) of 16-bit timer/event counter P54/TO TO Output 16-bit timer/event counter output Input P54/TI1 TI5 Input External count clock input to 8-bit timer/event counter 5 Input P5/TO5 TO5 Output 8-bit timer/event counter 5 output Input P5/TI5 RTP1 to RTP15 Output Real-time output port 1 output Output TWTO to TWTO5 ADTRG Input A/D converter trigger input Input P3/INTP3 ANI to ANI3 Input A/D converter analog input Input P2 to P23 AVREF Input A/D converter reference voltage input and positive power supply for port 2 AVSS A/D converter ground potential. Make the same potential as VSS. RESET Input System reset input X1 Input Connecting resonator for X1 input clock oscillation X2 VDD Positive power supply (except for ports) VSS Ground potential (except for ports) FLMD Flash memory programming mode setting FLMD1 Input Input P17 22 User s Manual U1789EJ2VUD

23 CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions P to P3 (port ) P to P3 function as a 4-bit I/O port. These pins also function as external interrupt request input, timer output stop external signal, and A/D converter trigger input. The following operation modes can be specified in 1-bit units. (1) Port mode P to P3 function as a 4-bit I/O port. P to P3 can be set to input or output in 1-bit units using port mode register (PM). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register (PU). (2) Control mode P to P3 function as external interrupt request input, timer output stop external signal, and A/D converter trigger input. (a) INTP to INTP3 These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) TWTOFFP This is an external input pin to stop timer output (TWTO to TWTO5). (c) ADTRG This is an external trigger signal input pin of the A/D converter P13, P14, P16, P17 (port 1) P13, P14, P16, and P17 function as an 4-bit I/O port. These pins also function as pins for serial interface data I/O and flash memory programming mode setting. The following operation modes can be specified in 1-bit units. (1) Port mode P13, P14, P16, and P17 function as an 4-bit I/O port. P13, P14, P16, and P17 can be set to input or output in 1- bit units using port mode register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1). (2) Control mode P13, P14, P16, and P17 function as serial interface data I/O and flash memory programming mode setting. (a) RxD This is the serial data input pin of the asynchronous serial interface. (b) TxD This is the serial data output pin of the asynchronous serial interface. (c) FLMD1 This pin sets the flash memory programming mode. User s Manual U1789EJ2VUD 23

24 CHAPTER 2 PIN FUNCTIONS P2 to P23 (port 2) P2 to P23 function as an 4-bit input-only port. These pins also function as pins for A/D converter analog input. The following operation modes can be specified in 1-bit units. (1) Port mode P2 to P23 function as an 4-bit input-only port Note. <R> Note Connect AVREF to VDD when port 2 is used as a digital port. (2) Control mode P2 to P23 function as A/D converter analog input pins (ANI to ANI3). When using these pins as analog input pins, see (5) ANI/P2 to ANI3/P23 in 13.7 Cautions for A/D Converter P5, P53, P54 (port 5) P5, P53, and P54 function as an 3-bit I/O port. These pins also function as external interrupt request input and timer I/O. The following operation modes can be specified. (1) Port mode P5, P53, and P54 function as an 3-bit I/O port. P5, P53, and P54 can be set to input or output in 1-bit units using port mode register 5 (PM5). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (PU5). (2) Control mode P5, P53, and P54 function as the pins for the external interrupt request input and timer I/O. (a) INTP5 This is the external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) TI5 This is the pin for inputting an external count clock to 8-bit timer/event counter 5. (c) TO5 This is timer output pin from 8-bit timer/event counter 5. (d) TI This is the pin for inputting an external count clock to 16-bit timer/event counters and is also for inputting a capture trigger signal to the capture registers (CR, CR1). (e) TI1 This is the pin for inputting a capture trigger signal to the capture register (CR) of 16-bit timer/event counters. (f) TO This is timer output pin from 16-bit timer/event counter TWTO/RTP1 to TWTO5/RTP15 These are 1-bit inverter control timer output pins. And, these pins function also as real-time output port pins. 24 User s Manual U1789EJ2VUD

25 CHAPTER 2 PIN FUNCTIONS AVREF This is the A/D converter reference voltage input pin. When the A/D converter is not used, connect this pin directly to VDD Note. Note Connect port 2 directly to VDD when it is used as a digital port AVSS This is the A/D converter ground potential pin. Even when the A/D converter is not used, always use this pin with the same potential as the VSS pin RESET This is the active-low system reset input pin X1 and X2 These are the pins for connecting a resonator for the X1 input clock. When supplying an external clock, input a signal to the X1 pin and input the inverse signal to the X2 pin. Remark The X1 and X2 pins of the product with an on-chip debug function (part number pending) can be used to set the on-chip debug mode when the on-chip debug function is used. For details, see CHAPTER 23 ON-CHIP DEBUG FUNCTION VDD The positive power supply pin VSS The ground potential pin FLMD This pin sets the flash memory programming mode. Connect FLMD to a flash memory programmer in the flash memory programming mode, and to VSS in the normal operation mode. User s Manual U1789EJ2VUD 25

26 CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins. See Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-2. Pin I/O Circuit Types Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins P/INTP/TWTOFFP P1/INTP1 P2/INTP2 P3/INTP3/ADTRG P13/RxD P14/TxD P16 P17/FLMD1 8-C 5-H I/O Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. P2/ANI to P23/ANI3 9-C Input Connect to VDD or VSS. P5/TI5/TO5 P53/TI/INTP5 8-C I/O Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. P54/TI1/TO TWTO/RTP1-TWTO5/RTP15 4-B Output Leave open. RESET 2 Input AVREF Connect directly to VDD Note 1. AVSS FLMD Connect directly to VSS. Connect to VSS Note 2. Notes 1. Connect port 2 directly to VDD when it is used as a digital port. 2. FLMD is a pin that is used to write data to the flash memory. To rewrite the data of the flash memory on-board, connect this pin to EVSS or VSS via a resistor (1 kω: recommended). 26 User s Manual U1789EJ2VUD

27 + CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List Type 2 Type 8-C VDD Pullup enable P-ch IN VDD Data P-ch Schmitt-triggered input with hysteresis characteristics IN/OUT Output disable N-ch Type 4-B Type 9-C Data VDD P-ch IN P-ch N-ch Comparator AVSS OUT VREF (threshold voltage) Output disable N-ch Input enable Type 5-H VDD Pullup enable P-ch VDD Data P-ch IN/OUT Output disable N-ch Input enable User s Manual U1789EJ2VUD 27

28 CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space μpd78f711 and 78F712 products can each access a 64 KB memory space. Figures 3-1 and 3-2 show the memory map. Caution Because the initial value of the memory size switching register (IMS) is CFH, set IMS to 2H (μpd78f711) or 4H (μpd78f712) by initialization. Figure 3-1. Memory Map (μpd78f711) FFFFH FFH FEFFH FEEH FEDFH Special function registers (SFR) bits General-purpose registers 32 8 bits Note 1 1FFFH Internal high-speed RAM bits Program area FCH FBFFH 1H FFFH Data memory space Reserved 8H 7FFH CALLF entry area Program area 2H 1FFFH 84H 83H 81H 8H 7FH Note 2 Option bite reservation area (Reserved) Option bite area Flash memory bits CALLT table area 4H 3FH 84H 83H H Note 2 H Vector table area Notes 1. This area occupies 9 bytes (planned) during on-chip debugging because it is used as a backup area for user data during communication. 2. This area cannot be used during on-chip debugging because it is used as a communication command area (256 bytes to 1 KB). 28 User s Manual U1789EJ2VUD

29 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (μpd78f712) FFFFH FFH FEFFH FEEH FEDFH Special function registers (SFR) bits General-purpose registers 32 8 bits Note 1 3FFFH Internal high-speed RAM bits Program area FCH FBFFH 1H FFFH Data memory space Reserved 8H 7FFH CALLF entry area Program area 4H 3FFFH 84H 83H 81H 8H 7FH Note 2 Option bite reservation area (Reserved) Option bite area Flash memory bits CALLT table area 4H 3FH 84H 83H H Note 2 H Vector table area Notes 1. This area occupies 9 bytes (planned) during on-chip debugging because it is used as a backup area for user data during communication. 2. This area cannot be used during on-chip debugging because it is used as a communication command area (256 bytes to 1 KB). User s Manual U1789EJ2VUD 29

30 CHAPTER 3 CPU ARCHITECTURE Internal program memory space The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). μpd78f711 and 78F712 products incorporate internal ROM (flash memory), as shown below. Table 3-1. Internal ROM Capacity Part Number Internal ROM μpd78f711 μpd78f712 Flash memory Structure Capacity bits (H to 1FFFH) bits (H to 3FFFH) The internal program memory space is divided into the following areas. (1) Vector table area The 64-byte area H to 3FH is reserved as a vector table area. The program start addresses for branch upon reset signal input or generation of each interrupt request are stored in the vector table area. Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. Table 3-2. Vector Table Vector Table Address Interrupt Source Vector Table Address Interrupt Source H RESET input, POC, LVI, WDT 2H 22H Note Note 4H INTLVI 24H Note 6H INTP 26H Note 8H INTP1 28H INTTM AH INTP2 2AH INTTM1 CH INTP3 2CH INTSRE EH Note 2EH INTSR 1H INTP5 3H INTST 12H Note 32H INTTM5 14H Note 34H INTTM51 16H INTTWUD 36H Note 18H INTTWCM3 38H Note 1AH INTTWCM4 3AH INTDMU 1CH INTTWCM5 3CH INTAD 1EH Note Note There is no interrupt request corresponding to this vector table address. (2) CALLT instruction table area The 64-byte area 4H to 7FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) Option byte area The 1-byte area 8H is reserved as a option byte area. For details, see CHAPTER 21 OPTION BYTE. 3 User s Manual U1789EJ2VUD

31 CHAPTER 3 CPU ARCHITECTURE (4) CALLF instruction entry area The area 8H to FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF) Internal data memory space μpd78f711 and 78F712 products incorporate the following RAMs. (1) Internal high-speed RAM The internal high-speed RAM is allocated to the area FCH to FEFFH in a bits configuration. The 32-byte area FEEH to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit registers per one bank. This area cannot be used as a program area in which instructions are written and executed. The internal high-speed RAM can also be used as a stack memory Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FFH to FFFFH (see Table 3-3 Special Function Register List in Special function registers (SFRs)). Caution Do not access addresses to which SFRs are not assigned Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the μpd78f711 and 78F712, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of special function registers (SFR) and generalpurpose registers are available for use. Figure 3-3 and 3-4 show correspondence between data memory and addressing. For details of each addressing mode, see 3.4 Operand Address Addressing. User s Manual U1789EJ2VUD 31

32 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Correspondence Between Data Memory and Addressing (μpd78f711) FFFFH FF2H FF1FH Special function registers (SFR) bits SFR addressing FFH FEFFH FEEH FEDFH General-purpose registers 32 8 bits Register addressing Short direct addressing Internal high-speed RAM bits FE2H FE1FH Note 1 FCH FBFFH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved 2H 1FFFH Flash memory bits 84H 83H Note 2 H Notes 1. This area occupies 9 bytes (planned) during on-chip debugging because it is used as a backup area for user data during communication. 2. This area cannot be used during on-chip debugging because it is used as a communication command area (256 bytes to 1 KB). 32 User s Manual U1789EJ2VUD

33 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Correspondence Between Data Memory and Addressing (μpd78f712) FFFFH FF2H FF1FH Special function registers (SFR) bits SFR addressing FFH FEFFH FEEH FEDFH General-purpose registers 32 8 bits Register addressing Short direct addressing Internal high-speed RAM bits FE2H FE1FH Note 1 FCH FBFFH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved 4H 3FFFH Flash memory bits 84H 83H Note 2 H Notes 1. This area occupies 9 bytes (planned) during on-chip debugging because it is used as a backup area for user data during communication. 2. This area cannot be used during on-chip debugging because it is used as a communication command area (256 bytes to 1 KB). User s Manual U1789EJ2VUD 33

34 CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The μpd78f711 and 78F712 products incorporate the following processor registers Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. RESET input sets the reset vector table values at addresses H and 1H to the program counter. Figure 3-5. Format of Program Counter 15 PC PC15 PC14 PC13 PC12 PC11 PC1 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions. RESET input sets the PSW to 2H. Figure 3-6. Format of Program Status Word 7 PSW IE Z RBS1 AC RBS ISP CY (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupts are disabled. When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specification flag. The IE flag is reset () upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset () in all other cases. 34 User s Manual U1789EJ2VUD

35 CHAPTER 3 CPU ARCHITECTURE (c) Register bank select flags (RBS and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored. (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset () in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is, lowlevel vectored interrupt requests specified by a priority specification flag register (PRL, PRH, PR1L, PR1H) (see 19.3 (3) Priority specification flag registers (PRL, PRH, PR1L, PR1H)) cannot be acknowledged. Actual interrupt request acknowledgment is controlled by the interrupt enable flag (IE). (f) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-7. Format of Stack Pointer 15 SP SP15 SP14 SP13 SP12 SP11 SP1 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-8 and 3-9. Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before using the stack. User s Manual U1789EJ2VUD 35

36 CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEEH) SP FEEH FEEH FEDFH Register pair higher SP FEDEH FEDEH Register pair lower (b) CALL, CALLF, CALLT instructions (when SP = FEEH) SP FEEH FEEH FEDFH PC15 to PC8 SP FEDEH FEDEH PC7 to PC (c) Interrupt, BRK instructions (when SP = FEEH) SP FEEH FEEH FEDFH PSW FEDEH PC15 to PC8 SP FEDDH FEDDH PC7 to PC 36 User s Manual U1789EJ2VUD

37 CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) SP FEEH FEEH FEDFH Register pair higher SP FEDEH FEDEH Register pair lower (b) RET instruction (when SP = FEDEH) SP FEEH FEEH FEDFH PC15 to PC8 SP FEDEH FEDEH PC7 to PC (c) RETI, RETB instructions (when SP = FEDDH) SP FEEH FEEH FEDFH PSW FEDEH PC15 to PC8 SP FEDDH FEDDH PC7 to PC User s Manual U1789EJ2VUD 37