Processor Design. System-on-Chip Computing for ASICs and FPGAs. Edited by. Jari Nurmi Tampere University of Technology Finland

Transcription

1 Processor Design

2 Processor Design System-on-Chip Computing for ASICs and FPGAs Edited by Jari Nurmi Tampere University

3 A C.I.P. Catalogue record for this book is available from the Library of Congress. ISBN (HB) ISBN (e-book) Published by Springer, P.O. Box 17, 3300 AA Dordrecht, The Netherlands. Printed on acid-free paper All Rights Reserved 2007 Springer No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work.

4 To Pirjo, Lauri, Eero, and Santeri

5 Preface When I started my computing career by programming a PDP-11 computer as a freshman in the university in early 1980s, I could not have dreamed that one day I d be able to design a processor. At that time, the freshmen were only allowed to use PDP. Next year I was given the permission to use the famous brand-new VAX-780 computer. Also, my new roommate at the dorm had got one of the first personal computers, a Commodore-64 which we started to explore together. Again, I could not have imagined that hundreds of times the processing power will be available in an everyday embedded device just a quarter of century later. Little by little I delved into the design of digital circuits, and computer architecture. I finally learned my lessons in RISC philosophy when I was teaching computer architecture classes in early 1990s according to the famous groundbreaking book by Hennessy and Patterson. At that time, I had already started to design processors, first some simple configurable filters and then straightforward DSP cores. The story continued in a number of different kinds of design projects purely in academia, as academiaindustry cooperation projects and as commercial developments in industry. For me, this decade has meant the time to be back in academia, where I have taught processor-design courses since A characteristic feature to these courses has been the lack of a good course textbook. I have tried out a few books, and used a scattered set of my own material trying bridge the gaps that I perceived. Year after year I got more annoyed with the absence of a textbook, until, after gaining some editor experience in another book project, I decided that the book needed to be written. I would like to thank my contact person at Springer, Mark de Jongh, who believed in me right from the start, and all the contributors of this book. A big part of the success of this project was that I knew some good people and asked for their contribution. I had worked with many of them previously in the annual International Symposium on System-on-Chip since 1999, without realizing what kind of assets they represented. Thanks also to all the people who used their valuable time to review the book chapters. vii

6 viii Preface I hope that you will find this book to be beneficial to you whether you are a student, engineer, teacher or engineering manager. This book definitely fills the gap that I had recognized, so I hope that we shared the same gap. In Tampere, April 2007 Jari Nurmi

7 Table of Contents List of Contributing Authors...xv 1 Introduction Embedded Computer Architecture Fundamentals...7 Components of (an embedded) computer...7 Architecture organization...12 Ways of parallelism...15 Memory...19 I/O operations and peripherals Beyond the Valley of the Lost Processors: Problems, Fallacies, and Pitfalls in Processor Design...27 Designing a high-level computer instruction-set architecture (ISA) to support a specific language or language domain...28 Use of intermediate ISAs to allow a simple machine to emulate its betters...32 Stack machines...35 Extreme CISC and extreme RISC...39 Very long instruction word (VLIW)...43 Overly aggressive pipelining...45 Unbalanced processor design...47 Omitting pipeline interlocks...50 Non-power-of-2 data-word widths for general-purpose computing...53 Too small an address space...55 Memory segmentation...58 Multithreading...60 Symmetric multiprocessing Processor Design Flow...69 Capturing requirements...69 Instruction coding...74 Exploration of architecture organizations...79 ix

8 x Table of Contents Hardware and software development...80 Software tools and libraries General-Purpose Embedded Processor Cores The COFFEE RISC Example...83 Introduction...83 Implications of RISC design philosophy...84 The COFFEE RISC Core instruction set architecture...86 Software view of the COFFEE RISC Core...88 Hardware view of the COFFEE RISC Core...90 The COFFEE RISC Core pipeline structure...92 The COFFEE RISC Core implementation...95 The COFFEE RISC Core characteristics...97 Conclusions The DSP and Its Impact on Technology Introduction Why a DSP is different The evolving architecture of a DSP What is next in the evolution of the DSP Summary VLIW DSP Processor for High-End Mobile Communication Applications Trends in mobile communication DSP-specific requirements Microarchitectural concepts VLIW and SW programmability a, an application specific adaptable core architecture Benchmarking: kernel versus application benchmarking Design space exploration The complexity of configurability Summary Acknowledgment Customizable Processors and Processor Customization Introduction A benefits analysis of processor customization Using microprocessor cores in SOC design Benefiting from microprocessor extensibility How microprocessor use differs between SOC and board-level design...157

9 Table of Contents xi Tensilica s extensible Xtensa processor core The TIE language Conclusion Run-Time Reconfigurable Processors Embedded microprocessor trends Instruction set metamorphosis Reconfigurable computing Run-time reconfigurable instruction set processors Coarse-grained reconfigurable processors Conclusions Coprocessor Approach to Accelerating Multimedia Applications Need for accelerators Accelerators and different types of parallelism Processor architectures and different approaches to acceleration Requirements of applications for hardware coprocessors Numeric coprocessors: floating-point units Various types of reconfigurable accelerators Milk coprocessor and Butter accelerator Conclusions Designing Soft-Core Processors for FPGAs Configurable processors Challenges of FPGA processor design Opportunities of FPGA processor design FPGA architecture overview FPGA design issues Instruction set issues FPGA processor instruction set comparison Case study Nios II Closing comments Acknowledgments Protocol Processor Design Issues Introduction Domain and application analysis for optimized protocol processing hardware Hardware abstraction to handle the complexity of specifications...262

10 xii Table of Contents Custom design frameworks Design processes The TACO framework for protocol processor design Conclusions Java Co-Processor for Embedded Systems Introduction Generic virtual machine architecture Using hardware systems in virtual machine implementations Structure of the co-processor Current status and future work Summary Stream Multicore Processors Introduction Raw architecture overview Related architectures Raw chip implementation Methodology for performance analysis Stream computation ILP computation Bit-level computation Conclusion Acknowledgments Processor Clock Generation and Distribution Introduction Clock parameters and trends Clock distribution networks Deskew circuits Jitter reduction techniques Low power clock distribution Future directions in clock distribution Summary Asynchronous and Self-Timed Processor Design Motivation for asynchronous design The development of asynchronous processors Asynchronous design styles Features of asynchronous design Summary and conclusions...388

11 Table of Contents xiii 17 Early-Estimation Modeling of Processors Introduction History of early estimation models for computer architectures Adapting models to meet modern processor architectures Architecture modeling Processor logic optimization at 90 nm technology Physical design issues in the era of sub-100 nm technologies System Level Simulations Introduction Simulation and languages TACO configurable SystemC simulator High-level instruction set simulator generator for COFFEE Risc Core Conclusion Programming Tools for Reconfigurable Processors Algorithm development on reconfigurable processors (programming issues) Instruction set extension implementation on a standard compilation tool-chain Bridging the gap from hardware to software through C-described data flow graphs Overview of programming tools for reconfigurable processors An example of algorithm development environment for reconfigurable processors: the Griffy-C approach Software-Based Self-Testing of Embedded Processors Evolution of software-based self-test High-level SBST methodology Case studies experimental results Conclusions and perspective Future Directions in Processor Design References Index...515

12 List of Contributing Authors Anant Agarwal Tapani Ahonen Tampere University Institute of Digital and Computer Systems P.O. Box 553 FI Tampere Saman Amarasinghe James Ball Altera, Inc. 110 Cooper St., Suite 201 Santa Cruz, CA Ian Bratt Claudio Brunelli Tampere University Institute of Digital and Computer Systems P.O. Box 553 FI Tampere Fabio Campi STMicroelectronics FTM/CCDS/Configurable Logics Viale C. Pepoli 3/ Bologna Italy Matt Frank xv

13 xvi List of Contributing Authors Gene Frantz Texas Instruments, Inc Southwest Freeway, MS 701 Stafford, TX Steve Furber School of Computer Science The University of Manchester Oxford Road Manchester M13 9PL United Kingdom Jim Garside School of Computer Science The University of Manchester Oxford Road Manchester M13 9PL United Kingdom Dimitris Gizopoulos University of Piraeus Department of Informatics 80 Karaoli & Dimitriou Street Piraeus Greece Ben Greenwald Henry Hoffmann Jouni Isoaho University of Turku Technology FI Turku Paul Johnson Jason Kim Nektarios Kranitis National and Kapodistrian University of Athens Department of Informatics and Telecommunications Panepistimiopolis, Ilissia 15784, Athens Greece

14 List of Contributing Authors xvii Juha P. Kylliäinen Tampere University Institute of Digital and Computer Systems P.O. Box 553 FI Tampere Walter Lee Steve Leibson Tensilica, Inc Scott Blvd. Santa Clara, CA Johan Lilius Åbo Akademi University Technologies Joukahaisenkatu 3-5 FI Turku Grant Martin Tensilica, Inc Scott Blvd. Santa Clara, CA Jason Eric Miller Claudio Mucci ARCES, University of Bologna Viale C. Pepoli 3/ Bologna Italy Sanna Määttä Tampere University Institute of Digital and Computer Systems P.O. Box 553 FI Tampere Jari Nurmi Tampere University Institute of Digital and Computer Systems P.O. Box 553 FI Tampere Tero Nurmi University of Turku Technology FI Turku

15 xviii List of Contributing Authors Christian Panis Catena Radio Design, B.V. Science Park Eindhoven Ekkersrijt EG Son en Breugel The Netherlands Antonis Paschalis National and Kapodistrian University of Athens Department of Informatics and Telecommunications Panepistimiopolis, Ilissia 15784, Athens Greece Juha Plosila University of Turku Technology FI Turku James Psota Rodric Rabbah Stefan Rusu Intel Corporation 2200 Mission College Blvd., M/S SC Santa Clara, CA Arvind Saraf Nathan Shnidman Volker Strumpen Tero Säntti University of Turku Technology FI Turku

16 List of Contributing Authors xix Michael Bedford Taylor Dragos Truscan Åbo Akademi University Technologies Joukahaisenkatu 3-5 FI Turku Joonas Tyystjärvi University of Turku Technology FI Turku David Wentzlaff Tomi Westerlund University of Turku Technology FI Turku George Xenoulis University of Piraeus Department of Informatics 80 Karaoli & Dimitriou Street Piraeus Greece Seppo Virtanen University of Turku Technology FI Turku