SPECC: SPECIFICATION LANGUAGE AND METHODOLOGY

Transcription

1 SPECC: SPECIFICATION LANGUAGE AND METHODOLOGY

2 SPECC: SPECIFICATION LANGUAGE AND METHODOLOGY Daniel D. Gajski Jianwen Zhu Rainer Dömer Andreas Gerstlauer Shuqing Zhao University of California, Irvine SPRINGER SCIENCE+BUSINESS MEDIA, LLC

3 Library of Congress Cataloging-in-Publication Data A C.I.P. Catalogue record for this book is available from the Library of Congress. ISBN ISBN (ebook) DOI / Copyright 2000 Springer Science+Business Media New York Originally published by Kluwer Academic Publishers New York in 2000 Softcover reprint of the hardcover 1st edition 2000 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photo-copying, recording, or otherwise, without the prior written permission of the publisher, Springer Science+Business Media, LLC. Printed on acid-free paper.

4 Contents List of Figures List of Tables Preface Acknowledgments ix xiii xv XVll 1. INTRODUCTION System Level Design Challenge Platform Approach IP Assembly Synthesis from Specifications System Level Design Language Related Work University projects Commercial systems Open Consortia SpecC Goals Summary ESSENTIAL ISSUES IN SYSTEM LEVEL DESIGN Models Finite-state machines Dataflow graph Finite-state machine with datapath Programming languages Superstate FSMD Hierarchical concurrent finite-state machines Program-state machines Architectures Controller architecture Datapath architecture Processor architecture CISC architecture RISC architecture 31

5 vi SPECC: SPECIFICATION LANGUAGE AND METHODOLOGY VLIW architecture SOC architecture Languages Concurrency State transitions Hierarchy Programming constructs Behavioral completion Exception handling Timing Communication Process synchronization Methodology IP Requirements Synthesis Flow Analysis and Validation Flow Backend Summary THESPECCLANGUAGE Design Considerations for System Level Design Language Traditional Languages The SpecC language Structural Hierarchy Behavioral Hierarchy Synchronization Exception Handling Timing Additional features Reuse and IP Reference Implementation Summary THE SPECC METHODOLOGY Overview Specification Specification Model Architecture exploration Communication Synthesis Backend Summary SYSTEM LEVEL DESIGN WITH SPECC GSM Enhanced Full Rate Vocoder Human Vocal Tract Speech Synthesis Model Speech Encoding and Decoding Specification 108

6 Contents VB General Vocoder Specification 5.3 Architecture Exploration Exploration Flow Analysis and Estimation Architecture Allocation Partitioning Scheduling Results 5.4 Communication Synthesis Protocol Insertion Transducer Synthesis Protocol Inlining Vocoder Communication Synthesis Results 5.5 Backend Software Synthesis Custom Hardware Synthesis 5.6 Summary 6. CONCLUSIONS Appendices A- The SpecC Language Reference Manual Al Syntax and Semantics Al.l Boolean Type Al.2 Bitvector Type Al.3 Event Type Al.4 Time Type Al.5 Behavior Class Al.6 Channel Class Al.7 Interface Class Al.8 Ports Al.9 Class Instantiation Al.10 Sequential Execution Al.ll Parallel Execution Al.12 Pipelined Execution Al.13 Finite State Machine Execution Al.14 Exception Handling Al.15 Synchronization Al.16 Timing Specification Al.17 Binary Import Al.18 Persistent Annotation A2 Summary B- Vocoder Description B.l C Reference Implementation Block Diagrams B.l.l Coder B.l.2 Decoder

7 viii SPECC: SPECIFICATION LANGUAGE AND METHODOLOGY B.2 Vocoder Specification 211 B.2.! General (shared) behaviors 211 B.2.2 Coder 211 B.2.3 Decoder 224 B.3 Specification Model 231 B.3.l Testbench 231 B.3.2 Coder 232 B.3.3 Preprocessing 239 B.3.4 Linear Prediction Analysis 240 B.3.5 Open-Loop Pitch Analysis 245 B.3.6 Closed-Loop Pitch Analysis 248 B.3.7 Algebraic (fixed) codebook search 254 B.3.8 Filter memory updates 259 B.3.9 Postprocessing 261 B.4 Architecture Model 262 B.4.1 Coder 262 BA.2 Bus 263 B.4.3 DSP 266 B.4.4 HW 275 B.S Communication Model 276 B.5.1 Coder 277 B.5.2 Bus 277 B.5.3 DSP 279 B.5A HW 282 B.6 Implementation Model 285 B.6.1 RTL behavioral code 285 B.6.2 RTL structural code (control only) 287 Index 311

8 List of Figures 1.1 Platform architecture IP assembly Synthesis FSM model for the elevator controller Example of a dataflow graph FSMD model for the elevator controller Statecharts: hierarchical concurrent states An example of a program-state machine A generic controller design Two different datapaths for FIR filter An example of a custom datapath Design model clse with microprogrammed control RISe with hardwired control An example of VLIW datapath A heterogeneous multiprocessor Pipelined concurrency Structural hierarchy Sequential behavioral decomposition Behavioral decomposition types Exception types Timing diagram Communication model Examples of communication Control synchronization with a fork-join Control synchronization by initialization in Statecharts Data-dependent synchronization in Statecharts A generic codesign methodology Channel inlining. 50

9 x SPECC: SPECIFICATION LANGUAGE AND METHODOLOGY 3.1 Language Comparison Basic structure of a SpecC model Basic structure of SpecC code Behavioral hierarchy Example for simple shared memory channel Exception handling Timing Example: SRAM Read Protocol The SpecC Environment (SCE) The SpecC methodology Specification model of design example SpecC code for specification model of design example Synchronization of shared variable accesses in the specification model SpecC code for the synchronization channel Intermediate model after behavior partitioning Intermediate model after scheduling Model after behavior partitioning Example model after variable partitioning to a dedicated memory Example model after variable partitioning to local memories Model of design example after channel partitioning SpecC code for architecture model of design example Synchronization inside leaf behaviors of the architecture model SpecC code for message-passing channel Model of design example after protocol insertion Model with IPs after protocol and transducer insertion Model after protocol inlining Model with IPs after protocol inlining SpecC code for communication model of design example Speech synthesis model Vocoder top level specification Coder part of the vocoder specification Encoding part of the coder specification Decoder part of the vocoder specification Timing constraints Architecture exploration flow Sample operation profile Profile of computational complexity of coder parts Profile of computational complexity of decoder parts Estimated coder delays Estimated decoder delays. 124

10 List of Figures xi 5.13 Execution sequence of coder subbehaviors in one frame Execution sequence of decoder subbehaviors in one frame Component matching Vocoder architecture Criticality of vocoder behaviors Final vocoder partitioning Channel partitioning Sample encoder partition after scheduling Final dynamic scheduling of vocoder tasks Breakdown of coder delays after exploration Breakdown of decoder delays after exploration Architecture model General model after protocol insertion Sample model after transducer synthesis General communication model after inlining Vocoder model after protocol insertion DSP56600 bus protocol Vocoder communication model after inlining Hardware coprocessor SFSMD model after in1ining Hardware communication SFSMDs Vocoder hardware/software interfacing model Original C source code example Assembly output of original compiler Assembly code after manual optimizations HLS design flow The scheduled codebook search Superstate FSMD model Data-flow view of codebook search behavioral model A generic controller/datapath implementation Operation profile for one sub-frame RTL behavior for prefilter Datapath diagram Critical path candidates Execution time distribution. 171 B.1 Coder. 212 B.2 LP Analysis. 213 B.3 Open-loop pitch analysis. 215 B.4 Closed loop pitch search. 216 B.5 Algebraic (fixed) codebook search. 219 B.6 Filter memory update. 222 B.7 Coder block diagram. 223 B.8 Decoder. 224

11 xii SPECC: SPECIFICATION language AND METHODOLOGY B.9 B.lO B.11 B.12 LSP decoding. Subframe decoding. Post filtering. Decoder block diagram

12 List of Tables 1.1 System-level Design Projects in Academia Specification model guidelines Refinement rules for behavior partitioning Refinement rules for scheduling Refinement rules for variable partitioning Refinement rules for channel partitioning Architecture model guidelines Refinement rules for protocol insertion Refinement rules for transducer synthesis Refinement rules for inlining Communication model guidelines Implementation model guidelines Delays after architecture exploration Vocoder interrupt and address assignment Vocoder Interrupt priorities Worst-case delays for vocoder in back-to-back operation Functional Unit Selection Result Memory Addresses Unit delays. 170

13 Preface The research on system-level design and methodologies began many years ago. In 1989, we were looking for a language which would be suitable for specifying systems, and Statecharts seemed to be one of the best candidates. However, Statecharts were not intended for softwarelhardware codesign. In order to accommodate codesign, we introduced the concept of a superstate, which can execute programming language code of any length. We also incorporated several other features into our specification language, which we called SpecCharts in honor of Harel's Statecharts, which we had used as a starting point. SpecCharts were a VHDL frontend intended for the design of ASICs. Subsequently, we developed other tools for partitioning and synthesis, and encapsulated them into the SpecSyn environment, which was distributed to over 60 companies. During evaluation and experimentation with SpecSyn we have noticed two interesting trends: (a) All examples contributed by industry were written in the C programming language. (b) Many companies wanted to evolve, modify, or include legacy designs into the new system/product. These observations led us to the inclusion of new features in the language: (a) For legacy designs, we introduced structure in addition to behavior in the specification. (b) For intellectual property (IP), we separated communication from computation, and encapsulated them into behaviors and channels. Similarly, IPs were encapsulated into wrappers to enable easy ''plug-and-play'' of different IPs for developers.

14 XVI SPECC: SPECIFICATION LANGUAGE AND METHODOLOGY (c) We introduced concepts of discrete event timing in order to describe timing diagrams for protocols. Furthermore, we decided to formulate the specification language as a frontend for C. These new additions lead to SpecC, and an elegant and easy to learn IP-centric methodology for system design. In this book, we present our findings, introduce the SpecC language and provide a language reference manual, describe the SpecC methodology, and demonstrate the methodology with the example of a voice coder design. We hope that our book can be used in industrial settings for the study of design flow and methodology, and in academic settings for the education of students in system specification, modeling, and design. We welcome any comments, observations, and discussion of the topics presented in this book from our readers, who can reach us via electronic mail. Irvine, California January 2000 D. D. GAJSKI, J. ZHU, R. DOMER, A. GERSTLAUER, S. ZHAO

15 Acknowledgments The authors would like to acknowledge several individuals and organizations who helped us in concepts and experiments leading to this book. First, we would like to acknowledge contributions of Frank Vahid, Sanjiv Narayan and Jie Gong, the coauthors of the first book on Specification and Design of Embedded Systems [GVNG94]. They contributed early to some main concepts presented in this book. We would also like to acknowledge students in the Friday seminars on Design Science at UCI who participated in discussions of some concepts and ideas exposed in this book. Also, we would like to thank the organizations that sponsored this work since 1989, including NSF, Semiconductor Research Corporation, Rockwell, Toshiba, Hitachi, Matsushita, Conexant and Motorola. We would like to thank in particular Tadatoshi Ishii and Dai Araki from Toshiba for helping us focus on real industrial needs and contributing reality to the SpecC methodology. We would also like to thank Arkady Horak from Motorola for his help in the vocoder project. Also, we would like to thank Lukai Cai, Hongxing Li, Junyu Peng, Martin von Weymarn, Vincent Chang from UCI and Justin Denison, Mike Olivarez from Motorola for help in the vocoder design and in the synthesis of the codebook search part, presented in Chapter 5.