Multi processor systems with configurable hardware acceleration
|
|
|
- Ferdinand Greer
- 5 years ago
- Views:
Transcription
1 Multi processor systems with configurable hardware acceleration Ph.D in Electronics, Computer Science and Telecommunications Ph.D Student: Davide Rossi Ph.D Tutor: Prof. Roberto Guerrieri
2 Outline Motivations Electronics systems requirements and issues The Morpheus Platform Heterogeneous multi-core Reconfigurable platform The Manyac Platform Homogeneous and regular multi-core platform Configurable and reconfigurable acceleration Results Programming productivity Performance (area, power) Impact on manufacturing costs
3 Motivations (1) New generation embedded applications are pushing signal processing systems to improve: Performance Energy efficiency *source ITRS Flexibility Programmability Time to market *source ITRS
4 Motivations (2) Increase of products development costs (NRE): Design costs Front-end Implementation Verification Testing Software development *source PHILIPS Mask costs Significant impact on small volume products *source SEMATECH 4
5 Morpheus: Main Goals Programming legacy through: ARM Processor acting as system supervisor Flexibility and performance gain through three heterogeneous reconfigurable processing cores: Fine grain fabric (Abound Logic Flexeos efpga) Medium grain fabric (STMicroelectronics DREAM) Coarse grain fabric (PACT XPP-III) Programming productivity through: High level programming approaches for reconfigurable engines 5
6 Morpheus: Architecture Bridge Conf Mem Main Mem External Memory Controller PCM ARM9 AMBA (main bus) DNA NOC NoC DREAM AMBA (configuration bus) efpga XPP ARM core Standard peripheral set 3 communication domains Synchronization and control: Main bus (AHB) Data transfers: 8-nodes 64- bit NoC (STNoC) Configuration: Configuration bus (AHB) Hardware services: Predictable Configuration Manager (PCM) Direct Network Accesses (DNA) 4 Domains Dynamic Frequency Scaling
7 Morpheus: Reconfigurable engines Encapsulated into three independent clock islands Local buffers act as domain crossing mechanism (DPDC memories) PACT XPP Coarse grain device (16-bit) Streaming applications with regular computation patterns Programming: NML (Natural Mapping Language) DREAM Medium grain computation intensive device (4-bit) Iterative applications with complex addressing patterns Programming: Griffy-C efpga Fine grain device (1-bit LUT) Applications handling bit-manipulations, configurable I/O Programming: VHDL 7
8 Morpheus: Chip description and Measurements e F P G A C. M E M M. M E M PCM ARM DREAM PACT XPP Technology: CMOS090GP Supply voltage: 1V Transistor count: 97 M Chip area: 110 mm 2 Static power: 235 mw Max frequency 250 MHz Peak power: 3W ARM DOMAIN Max Freq@1V: 250 MHz Dynamic power: 2.4 mw/mhz XPP subsystem: Max Freq@1V: 150 MHz Dynamic power: 7,5 mw/mhz DREAM subsystem: Max Freq@1V: 200 MHz Dynamic power: 2,1 mw/mhz efpga subsystem: Max Freq@1V: 100 MHz Dynamic power: 0,8 mw/mhz
9 Manyac: Main Goals Flexibility and Programmability through: Multi-processor approach Performance gain trough: Application specific hardware accelerators Programming/design productivity through: High level programming approach based on OpenCL Automatic synthesis of accelerators from high-level language (Griffy-C) Reduction of costs through: Platform-based design approach Regular replication of identical tiles Regular silicon structures for implementation of accelerators 9
10 Manyac: Architecture Regular replication of identical computational tiles + one IO tile Communication: ring topology NoC (STNoC) 3 Hierarchy levels memory infrastructure: Private memory Local memory Global memory Hardware synchronization Hardware accelerators Regular gate arrays The architectural parameters are configurable at design time 10
11 Manyac: Configurable Hardware Accelerators(ST Microelectronics) Pipelined datapaths targeting three kinds of configurable gate array: Run-time programmable gate array Routing and functionalities are programmed through SRAMs Post-fabrication programmability Via-programmable gate array Routing and functionalities are programmed through one via layer Customization: 1 metal layer Metal-programmable gate array Functionalities are mapped on a library of metal programmable cells Customization: 9 metal layers customizations through VIAs customizations through metals 11
12 Manyac: Programming Model Based on OpenCL Sequential code executes on a host processor Parallel and hardware accelerated code executes on the parallel device Two programming models Data parallel (Homogeneous) Task parallel (Heterogeneous) Hardware accelerated functions are encapsulated within parallel kernels and tasks 12
13 Manyac: Design environment OpenCL compiler Allocates function and variables according to OpenCL qualifiers Generates host and device code TLM simulation platform High level exploration of architectural parameters RTL platform Cycle-accurate simulation platform Entry point for physical implementation Griffy environment Accelerators design, simulation models and implementation 13
14 Manyac: Implementation Technology: CMOS40LP, 1.1V Configuration Technology: Metal programmable CT Area: Post Layout: 0,8 mm 2 Metal Programmable area (targeting motion detection application): Post Layout: 0,2 mm 2 4 Tiles Cluster Area: Post Synthesis: ~5 mm 2 Max frequency (post layout): 250 MHz (wc, 125 C, 1.0V) Power consumption : 45 mw@250mhz (nc, 25 C, 1.1V) Computational tile area breakdown by logic entity Computational tile layout 14
15 Results: analysis of programming productivity Objective: evaluate programming productivity improvement due to high level approaches Efforts are estimated according with programming language tables based (*SPR) on the Function Point Analysis (FPA) extended to VHDL language Griffy-C and NML treated as ASM Programming effort required to implement signal processing application on different computational platforms Reduction of design effort with respect to VHDL: 1,3x 2x Language Average Source Statements per FP Productivity Average per Staff Month C FP ASM FP VHDL FP 15
16 Results: Morpheus performance Application fields selected for characterization: Image processing (Edge detection, Binarization, Rgb2YUV) Video processing ( Motion Estimation, Motion Compensation) Telecommunications (CRC, AES, Ethernet) Performance (measured): 1,6 15 GOPS Energy efficiency (measured): 2,7 52,9 GOPS/W Reduction of dynamic power due to frequency scaling: 1.5x 5.5x PERFORMANCE (GOPS) ENERGY EFFICIENCY (GOPS/W) 16
17 Results: Manyac performance by configuration technology Technology node: CMOS65LP 8 cores platform All figures are estimated Std-cell based accelerators: Performance: 5,5 25 GOPS Energy efficiency: GOPS/W Area efficiency: 0,6 3 GOPS/mm 2 Metal programmable accelerators overhead is negligible Via programmable accelerators Performance overhead: 1,25x Energy efficiency: 2,9x Area efficiency: 4,7x Run-time programmable accelerators Performance overheads: 1,25x Energy efficiency: 3,7x Area efficiency: 10x 17
18 Results: Manyac manufacturing costs by configuration technology Assumptions: Technology node: CMOS65LP 5 customizations (or re-spins) of the same platform Run-time programmable and via programmable technologies are convenient only for very low market volumes Run-time programmable: <5K pieces Via programmable: 5K 12K pieces) Metal programmable technology is convenient for larger market volumes Perspectives: As technology nodes scale reconfigurable technologies are becoming even more convenient MANUFACTURING COST PER CONFIGURATION TECHNOLOGY TECHNOLOGY NODES TRENDS 18
19 Conclusion Two multi-core platforms with configurable/ reconfigurable acceleration have been presented: The Morpheus platform (heterogeneous, reconfigurable) The Manyac platform (homogeneous, configurable) Improvement of design/programming productivity due to high level approaches: 1,3x 2x Multi-processor systems with accelerators implemented on reconfigurable and structured ASIC technologies are able to provide high performance, still showing some overhead in terms of power and area with respect to traditional standardcell based approach. The proposed approaches provide an effective way to reduce manufacture costs, especially for low volume products. 19
20 Collaborations The PhD is in collaboration with STMicroelectronics Collaborations within 2 European projects: MORPHEUS (FP6) MODERN (ENIAC)
21 Publications Book chapters: N. Voros et al. Dynamic System Reconfiguration in Heterogeneous Platforms, Chapter 5: The DREAM digital Signal Processor, Chapter 8: The MORPHEUS Data Communication and Storage Infrastructure, Springer, Conference Papers: D. Rossi et al. A Heterogeneous Digital Signal Processor Implementation for Dynamically Reconfigurable Computing, CICC (Custom Integrated Circuit Conference), D. Rossi et al. A Multi-Core Signal Processor for Heterogeneous Reconfigurable Computing, International Symposium on System-on-Chip, Proceedings, F. Campi et al. RTL-to-Layout Implementation of an Embedded Coarse Grained Architecture for Dynamically Reconfigurable Computing in Systems-on-Chip, Proceedings, Journal Papers: D. Rossi et al., A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing, JSSC IEEE Journal of Solid-State Circuits, D. Rossi, C. Mucci, F. Campi, S. Spolzino, L. Vanzolini, H. Sahlbach, S. Whitty, R. Ernst, W. Putzke-Röming, and R. Guerrieri, Application Space Exploration of a Heterogeneous Run Time Configurable Digital Signal Processor, IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2012.
22 Thanks for your attention
Design methodology for multi processor systems design on regular platforms
Design methodology for multi processor systems design on regular platforms Ph.D in Electronics, Computer Science and Telecommunications Ph.D Student: Davide Rossi Ph.D Tutor: Prof. Roberto Guerrieri Outline
A heterogeneous reconfigurable System-on-Chip: MORPHEUS
A heterogeneous reconfigurable System-on-Chip: MORPHEUS Florian Thoma 1, Matthias Kühnle 1, Arnaud Grasset 2, Paul Brelet 2, Philippe Millet 2, Philippe Bonnot 2, Fabio Campi 3, Nikolaos S. Voros 4, Wolfram
FPGA based Design of Low Power Reconfigurable Router for Network on Chip (NoC)
FPGA based Design of Low Power Reconfigurable Router for Network on Chip (NoC) D.Udhayasheela, pg student [Communication system],dept.ofece,,as-salam engineering and technology, N.MageshwariAssistant Professor
Modeling and Simulation of System-on. Platorms. Politecnico di Milano. Donatella Sciuto. Piazza Leonardo da Vinci 32, 20131, Milano
Modeling and Simulation of System-on on-chip Platorms Donatella Sciuto 10/01/2007 Politecnico di Milano Dipartimento di Elettronica e Informazione Piazza Leonardo da Vinci 32, 20131, Milano Key SoC Market
ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
1 ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology Mikkel B. Stensgaard and Jens Sparsø Technical University of Denmark Technical University of Denmark Outline 2 Motivation ReNoC Basic
Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles
Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles Zhiyi Yu, Bevan Baas VLSI Computation Lab, ECE Department University of California, Davis, USA Outline Introduction Timing issues
COE 561 Digital System Design & Synthesis Introduction
1 COE 561 Digital System Design & Synthesis Introduction Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Outline Course Topics Microelectronics Design
A 167-processor 65 nm Computational Platform with Per-Processor Dynamic Supply Voltage and Dynamic Clock Frequency Scaling
A 167-processor 65 nm Computational Platform with Per-Processor Dynamic Supply Voltage and Dynamic Clock Frequency Scaling Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Toney Jacobson, Gouri Landge,
Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays
Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays Éricles Sousa 1, Frank Hannig 1, Jürgen Teich 1, Qingqing Chen 2, and Ulf Schlichtmann
Abstract A SCALABLE, PARALLEL, AND RECONFIGURABLE DATAPATH ARCHITECTURE
A SCALABLE, PARALLEL, AND RECONFIGURABLE DATAPATH ARCHITECTURE Reiner W. Hartenstein, Rainer Kress, Helmut Reinig University of Kaiserslautern Erwin-Schrödinger-Straße, D-67663 Kaiserslautern, Germany
Dependable VLSI Platform using Robust Fabrics
Dependable VLSI Platform using Robust Fabrics Director H. Onodera, Kyoto Univ. Principal Researchers T. Onoye, Y. Mitsuyama, K. Kobayashi, H. Shimada, H. Kanbara, K. Wakabayasi Background: Overall Design
Introduction to reconfigurable systems
Introduction to reconfigurable systems Reconfigurable system (RS)= any system whose sub-system configurations can be changed or modified after fabrication Reconfigurable computing (RC) is commonly used
System On Chip: Design & Modelling (SOC/DAM)
System On Chip: Design & Modelling (SOC/DAM) Exercises Here is the second set of exercises. These are intended to cover subject groups 5-8 of the SOC/DAM syllabus (ABD, SFT, RD, E). These questions are
A Reconfigurable Crossbar Switch with Adaptive Bandwidth Control for Networks-on
A Reconfigurable Crossbar Switch with Adaptive Bandwidth Control for Networks-on on-chip Donghyun Kim, Kangmin Lee, Se-joong Lee and Hoi-Jun Yoo Semiconductor System Laboratory, Dept. of EECS, Korea Advanced
Session: Configurable Systems. Tailored SoC building using reconfigurable IP blocks
IP 08 Session: Configurable Systems Tailored SoC building using reconfigurable IP blocks Lodewijk T. Smit, Gerard K. Rauwerda, Jochem H. Rutgers, Maciej Portalski and Reinier Kuipers Recore Systems www.recoresystems.com
Design Methodologies
Design Methodologies 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2003 2005 2007 2009 Complexity Productivity (K) Trans./Staff - Mo. Productivity Trends Logic Transistor per Chip (M) 10,000 0.1
Hardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University
Hardware Design Environments Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University Outline Welcome to COE 405 Digital System Design Design Domains and Levels of Abstractions Synthesis
A 167-processor Computational Array for Highly-Efficient DSP and Embedded Application Processing
A 167-processor Computational Array for Highly-Efficient DSP and Embedded Application Processing Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Toney Jacobson, Gouri Landge, Michael Meeuwsen, Christine
ISSCC 2001 / SESSION 9 / INTEGRATED MULTIMEDIA PROCESSORS / 9.2
ISSCC 2001 / SESSION 9 / INTEGRATED MULTIMEDIA PROCESSORS / 9.2 9.2 A 80/20MHz 160mW Multimedia Processor integrated with Embedded DRAM MPEG-4 Accelerator and 3D Rendering Engine for Mobile Applications
Network on Chip Architecture: An Overview
Network on Chip Architecture: An Overview Md Shahriar Shamim & Naseef Mansoor 12/5/2014 1 Overview Introduction Multi core chip Challenges Network on Chip Architecture Regular Topology Irregular Topology
Hardware/Software Co-design
Hardware/Software Co-design Zebo Peng, Department of Computer and Information Science (IDA) Linköping University Course page: http://www.ida.liu.se/~petel/codesign/ 1 of 52 Lecture 1/2: Outline : an Introduction
INTRODUCTION TO FPGA ARCHITECTURE
3/3/25 INTRODUCTION TO FPGA ARCHITECTURE DIGITAL LOGIC DESIGN (BASIC TECHNIQUES) a b a y 2input Black Box y b Functional Schematic a b y a b y a b y 2 Truth Table (AND) Truth Table (OR) Truth Table (XOR)
Hardware-Software Codesign. 1. Introduction
Hardware-Software Codesign 1. Introduction Lothar Thiele 1-1 Contents What is an Embedded System? Levels of Abstraction in Electronic System Design Typical Design Flow of Hardware-Software Systems 1-2
The Use Of Virtual Platforms In MP-SoC Design. Eshel Haritan, VP Engineering CoWare Inc. MPSoC 2006
The Use Of Virtual Platforms In MP-SoC Design Eshel Haritan, VP Engineering CoWare Inc. MPSoC 2006 1 MPSoC Is MP SoC design happening? Why? Consumer Electronics Complexity Cost of ASIC Increased SW Content
Reconfigurable Computing. Introduction
Reconfigurable Computing Tony Givargis and Nikil Dutt Introduction! Reconfigurable computing, a new paradigm for system design Post fabrication software personalization for hardware computation Traditionally
An Evaluation of an Energy Efficient Many-Core SoC with Parallelized Face Detection
An Evaluation of an Energy Efficient Many-Core SoC with Parallelized Face Detection Hiroyuki Usui, Jun Tanabe, Toru Sano, Hui Xu, and Takashi Miyamori Toshiba Corporation, Kawasaki, Japan Copyright 2013,
Design and Test Solutions for Networks-on-Chip. Jin-Ho Ahn Hoseo University
Design and Test Solutions for Networks-on-Chip Jin-Ho Ahn Hoseo University Topics Introduction NoC Basics NoC-elated esearch Topics NoC Design Procedure Case Studies of eal Applications NoC-Based SoC Testing
DNNBuilder: an Automated Tool for Building High-Performance DNN Hardware Accelerators for FPGAs
IBM Research AI Systems Day DNNBuilder: an Automated Tool for Building High-Performance DNN Hardware Accelerators for FPGAs Xiaofan Zhang 1, Junsong Wang 2, Chao Zhu 2, Yonghua Lin 2, Jinjun Xiong 3, Wen-mei
Bus AMBA. Advanced Microcontroller Bus Architecture (AMBA)
Bus AMBA Advanced Microcontroller Bus Architecture (AMBA) Rene.beuchat@epfl.ch Rene.beuchat@hesge.ch Réf: AMBA Specification (Rev 2.0) www.arm.com ARM IHI 0011A 1 What to see AMBA system architecture Derivatives
Soft-error and Variability Resilience in Dependable VLSI Platform. Hidetoshi Onodera Kyoto University
Soft-error and Variability Resilience in Dependable VLSI Platform Hidetoshi Onodera Kyoto University Outline: Soft-error and Variability Resilience 1 Background Overview: Dependable VLSI Platform Circuit-level
Fast Flexible FPGA-Tuned Networks-on-Chip
This work was funded by NSF. We thank Xilinx for their FPGA and tool donations. We thank Bluespec for their tool donations. Fast Flexible FPGA-Tuned Networks-on-Chip Michael K. Papamichael, James C. Hoe
ASYNC Rik van de Wiel COO Handshake Solutions
ASYNC 2006 Rik van de Wiel COO Handshake Solutions Outline Introduction to Handshake Solutions Applications Design Tools ARM996HS Academic Program Handshake Solutions Started as research project in Philips
On-Chip Communications
On-Chip Communications Somayyeh Koohi Department of Computer Engineering Sharif University of Technology 1 Introduction Adapted with modifications from lecture notes prepared by S.Pasricha and N.Dutt Outline
IMPROVES. Initial Investment is Low Compared to SoC Performance and Cost Benefits
NOC INTERCONNECT IMPROVES SOC ECONO CONOMICS Initial Investment is Low Compared to SoC Performance and Cost Benefits A s systems on chip (SoCs) have interconnect, along with its configuration, verification,
System-on-Chip Architecture for Mobile Applications. Sabyasachi Dey
System-on-Chip Architecture for Mobile Applications Sabyasachi Dey Email: sabyasachi.dey@gmail.com Agenda What is Mobile Application Platform Challenges Key Architecture Focus Areas Conclusion Mobile Revolution
An Overview of Standard Cell Based Digital VLSI Design
An Overview of Standard Cell Based Digital VLSI Design With examples taken from the implementation of the 36-core AsAP1 chip and the 1000-core KiloCore chip Zhiyi Yu, Tinoosh Mohsenin, Aaron Stillmaker,
Exploring Logic Block Granularity for Regular Fabrics
1530-1591/04 $20.00 (c) 2004 IEEE Exploring Logic Block Granularity for Regular Fabrics A. Koorapaty, V. Kheterpal, P. Gopalakrishnan, M. Fu, L. Pileggi {aneeshk, vkheterp, pgopalak, mfu, pileggi}@ece.cmu.edu
Embedded Programmable Logic Core Enhancements for System Bus Interfaces
Embedded Programmable Logic Core Enhancements for System Bus Interfaces Bradley R. Quinton, Steven J.E. Wilton Dept. of Electrical and Computer Engineering University of British Columbia {bradq,stevew}@ece.ubc.ca
HRL: Efficient and Flexible Reconfigurable Logic for Near-Data Processing
HRL: Efficient and Flexible Reconfigurable Logic for Near-Data Processing Mingyu Gao and Christos Kozyrakis Stanford University http://mast.stanford.edu HPCA March 14, 2016 PIM is Coming Back End of Dennard
Run-Time Reconfigurable Processors. Contents crafted by Dr. Fabio Campi STMicroelectronics
Run-Time Reconfigurable Processors Contents crafted by Dr. Fabio Campi STMicroelectronics AIM of the Presentation Explore Tradeoffs/Issues/solutions in the field of Embedded Reconfigurable Processors Survey
Near-Threshold Computing: Reclaiming Moore s Law
1 Near-Threshold Computing: Reclaiming Moore s Law Dr. Ronald G. Dreslinski Research Fellow Ann Arbor 1 1 Motivation 1000000 Transistors (100,000's) 100000 10000 Power (W) Performance (GOPS) Efficiency (GOPS/W)
HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips
on introducing a new design paradigm HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips D. Diamantopoulos, K. Siozios, E. Sotiriou-Xanthopoulos, G. Economakos and D. Soudris
TIMA Lab. Research Reports
ISSN 1292-862 TIMA Lab. Research Reports TIMA Laboratory, 46 avenue Félix Viallet, 38000 Grenoble France Session 1.2 - Hop Topics for SoC Design Asynchronous System Design Prof. Marc RENAUDIN TIMA, Grenoble,
DIGITAL VS. ANALOG SIGNAL PROCESSING Digital signal processing (DSP) characterized by: OUTLINE APPLICATIONS OF DIGITAL SIGNAL PROCESSING
1 DSP applications DSP platforms The synthesis problem Models of computation OUTLINE 2 DIGITAL VS. ANALOG SIGNAL PROCESSING Digital signal processing (DSP) characterized by: Time-discrete representation
Linköping University Post Print. epuma: a novel embedded parallel DSP platform for predictable computing
Linköping University Post Print epuma: a novel embedded parallel DSP platform for predictable computing Jian Wang, Joar Sohl, Olof Kraigher and Dake Liu N.B.: When citing this work, cite the original article.
Hardware-Software Codesign. 1. Introduction
Hardware-Software Codesign 1. Introduction Lothar Thiele 1-1 Contents What is an Embedded System? Levels of Abstraction in Electronic System Design Typical Design Flow of Hardware-Software Systems 1-2
DESIGN AND IMPLEMENTATION OF SDR SDRAM CONTROLLER IN VHDL. Shruti Hathwalia* 1, Meenakshi Yadav 2
ISSN 2277-2685 IJESR/November 2014/ Vol-4/Issue-11/799-807 Shruti Hathwalia et al./ International Journal of Engineering & Science Research DESIGN AND IMPLEMENTATION OF SDR SDRAM CONTROLLER IN VHDL ABSTRACT
Co-Design of Many-Accelerator Heterogeneous Systems Exploiting Virtual Platforms. SAMOS XIV July 14-17,
Co-Design of Many-Accelerator Heterogeneous Systems Exploiting Virtual Platforms SAMOS XIV July 14-17, 2014 1 Outline Introduction + Motivation Design requirements for many-accelerator SoCs Design problems
The Design of the KiloCore Chip
The Design of the KiloCore Chip Aaron Stillmaker*, Brent Bohnenstiehl, Bevan Baas DAC 2017: Design Challenges of New Processor Architectures University of California, Davis VLSI Computation Laboratory
Embedded Systems. 7. System Components
Embedded Systems 7. System Components Lothar Thiele 7-1 Contents of Course 1. Embedded Systems Introduction 2. Software Introduction 7. System Components 10. Models 3. Real-Time Models 4. Periodic/Aperiodic
Re-Examining Conventional Wisdom for Networks-on-Chip in the Context of FPGAs
This work was funded by NSF. We thank Xilinx for their FPGA and tool donations. We thank Bluespec for their tool donations. Re-Examining Conventional Wisdom for Networks-on-Chip in the Context of FPGAs
Vdd Programmable and Variation Tolerant FPGA Circuits and Architectures
Vdd Programmable and Variation Tolerant FPGA Circuits and Architectures Prof. Lei He EE Department, UCLA LHE@ee.ucla.edu Partially supported by NSF. Pathway to Power Efficiency and Variation Tolerance
Outline Marquette University
COEN-4710 Computer Hardware Lecture 1 Computer Abstractions and Technology (Ch.1) Cristinel Ababei Department of Electrical and Computer Engineering Credits: Slides adapted primarily from presentations
3D TECHNOLOGIES: SOME PERSPECTIVES FOR MEMORY INTERCONNECT AND CONTROLLER
3D TECHNOLOGIES: SOME PERSPECTIVES FOR MEMORY INTERCONNECT AND CONTROLLER CODES+ISSS: Special session on memory controllers Taipei, October 10 th 2011 Denis Dutoit, Fabien Clermidy, Pascal Vivet {denis.dutoit@cea.fr}
Spiral 2-8. Cell Layout
2-8.1 Spiral 2-8 Cell Layout 2-8.2 Learning Outcomes I understand how a digital circuit is composed of layers of materials forming transistors and wires I understand how each layer is expressed as geometric
VLSI Design Automation. Maurizio Palesi
VLSI Design Automation 1 Outline Technology trends VLSI Design flow (an overview) 2 Outline Technology trends VLSI Design flow (an overview) 3 IC Products Processors CPU, DSP, Controllers Memory chips
ECE 636. Reconfigurable Computing. Lecture 2. Field Programmable Gate Arrays I
ECE 636 Reconfigurable Computing Lecture 2 Field Programmable Gate Arrays I Overview Anti-fuse and EEPROM-based devices Contemporary SRAM devices - Wiring - Embedded New trends - Single-driver wiring -
Model-Based Design for effective HW/SW Co-Design Alexander Schreiber Senior Application Engineer MathWorks, Germany
Model-Based Design for effective HW/SW Co-Design Alexander Schreiber Senior Application Engineer MathWorks, Germany 2013 The MathWorks, Inc. 1 Agenda Model-Based Design of embedded Systems Software Implementation
Efficient Systems. Micrel lab, DEIS, University of Bologna. Advisor
Row-based Design Methodologies To Compensate Variability For Energy- Efficient Systems Micrel lab, DEIS, University of Bologna Mohammad Reza Kakoee PhD Student m.kakoee@unibo.it it Luca Benini Advisor
FABRICATION TECHNOLOGIES
FABRICATION TECHNOLOGIES DSP Processor Design Approaches Full custom Standard cell** higher performance lower energy (power) lower per-part cost Gate array* FPGA* Programmable DSP Programmable general
VLSI Design of Multichannel AMBA AHB
RESEARCH ARTICLE OPEN ACCESS VLSI Design of Multichannel AMBA AHB Shraddha Divekar,Archana Tiwari M-Tech, Department Of Electronics, Assistant professor, Department Of Electronics RKNEC Nagpur,RKNEC Nagpur
Asynchronous on-chip Communication: Explorations on the Intel PXA27x Peripheral Bus
Asynchronous on-chip Communication: Explorations on the Intel PXA27x Peripheral Bus Andrew M. Scott, Mark E. Schuelein, Marly Roncken, Jin-Jer Hwan John Bainbridge, John R. Mawer, David L. Jackson, Andrew
Chapter 5: ASICs Vs. PLDs
Chapter 5: ASICs Vs. PLDs 5.1 Introduction A general definition of the term Application Specific Integrated Circuit (ASIC) is virtually every type of chip that is designed to perform a dedicated task.
The extreme Adaptive DSP Solution to Sensor Data Processing
The extreme Adaptive DSP Solution to Sensor Data Processing Abstract Martin Vorbach PACT XPP Technologies Leo Mirkin Sky Computers, Inc. The new ISR mobile autonomous sensor platforms present a difficult
Adaptive Voltage Scaling (AVS) Alex Vainberg October 13, 2010
Adaptive Voltage Scaling (AVS) Alex Vainberg Email: alex.vainberg@nsc.com October 13, 2010 Agenda AVS Introduction, Technology and Architecture Design Implementation Hardware Performance Monitors Overview
Lab. Course Goals. Topics. What is VLSI design? What is an integrated circuit? VLSI Design Cycle. VLSI Design Automation
Course Goals Lab Understand key components in VLSI designs Become familiar with design tools (Cadence) Understand design flows Understand behavioral, structural, and physical specifications Be able to
Programmable Logic Devices II
São José February 2015 Prof. Hoeller, Prof. Moecke (http://www.sj.ifsc.edu.br) 1 / 28 Lecture 01: Complexity Management and the Design of Complex Digital Systems Prof. Arliones Hoeller arliones.hoeller@ifsc.edu.br
08 - Address Generator Unit (AGU)
October 2, 2014 Todays lecture Memory subsystem Address Generator Unit (AGU) Schedule change A new lecture has been entered into the schedule (to compensate for the lost lecture last week) Memory subsystem
Massively Parallel Computing on Silicon: SIMD Implementations. V.M.. Brea Univ. of Santiago de Compostela Spain
Massively Parallel Computing on Silicon: SIMD Implementations V.M.. Brea Univ. of Santiago de Compostela Spain GOAL Give an overview on the state-of of-the- art of Digital on-chip CMOS SIMD Solutions,
SYSTEMS ON CHIP (SOC) FOR EMBEDDED APPLICATIONS
SYSTEMS ON CHIP (SOC) FOR EMBEDDED APPLICATIONS Embedded System System Set of components needed to perform a function Hardware + software +. Embedded Main function not computing Usually not autonomous
Operating system integrated energy aware scratchpad allocation strategies for multiprocess applications
University of Dortmund Operating system integrated energy aware scratchpad allocation strategies for multiprocess applications Robert Pyka * Christoph Faßbach * Manish Verma + Heiko Falk * Peter Marwedel
A Low Power Asynchronous FPGA with Autonomous Fine Grain Power Gating and LEDR Encoding
A Low Power Asynchronous FPGA with Autonomous Fine Grain Power Gating and LEDR Encoding N.Rajagopala krishnan, k.sivasuparamanyan, G.Ramadoss Abstract Field Programmable Gate Arrays (FPGAs) are widely
VLSI Design Automation
VLSI Design Automation IC Products Processors CPU, DSP, Controllers Memory chips RAM, ROM, EEPROM Analog Mobile communication, audio/video processing Programmable PLA, FPGA Embedded systems Used in cars,
DIGITAL DESIGN TECHNOLOGY & TECHNIQUES
DIGITAL DESIGN TECHNOLOGY & TECHNIQUES CAD for ASIC Design 1 INTEGRATED CIRCUITS (IC) An integrated circuit (IC) consists complex electronic circuitries and their interconnections. William Shockley et
Multicore SoC is coming. Scalable and Reconfigurable Stream Processor for Mobile Multimedia Systems. Source: 2007 ISSCC and IDF.
Scalable and Reconfigurable Stream Processor for Mobile Multimedia Systems Liang-Gee Chen Distinguished Professor General Director, SOC Center National Taiwan University DSP/IC Design Lab, GIEE, NTU 1
Mapping and Configuration Methods for Multi-Use-Case Networks on Chips
Mapping and Configuration Methods for Multi-Use-Case Networks on Chips Srinivasan Murali, Stanford University Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli, Ecole Polytechnique Federal
Computer Architecture
Computer Architecture Slide Sets WS 2013/2014 Prof. Dr. Uwe Brinkschulte M.Sc. Benjamin Betting Part 10 Thread and Task Level Parallelism Computer Architecture Part 10 page 1 of 36 Prof. Dr. Uwe Brinkschulte,
Multithreaded Coprocessor Interface for Dual-Core Multimedia SoC
Multithreaded Coprocessor Interface for Dual-Core Multimedia SoC Student: Chih-Hung Cho Advisor: Prof. Chih-Wei Liu VLSI Signal Processing Group, DEE, NCTU 1 Outline Introduction Multithreaded Coprocessor
Synthesizable FPGA Fabrics Targetable by the VTR CAD Tool
Synthesizable FPGA Fabrics Targetable by the VTR CAD Tool Jin Hee Kim and Jason Anderson FPL 2015 London, UK September 3, 2015 2 Motivation for Synthesizable FPGA Trend towards ASIC design flow Design
Energy Efficient Computing Systems (EECS) Magnus Jahre Coordinator, EECS
Energy Efficient Computing Systems (EECS) Magnus Jahre Coordinator, EECS Who am I? Education Master of Technology, NTNU, 2007 PhD, NTNU, 2010. Title: «Managing Shared Resources in Chip Multiprocessor Memory
Virtual Array Architecture for efpga April 5, 2018
Virtual Array Architecture for efpga April 5, 2018 Cheng C. Wang SVP of Engineering Copyright 2014-2018 Flex Logix Technologies, Inc. Why the Need for Virtual Arrays? Security: Keep your secret sauce design
Controller Synthesis for Hardware Accelerator Design
ler Synthesis for Hardware Accelerator Design Jiang, Hongtu; Öwall, Viktor 2002 Link to publication Citation for published version (APA): Jiang, H., & Öwall, V. (2002). ler Synthesis for Hardware Accelerator
Analyzing and Debugging Performance Issues with Advanced ARM CoreLink System IP Components
Analyzing and Debugging Performance Issues with Advanced ARM CoreLink System IP Components By William Orme, Strategic Marketing Manager, ARM Ltd. and Nick Heaton, Senior Solutions Architect, Cadence Finding
UNIT 4 INTEGRATED CIRCUIT DESIGN METHODOLOGY E5163
UNIT 4 INTEGRATED CIRCUIT DESIGN METHODOLOGY E5163 LEARNING OUTCOMES 4.1 DESIGN METHODOLOGY By the end of this unit, student should be able to: 1. Explain the design methodology for integrated circuit.
Lecture 41: Introduction to Reconfigurable Computing
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 41: Introduction to Reconfigurable Computing Michael Le, Sp07 Head TA April 30, 2007 Slides Courtesy of Hayden So, Sp06 CS61c Head TA Following
EE382V: System-on-a-Chip (SoC) Design
EE382V: System-on-a-Chip (SoC) Design Lecture 10 Task Partitioning Sources: Prof. Margarida Jacome, UT Austin Prof. Lothar Thiele, ETH Zürich Andreas Gerstlauer Electrical and Computer Engineering University
EITF35: Introduction to Structured VLSI Design
EITF35: Introduction to Structured VLSI Design Part 1.1.2: Introduction (Digital VLSI Systems) Liang Liu liang.liu@eit.lth.se 1 Outline Why Digital? History & Roadmap Device Technology & Platforms System
Higher Level Programming Abstractions for FPGAs using OpenCL
Higher Level Programming Abstractions for FPGAs using OpenCL Desh Singh Supervising Principal Engineer Altera Corporation Toronto Technology Center ! Technology scaling favors programmability CPUs."#/0$*12'$-*
Intellectual Property Macrocell for. SpaceWire Interface. Compliant with AMBA-APB Bus
Intellectual Property Macrocell for SpaceWire Interface Compliant with AMBA-APB Bus L. Fanucci, A. Renieri, P. Terreni Tel. +39 050 2217 668, Fax. +39 050 2217522 Email: luca.fanucci@iet.unipi.it - 1 -
A Novel Design Framework for the Design of Reconfigurable Systems based on NoCs
Politecnico di Milano & EPFL A Novel Design Framework for the Design of Reconfigurable Systems based on NoCs Vincenzo Rana, Ivan Beretta, Donatella Sciuto Donatella Sciuto sciuto@elet.polimi.it Introduction
Hardware Software Codesign of Embedded Systems
Hardware Software Codesign of Embedded Systems Rabi Mahapatra Texas A&M University Today s topics Course Organization Introduction to HS-CODES Codesign Motivation Some Issues on Codesign of Embedded System
FPGA for Complex System Implementation. National Chiao Tung University Chun-Jen Tsai 04/14/2011
FPGA for Complex System Implementation National Chiao Tung University Chun-Jen Tsai 04/14/2011 About FPGA FPGA was invented by Ross Freeman in 1989 SRAM-based FPGA properties Standard parts Allowing multi-level
Low-Power Technology for Image-Processing LSIs
Low- Technology for Image-Processing LSIs Yoshimi Asada The conventional LSI design assumed power would be supplied uniformly to all parts of an LSI. For a design with multiple supply voltages and a power
VLSI Design Automation. Calcolatori Elettronici Ing. Informatica
VLSI Design Automation 1 Outline Technology trends VLSI Design flow (an overview) 2 IC Products Processors CPU, DSP, Controllers Memory chips RAM, ROM, EEPROM Analog Mobile communication, audio/video processing
Enhancing Energy Efficiency of Processor-Based Embedded Systems thorough Post-Fabrication ISA Extension
Enhancing Energy Efficiency of Processor-Based Embedded Systems thorough Post-Fabrication ISA Extension Hamid Noori, Farhad Mehdipour, Koji Inoue, and Kazuaki Murakami Institute of Systems, Information
Organic Computing. Dr. rer. nat. Christophe Bobda Prof. Dr. Rolf Wanka Department of Computer Science 12 Hardware-Software-Co-Design
Dr. rer. nat. Christophe Bobda Prof. Dr. Rolf Wanka Department of Computer Science 12 Hardware-Software-Co-Design 1 Reconfigurable Computing Platforms 2 The Von Neumann Computer Principle In 1945, the
Integrated Circuit Design Using. Open Cores and Design Tools. Martha SaloméLópez de la Fuente
Integrated Circuit Design Using Open Cores and Design Tools Martha SaloméLópez de la Fuente Science Publishing Group 548 Fashion Avenue New York, NY 10018 www.sciencepublishinggroup.com Published by Science
IMAGINE: Signal and Image Processing Using Streams
IMAGINE: Signal and Image Processing Using Streams Brucek Khailany William J. Dally, Scott Rixner, Ujval J. Kapasi, Peter Mattson, Jinyung Namkoong, John D. Owens, Brian Towles Concurrent VLSI Architecture
SystemC, OCCN and VPs. Integrated Systems Development NoC Round Table, ESTEC 17 September 2009
SystemC, OCCN and VPs M. Grammatikakis,, E. Politis and C. Papadas Integrated Systems Development NoC Round Table, ESTEC 17 September 2009 On SoC/NoC Modeling Developments ISD has contributed to the design,
ARM Processors for Embedded Applications
ARM Processors for Embedded Applications Roadmap for ARM Processors ARM Architecture Basics ARM Families AMBA Architecture 1 Current ARM Core Families ARM7: Hard cores and Soft cores Cache with MPU or