Experiment Fall Experiment 1: PLD ALU R&D and V&V

Transcription

1 Experiment Fall 2003 Experiment 1: PLD R&D and V&V Objectives: To gain experience with programmable logic devices and the tools available in the lab to program them. To refresh your memory on Boolean algebra and designs. To gain experience with the breadboards and test equipment in the 583 lab. Reading: Lecture Notes. Computer Organization and Design by Patterson and Hennessy (EE380 Text Book). PLD reference material on the course web page. Introduction: The muscle of any microprocessor is the data path and the bicept, if you will, of the data path is the. The functions of the define much of the instruction set of the machine and the efficiency of the design has a big impact on the performance of the processor. In this lab experiment you will implement an using programmable logic devices and then integrate your into a microprocessor. All of the hardware we will build will be implemented with commonly available programmable logic devices. You will find a skeleton file for the on the course web site. It is your job to download this file, make the necessary modifications to make the work, burn it into a chip and test it. Figure 1 shows a simple block diagram of the we will build. Control Inputs Flags Bus Interface Bus Figure 1: Overview

2 Experiment Fall 2003 The primary difference between this and the we designed in lecture is that this includes an accumulator. Accumulator based microprocessors were very popular in the early days of computing because it simplified the hardware. The accumulator is always implied as one of the operands in operations and is always implied as the destination for the result of the calculation. To use the Motorola terminology, the Accumulator is specified using the inherent addressing mode. For example, if we wanted to add two numbers using an accumulator based microcontroller and our two numbers are in memory locations named oper1 and oper2 respectively, the instruction sequence required may look something like this: LDA oper1 ; load accumulator with data at location ; oper1 (operand 1) ADD oper2 ; add the operand at location oper2 to the ; contents of the accumulator, the result ; always returns to the accumulator After this sequence completes, the answer would be in the accumulator which could be used in further calculations or stored back to memory. Another way to think of an accumulator machine is as a stack-based machine with only a one element stack. In this case, the top of the stack is poped off to be used as one operand and then the result is pushed on the stack. (Note: RPN calculators use the stack very effectively to carry out calculations, I have gotten to the point where it is very difficult for me to use non-rpn calculators, but that is beside the point). The point is that the stack model (and the one element stack model, aka, accumulator model) is a valid way for a microcontroller to carry out computation. In addition the same thing that made the accumulator-based microcontroller popular in the first computers is the same thing that makes it an attractive model for us to implement in programmable logic. The machine only needs one register for all calculations! This saves silicon and wires and, most importantly, debugging time in the lab when you try to build it. Let s take a closer look at the. For our simple we will limit ourselves to 4 operations, namely, ADD, AND, LSL, LDA. The first three are typical type operations, and the fourth is necessary to allow us to get operands from the bus into the accumulator (to load the accumulator). To further simplify our task, we will implement a 4-bit, that is an that operates on 4-bit operands. As you recall, we built an 8-bit s with 8 one-bit s with all 8 blocks of logic being identical. Because this lab is not intended as a test of your ability to cut and paste equations, it will suffice to do 4 bits. Once you can do 4 bits 8, 32, 128 bits is easy. Figure 2 shows a detailed block diagram of our, so lets take a look at our signals in Figure 2. First consider the inputs: X and Y define the operation (ADD, AND, LSL, or LDA). ACCin is used to latch results into the accumulator, and ACCout is used to assert the value on in the accumulator onto the bus. Since this is a bus, we must

3 Experiment Fall 2003 use tri-state outputs to prevent two drivers on the bus. (This can be a real problem, like when Sandra Bullock and Keanu Reeves were both trying to reach the pedals and steer scary stuff). The final inputs to our are the four bits of the bus itself which are used as one of the operands in the. The other 8 signals are all outputs. The first and foremost outputs are the four bits of data in the accumulator. When ACCout is asserted, the contents of the accumulator are asserted on the bus via a tri-state. The Flags constitute the other 4 outputs. The flags we will support in our are C (carry), N (negative), Z (zero), and V (Overflow). N and Z are simply functions of the contents of the accumulator, and as such, could be generated as functions of the accumulator bits. However, there are some instructions that we do not want to affect the flags so giving these two flags their very own flip-flops makes for a cleaner/better design. The other two flags are generated by the computation itself and can not be derived from the contents of the accumulator after the calculation completes. These Flags are Carry and Overflow. In order, to have these signals persist we must determine them during the calculation, and then latch them. The question then arises: When should we latch the flags? (Stop, Think, and answer this question before you turn the page. If people look at you funny pretend you have one of those ear-bud cell phones and are not just talking to yourself.) X Y ACCin ACCout Accumulator Flags(CNZV) Tri-state Bus Figure 2: Block Diagram

4 Experiment Fall 2003 You are right! Think of it this way, the flags are as much a result of the calculation performed in the as the sum bits, so we should use the ACCin signal. Nicely done, give yourself $5. OK, to further steer you in the right direction (get it steer bus, I got million of em), I have provided a summary of the operations of the instruction and Table 1 shows a truth table for the operation of the. ADD: Q3,Q2,Q1,Q0 <- Q3,Q2,Q1,Q0 + D3,D2,D1,D0 AND: Q3,Q2,Q1,Q0 <- Q3,Q2,Q1,Q0 & D3,D2,D1,D0 LSL: Q3,Q2,Q1,Q0 <- Q2,Q1,Q0,0 LDA: Q3,Q2,Q1,Q0 <- D3,D2,D1,D0 Where QX represents the contents of the bits of the accumulator and DX represents the data present on the bits of the data bus. Control Signals Function Flags Affected ACCout ACCin ALX ALY CF NF ZY VF ADD Y Y Y Y AND N Y Y N LSL Y Y Y N LDA N Y Y N 1 0 d d Acc on Bus N N N N Experiment: Once you have downloaded the skeleton, made the necessary changes and programmed it into a Mach chip you must connect it into a circuit and test it. To really put it through its paces, you need to simulate the control and other data-path hardware the would find itself connected to in a real processor. To do this we will use a breadboard and a little more glue logic to interface with the. First and foremost, you will need a bus, a way to input values on the bus, and way to monitor the bus. We have provided a design for a 22V10 to provide the necessary hardware to interface with the bus to a dip switch. You can download this from the course web site and burn it into a 22V10 (or use one of the pre-burned chips provided in the lab). To monitor the state of the bus we can use a simple TTL inverter. This will be only a single TTL input and will not load the bus. The inverter can then be used to drive LEDs so we can easily visually confirm the state of the bus. In addition, to provide a clean bounce free signal for ACCin (remember, this will be connected to the clock input of the accumulator flip-flops) we will use a debounce switch. You can make this switch with a flip-flop, some NAND gates, or the debounce switches built into the protoboards in the lab.

5 Experiment Fall 2003 Finally, we will need a way to observe the state of the flags. Again LEDs are the best bet for this. Figure 3 shows the overall configuration of your test circuit. Flags (CNZV) Debounce Switch DIP switches ACCin Switches 22V10 Hex Inverter ALX ALY ACCout DIP switch BUS Note: use Synario or ispexpert to compile your abel file (ipslever will not work). IspVM should be used to program the Mach211 parts at your lab stations or the Chipmaster specific software if you are using the big programmer in 583 lab or the 481 lab. Data sheets for all the parts can be found on the course web page. Once you have the circuit working, demonstrate its operation to the instructor. Instructor Signature: