Transitioning the I ntel Next. ( Nehalem and W estm ere) into the. Lily Looi, St ephan Jourdan I ntel Corporation Hot Chips 21 August 24, 2009

Transcription

1 Transitioning the I ntel Next Generation Microarchitectures ( Nehalem and W estm ere) into the Mainstream Lily Looi, St ephan Jourdan I ntel Corporation Hot Chips 21 August 24,

2 Agenda Next Generation Mainstream CPU s New Technologies for I ntegration for 2009 and beyond 2 2

3 Mem ory Cont roller I ntel Core i7 Recap Misc I O Core Core Core Core Queue Shared L3 Cache Misc I O QPI 0 QPI: Intel QuickPath Interconnect (Intel QPI) Core m icroarchit ect ure I ncreased parallelism e.g. 33% larger out of order window, handle m ore cache m isses sim ult aneously Enhanced algorit hm s e.g. faster unaligned cache accesses, faster sync prim itives, loop stream ing detector, m acro-fusion Better branch prediction e.g. 2nd level branch predictor, renam ed RSB New I nstructions (SSE4) I ntel Hyper-Threading Technology Uncore m icroarchit ect ure and connect ivit y Scalable m ulti-core fabric Shared last level Cache I ntegrated m em ory controller I ntel QuickPath I nterconnect Pow er m anagem ent t echnologies PCU Microcontroller I ntel Turbo Boost Technology I ntegrated power gates 3 3

4 Enabling Nehalem for Every Segm ent Cores / 8 Threads 2 Cores / 4 Threads w ith I ntegrated Graphics Mainstream Desktop Thin & Light Laptop 4 5 nm High- K 3 2 nm High- K Delivering Outstanding Nehalem Perform ance to Mainstream Desktops and Laptop Com puters 4 4 I nt el Microarchitecture codenam ed Nehalem

5 Mainstream Platform Partitioning I ntel Core 2 Processor based 3 - Chip Solution PCIe* Graphics DISPLAY Clock s Processor Intel 4 Series Chipset igfx Display ICH10 I/O FSB DMI IMC ME DDR2/3 PCIe* Graphics DISPLAY Nehalem / W estm ere based 2 - Chip Solution I ntel Flexible Display I nterface ( I ntel FDI ) igfx Processor Intel 5 series Chipset Display DMI I/O ME Clock Buffe r IMC DDR3 Graphics m oves int o Processor 1 Mem ory Cont roller m oves int o t he Processor Display m oves int o I ntel 5 series chipset ( I bex Peak) I ntel Manageabilit y Engine m oves int o I nt el 5 series chipset ( I bex Peak) Greater Perform ance and Low er Pow er through I ntegration 1. I ntegrat ed graphics on Clarkdale/ Arrandale 5 5 I nt el Microarchitecture codenam ed Nehalem Westm ere: 32nm version of I ntel m icroarchitect ure codenam e Nehalem

6 Mainstream Microprocessors Lynnfield/Clarksfield Clarkdale / Arrandale DDR3 4 5 nm processor ( single die) DDR3 DMI Discret e Graphics 1 x1 6 or 2 x8, Gen2 3 2 nm W est m ere processor core Intel FDI DMI Processor Graphics or Discrete / Switchable Graphics 4 5 nm igfx Intel 5 series Chipset Discrete graphics Manageability, Security, Display, PCI e, SATA, etc. Intel 5 series Chipset Integrated or discrete graphics 6

7 Agenda Next Generation Mainstream CPU s New Technologies for I ntegration for 2009 and beyond Integrated Power Gates Intel Turbo Boost Technology Intel Hyper-Threading Technology Energy Efficient performance Single Thread Multi-threads 7 7

8 I ntegrated Pow er Gates I ntegrated Power Gates (switches) are critical for integration, turning individual com ponent blocks on/ off Zero leakage power, low latency to wake block Key benefits in both idle and active power VCC Nehalem t urns individual cores on/ off Transparent to OS Reduces latency to wake a core Modular/ Scalable Clocking Cores, Mem ory System, I / O can run at independent voltage/ frequency Core0 Core1 Core2 Core3 Memory System, Cache, I/O VTT Extended in 2009 platform s as I ntegrated Power Gates also used in shared cache and I / O logic to dynam ically power down when inact ive I ntegrated Pow er Gates enable Energy Efficient I ntegration 8 8 I nt el Microarchitecture codenam ed Nehalem

9 I ntel Turbo Boost Technology I ntegration splits power allocation am ong m ore com ponent blocks I ntel Turbo Boost Technology is critical to dynam ically m anage power allocation and seam lessly m axim ize perform ance Higher benefits in sm aller form factors Lynnfield/ Clarksfield Higher Frequency Awake: Lower core activity Sleep Core 1 Core 2 Core 3 Core 4 Dynam ically Scaled Perform ance Boost 9 9

10 I ntel Hyper- Threading Technology Nehalem is a scalable m ulti-core architecture Hyper- Threading Technology augm ent s benefit s Power-efficient way to boost perform ance in all form factors: higher m ulti-threaded perform ance, faster m ulti-tasking response Without HT Technology With HT Technology Next generat ion Hyper- Threading Technology: Low- lat ency pipeline archit ect ure Enhanced cache archit ect ure Higher m em ory bandwidth Hyper-Threading Multi-cores Shared or Partitioned Replicated Replicated Register State X X Return Stack X X Reorder Buffer X X Instruction TLB X X Reservation Stations X X Cache (L1, L2) X X Data TLB X X Execution Units X X Enables 8 - w ay processing in Quad Core system s, 4 - w ay processing in Sm all Form Factors I nt el Microarchitecture codenam ed Nehalem

11 Energy Efficient Perform ance Many innovations in energy efficiency such as loop-stream ing detector and dynam ic loadline As looping is very com m on to every type of applications, Nehalem loopstream ing detector captures bigger loops and saves m ore energy IIntel Core 2 i7 Processor Pipeline Branch Predict ion Fet ch Queue Decode ( Loop) Queue Decode ( Loop) Execut e V P = V x I Dynam ic only loadline (PCU) Current cdt n Power = Voltage x Current I n prior processors, voltage line is anchored based on worst case Nehalem lowers Voltage based on current conditions: # active cores, tem perature, and saves m ore energy. W orst case I I nt el Major I nnovations in Energy Efficiency Microarchitecture codenam ed Nehalem

12 Sum m ary I ntel m aintains pace of innovation and execution Next generat ion perform ance 32nm : Anot her Process Technology Breakt hrough Enabling Nehalem for every segm ent Delivering outstanding Nehalem perform ance to m ainstream desktops and laptop com puters Redesigning m ore efficient platform s Best perform ance across all segm ents Low power and better power m anagem ent Higher levels of integration I nt el Microarchitecture codenam ed Nehalem

13 Q& A

14 Backup

15 Lynnfield/ Clarksfield Microarchitecture Built on m odularity of I ntel Core i7 Further integration to support new m ainstream platform s: VTd and I O virtualization support DDR3 PCI Express* int erface x16 PCI e configurable to 2x8 2.5 GT/ s (Gen1) and 5 GT/ s (Gen2) Flexible interface: lane reversal, dynam ic speed and link width changes, peer to peer posted writes Power Optim ization: L0s/ L1 support, low-voltage swing m ode and de-em phasis x4 DMI I nterface Series 5 enhancem ents Extended power m anagem ent Graphics DDR3 I MC PCI - E Core Core Core Core Thread Thread Thread Thread Pow er Thread Thread Thread Thread DMI 8 M I nt el 5 series Chipse t

16 I ntegrated Graphics and Media Architecture ( Clarkdale, Arrandale) Vertex Fetch VS/GS Setup/Rasterize Add l 3D Fixed Fxn Shaded Vertices EU EU Dedicated HD Decode Pipelines VLD EU Unified Execution Unit Array MPEG2 VLD IT EU EU MC/LF in EUs Mathbox Mathbox EU MC VC1 IT AVC IT VLD Mathbox MC MC LF LF Cache Texture Unit Pixel backend Post Process Unified Shader Archit ect ure Evolution of G965 & GM965 DX10 & Shader Model 4.0 in HW Full HD Decode, High Quality Video 6 threads/ EU Hierarchical Dept h Buffer Dynam ic load balanced Multi-functional; m ulti-threaded Enables scalability and flexibility I m proved Extended Math, larger caches

17 Legal Disclaim er I NFORMATI ON I N THI S DOCUMENT I S PROVI DED I N CONNECTI ON WI TH I NTEL PRODUCTS. NO LI CENSE, EXPRESS OR I MPLI ED, BY ESTOPPEL OR OTHERWI SE, TO ANY I NTELLECTUAL PROPERTY RI GHTS I S GRANTED BY THI S DOCUMENT. EXCEPT AS PROVI DED I N I NTEL S TERMS AND CONDI TI ONS OF SALE FOR SUCH PRODUCTS, I NTEL ASSUMES NO LI ABI LI TY WHATSOEVER, AND I NTEL DI SCLAI MS ANY EXPRESS OR I MPLI ED WARRANTY, RELATI NG TO SALE AND/ OR USE OF I NTEL PRODUCTS I NCLUDI NG LI ABI LI TY OR WARRANTI ES RELATI NG TO FI TNESS FOR A PARTI CULAR PURPOSE, MERCHANTABI LI TY, OR I NFRI NGEMENT OF ANY PATENT, COPYRI GHT OR OTHER I NTELLECTUAL PROPERTY RI GHT. I NTEL PRODUCTS ARE NOT I NTENDED FOR USE I N MEDI CAL, LI FE SAVI NG, OR LI FE SUSTAI NI NG APPLI CATI ONS. I ntel m ay m ake changes to specifications and product descriptions at any tim e, without notice. All products, dates, and figures specified are prelim inary based on current expectations, and are subject to change without notice. I ntel, processors, chipsets, and desktop boards m ay contain design defects or errors known as errata, which m ay cause the product to deviate from published specifications. Current characterized errata are available on request. Nehalem, Lynnfield, Clarkdale, Clarksfield, Arrandale, Westm ere, I bex Peak and other code nam es featured are used internally within I ntel to identify products that are in developm ent and not yet publicly announced for release. Custom ers, licensees and other third parties are not authorized by I ntel to use code nam es in advertising, prom otion or m arketing of any product or services and any such use of I ntel's internal code nam es is at the sole risk of the user Perform ance tests and ratings are m easured using specific com puter system s and/ or com ponents and reflect the approxim ate perform ance of I ntel products as m easured by those tests. Any difference in system hardware or software design or configuration m ay affect actual perform ance. I ntel, Core and the I ntel logo are tradem arks of I ntel Corporation in the United States and other countries. * Other nam es and brands m ay be claim ed as the property of others. Copyright 2009 I nt el Corporat ion. I ntel Active Managem ent Technology requires the com puter system to have an I ntel AMT-enabled chipset, network hardware and software, as well as connection with a power source and a corporate network connection. Setup requires configuration by the purchaser and m ay require scripting with the m anagem ent console or further integration into existing security fram eworks to enable certain functionality. I t m ay also require m odifications of im plem entation of new business processes. With regard to notebooks, I ntel AMT m ay not be available or certain capabilities m ay be lim ited over a host OS-based VPN or when connecting wirelessly, on battery power, sleeping, hibernating or powered off. For m ore inform ation, see / technology/ platform -technology/ intel-am t/

18 Risk Factors The above statem ents and any others in this docum ent that refer to plans and expectations for the first quarter, the year and the future are forwardlooking statem ents that involve a num ber of risks and uncertainties. Many factors could affect I ntel s actual results, and variances from I ntel s current expectations regarding such factors could cause actual results to differ m aterially from those expressed in these forward-looking statem ents. I ntel presently considers the following to be the im portant factors that could cause actual results to differ m aterially from the corporation s expectations. Current uncertainty in global econom ic conditions pose a risk to the overall econom y as consum ers and businesses m ay defer purchases in response to tighter credit and negative financial news, which could negatively affect product dem and and other related m atters. Consequently, dem and could be different from I ntel's expectations due to factors including changes in business and econom ic conditions, including conditions in the credit m arket that could affect consum er confidence; custom er acceptance of I ntel s and com petitors products; changes in custom er order patterns including order cancellations; and changes in the level of inventory at custom ers. I ntel operates in intensely com petitive industries that are characterized by a high percentage of costs that are fixed or difficult to reduce in the short term and product dem and that is highly variable and difficult to forecast. Revenue and the gross m argin percentage are affected by the tim ing of new I ntel product introductions and the dem and for and m arket acceptance of I ntel's products; actions taken by I ntel's com petitors, including product offerings and introductions, m arketing program s and pricing pressures and I ntel s response to such actions; I ntel s ability to respond quickly to technological developm ents and to incorporate new features into its products; and the availability of sufficient supply of com ponents from suppliers to m eet dem and. The gross m argin percentage could vary significantly from expectations based on changes in revenue levels; capacity utilization; excess or obsolete inventory; product m ix and pricing; variations in inventory valuation, including variations related to the tim ing of qualifying products for sale; m anufacturing yields; changes in unit costs; im pairm ents of long-lived assets, including m anufacturing, assem bly/ test and intangible assets; and the tim ing and execution of the m anufacturing ram p and associated costs, including start-up costs. Expenses, particularly certain m arketing and com pensation expenses, as well as restructuring and asset im pairm ent charges, vary depending on the level of dem and for I ntel's products and the level of revenue and profits. The recent financial crisis affecting the banking system and financial m arkets and the going concern threats to investm ent banks and other financial institutions have resulted in a tightening in the credit m arkets, a reduced level of liquidity in m any financial m arkets, and extrem e volatility in fixed incom e, credit and equity m arkets. There could be a num ber of follow-on effects from the credit crisis on I ntel s business, including insolvency of key suppliers resulting in product delays; inability of custom ers to obtain credit to finance purchases of our products and/ or custom er insolvencies; counterparty failures negatively im pacting our treasury operations; increased expense or inability to obtain short-term financing of I ntel s operations from the issuance of com m ercial paper; and increased im pairm ents from the inability of investee com panies to obtain financing. I ntel's results could be im pacted by adverse econom ic, social, political and physical/ infrastructure conditions in the countries in which I ntel, its custom ers or its suppliers operate, including m ilitary conflict and other security risks, natural disasters, infrastructure disruptions, health concerns and fluctuations in currency exchange rates. I ntel's results could be affected by adverse effects associated with product defects and errata (deviations from published specifications), and by litigation or regulatory m atters involving intellectual property, stockholder, consum er, antitrust and other issues, such as the litigation and regulatory m atters described in I ntel's SEC reports. Rev. 1/ 15/