- Multiprocessor Instructions 32-Bit CPU with S4-Bit Data Bus. On-Chip Local APIC Controller - Two Pipelined Integer Units Are

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1 intel PENTUM PROCESSOR at icomp NDEX 61\75 MHz PENTUM PROCESSOR at icomp NDEX 735\9 MHz PENTUM PROCESSOR at icomp NDEX 815\ 1 MHz PENTUM PROCESSOR at icomp NDEX 1\ 12 MHz Compatible with Large Software Base Multi-Processor Support - MS-DOS:/:, Windows:/:, OS/2:/:, UNX:/: - Multiprocessor nstructions 32-Bit CPU with S4-Bit Data Bus - Support for Second Level Cache Superscalar Architecture On-Chip Local APC Controller - Two Pipelined nteger Units Are - MP nterrupt Management Capable of 2 nstructions/clock Compatible - Pipelined Floating Point Unit.. nternal Error Detection Features Separate Code and Data Caches Upgradable with a Future Pentium - 8K Code, 8K Write Back Data OverDrive Processor - MES Cache Protocol Power Management Features Advanced Design Features - System Management Mode - Branch Prediction - Clock Control - Virtual Mode Extensions Fractional Bus Operation 3.3V BiCMOS Silicon Technology - 12-MHz Core/SO-MHz Bus 4M Pages for ncreased TLB Hit Rate -1-MHz Core/SS-MHz Bus -1-MHz Core/5-MHz Bus EEE Boundary Scan - 9-MHz Core/SO-MHz Bus Dual Processing Configuration - 75-MHz Core/5-MHz Bus The Pentium processor 75/9/1/12 extends the Pentium processor family, providing performance need ed for mainstream desktop applications as well as for workstations and servers. The Pentium processor is compatible with the entire installed base of applications for DOS, Windows, OS/2, and UNX. The Pentium processor 75/9/1/12 superscalar architecture can execute two instructions per clock cycle. Branch prediction and separate caches also increase performance. The pipe lined floating point unit delivers worksta tion level performance. Separate code and data caches reduce cache conflicts while remaining software transparent. The Pentium processor 75/9/1/12 has 3.3 million transistors and is built on ntel's advanced 3.3V BiCMOS silicon technology. The Pentium processor 75/9/1/12 has on chip dual processing sup port, a local multiprocessor interrupt controller, and SL power management features :j:other brands and trademarks are the property of their respective owners. tsince publication of documents referenced in this document, registration of the Pentium, OverDrive, and icomp trade marks has been issued to ntel Corporation. nformation in this document is provided solely to enable use of ntel products. ntel assumes no liability whatsoever, including nfringement of any patent or copyright, for sale and use of ntel products except as provided in ntel's Terms and Conditions of Sale for such products. nformation contained herein supersedes previously published specifications on these devices from NTEL CORPORATON, 1995 March 1995 Order Number:

2 PENTUM PROCESSOR at icomp NDEX 61\75 MHz PENTUM PROCESSOR at icomp NDEX 735\9 MHz PENTUM PROCESSOR at icomp NDEX 815\ 1 MHz PENTUM PROCESSOR at icomp NDEX 1\ 12 MHz CONTENTS PAGE CONTENTS PAGE 1. MCROPROCESSOR ARCHTECTURE OVERVEW Pentium Processor Family Architecture Pentium Processor 75/9/1/ PNOUT Pinout and Pin Descriptions Design Notes Quick Pin Reference Pin Reference Tables Pin Grouping According to Function ELECTRCAL SPECFCATONS Electrical Differences Between Pentium Processor 75/9/1/12 and Pentium Processor 6/ Absolute Maximum Ratings DC Specifications AC Specifications MECHANCAL SPECFCATONS THERMAL SPECFCATONS Measuring Thermal Values FUTURE PENTUM OverDrive PROCESSOR SOCKET SPECFCATON ntroduction Future Pentium OverDrive Processor (Socket 5) Pinout Electrical Specifications Absolute Maximum Ratings of Upgrade Mechanical Specifications Thermal Specifications Upgradability with Socket Testability

3 PENTUM PROCESSOR 75/9/1/12 1. MCROPROCESSOR ARCHTECTURE OVERVEW The Pentium processor at icomp rating 61\75 MHz, icomp rating 735\9 MHz, and icomp rating 815\1 MHz extends the ntel Penti um family of microprocessors. t is 1% binary compatible with the 886/88, 8286, ntel386 DX CPU, ntel386 SX CPU, ntel486 DX CPU, ntel486 SX CPU, ntel486 DX2 CPUs, and Pentium processor at icomp ndex 51\6 MHz and icomp ndex 567\66 MHz. The Pentium processor family consists of the Pentium processor at icomp rating 61\75 MHz, icomp rating 735\9 MHz, and icomp rating 815\1 MHz (product order code 852), described in this document, and the original Pentium processor 6/66 (order code 851). The name "Pentium processor 751 9/1/12" will be used in this document to refer to the Pentium processor at icomp rating 61\75 MHz, icomp rating 735\9 MHz, icomp rating 815\1 MHz and icomp rating 1\12 MHz. Also, the name "Pentium processor 6/66" will be used to refer to the original 6- and 66-MHz version product. The Pentium processor family architecture contains all of the features of the ntel486 CPU family, and provides significant enhancements and additions including the following: Superscalar Architecture Dynamic Branch Prediction Pipelined Floating-Point Unit mproved nstruction Execution Time Separate 8K Code and 8K Data Caches Writeback MES Protocol in the Data Cache 64-Bit Data Bus Bus Cycle Pipelining Address Parity nternal Parity Checking Functional Redundancy Checking Execution Tracing Performance Monitoring EEE Boundary Scan System Management Mode Virtual Mode Extensions n addition to the features listed above, the Pentium processor 75/9/1/12 offers the following enhancements over the Pentium processor 6/66: icomp performance rating of 1 at 12 MHz in single processor configuration icomp performance rating of 815 at 1 MHz in single processor configuration icomp performance rating of 735 at 9 MHz in single processor configuration icomp performance rating of 61 at 75 MHz in single processor configuration Dual processing support SL power management features Upgradable with a Future Pentium OverDrive processor Fractional bus operation On-chip local APC device 1.1 Pentium Processor Family Architecture The application instruction set of the Pentium processor family includes the complete ntel486 CPU family instruction set with extensions to accommodate some of the additional functionality of the Pentium processors. All application software written for the ntel386 and ntel486 family microprocessors will run on the Pentium processors without modification. The on-chip memory management unit (MMU) is completely compatible with the ntel386 family and ntel486 family of CPUs. The Pentium processors implement several enhancements to increase performance. The two instruction pipelines and floating-point unit on Pentium processors are capable of independent operation. Each pipeline issues frequently used instructions in a single clock. Together. the dual pipes can issue two integer instructions in one clock, or one floating point instruction (under certain circumstances, two floating-point instructions) in one clock. Branch prediction is implemented in the Pentium processors. To support this, Pentium processors implement two prefetch buffers, one to prefetch code in a linear fashion, and one that prefetches code according to the BTB so the needed code is almost always prefetched before it is needed for execution. The floating-point unit has been completely redesigned over the ntel486 CPU. Faster algorithms provide up to lox speed-up for common operations including add, multiply, and load. 3

4 PENTU~ PROCESSOR 75/9/1/12 Pentium processors include separate code and data caches integrated on-chip to meet performance goals. Each cache is 8 Kbytes in size, with a 32-byte line size and is 2-way set associative. Each cache has a dedicated Translation Lookaside Buffer (TLB) to translate linear addresses to physical addresses. The data cache is configurable to be write back or write through on a line-by-ine basis and follows the MES protocol. The data cache tags are triple ported to support two data transfers and an inquire cycle in the same clock. The code cache is an inherently write-protected cache. The code cache tags are also triple ported to support snooping and split line accesses. ndividual pages can be configured as cacheable or non-cacheable by software or hardware. The caches can be enabled or disabled by software or hardware. The Pentium processors have increased the data bus to 64 bits to improve the data transfer rate. Burst read and burst write back cycles are supllorted by the Pentium processors. n addition, bus cycle pipelining has been added to allow two bus cycles to be in progress simultaneously. The Pentium processors' Memory Management Unit contains optional extensions to the architecture which allow 2-Mbyte and 4-Mbyte page sizes. The Pentium processors have added significant data integrity and error detection capability. Data parity checking is still supported on a byte-by-byte basis. Address parity checking, and internal parity checking features have been added along with a new exception, the machine check exception. n addition, the Pentium processors have implemented functional redundancy checking to provide maximum error detection of the processor and the interface to the processor. When functional redundancy checking is used, a second processor, the "checker" is used to execute in lock step with the "master" processor. The checker samples the master's outputs and compares those values with the values it computes internally, and asserts an error signal if a mismatch occurs. As more and more functions are integrated on chip, the complexity of board level testing is increased. To address this, the Pentium processors have increased test and debug capability. The Pentium processors implement EEE Boundary Scan (Standard ). n addition, the Pentium processors have specified 4 breakpoint pins that correspond to each of the debug registers and externally indicate a breakpoint match.. Execution tracing provides externa indicatioj1s-when an instruction has completed execution "in either of the two internal pipelines, or when a branch has been taken. System Management Mode (SMM) has been implemented along with some extensions to the SMM architecture. Enhancements to the virtual 886 mode have been made to increase performance by reducing the number of times it is necessary to trap to a virtual 886 monitor. Figure 1 shows a block diagram of the Pentium processor 75/9/1/12. For Pentium. Processor (61\75) designs which use the TCP package,lntel document must be referenced for correct TCP pinout, mechanical, thermal, and AC specifications. 4

5 PENTUM PROCESSOR 75/9/1/12 Pentlum Processor (75/9/1/12 MHz) Control Branch Target Bulter 64 Blt Data BUB 32 B Address BUB Floating Point Unit Control Data Control Figure 1. Pentium Processor Block Diagram The block diagram shows the two instruction pipe lines, the "u" pipe and the "v" pipe. The u pipe can execute all integer and floating point instructions. The v pipe can execute simple integer instructions and the FXCH floating point instructions. The separate caches are shown, the code cache and data cache. The data cache has two ports, one for each of the two pipes (the tags are triple ported to allow simultaneous inquire cycles). The data cache has a dedicated Translation Lookaside Buffer (TLB) to translate linear addresses to the physical addresses used by the data cache. The code cache, branch target buffer and prefetch buffers are responsible for getting raw instructions into the execution units of the Pentium processor. nstructions are fetched from the code cache or from the external bus. Branch addresses are reo membered by the branch target buffer. The code cache TLB translates linear addresses to physical addresses used by the code cache. The decode unit decodes the prefetched instruc tions so the Pentium processors can execute the instruction. The control ROM contains the micro code which controls the sequence of operations that 5

6 PENTUM PROCESSOR 75/9/1/12 must be performed to implement the Pentium processor architecture. The control ROM unit has direct control over both pipelines. The Pentium processors contain a pipe lined floatingpoint unit that provides a significant floating-point performance advantage over previous generations of processors. The architectural features introduced in this chapter are more' fully described in the Pentium Family User's Manual. 1.2 Pentium Processor 75/9/1/12 n addition to the architecture described above for the Pentium processor family, the Pentium processor 75/9/1/12 has additional features which are described in this section. The Pentium processor 75/9/1/12 offers higher performance and higher operating frequencies than the Pentium processor 6/66. The 12-MHz version of the Pentium processor 75/9/1/12 offers core operation at 12 MHz, external bus interface at 6 MHz, and achieves an icomp index of 1, while the 1-MHz version of the Pentium processor 75/9/1/12 offers core operation at 1 MHz, external bus interface at 5 or 66 MHz, and achieves an icomp index of 815, while the 9-MHz version offers core operation at 9 MHz, external bus interface at 6 MHz, and achieves an icomp index of 735, and the Pentium processor 751 9/1/12 core operates at 75 MHz and the externalbus operates at 5 MHz. Symmetric dual processing in a system is supported with two Pentium processors 75/911/12. The, two processors appear to the system as a single Pentium processor 75/9/1/12. Operating systems with dual processing support properly schedule computing tasks between the two processors. This scheduling of tasks is transparent to software applications and the end-user. Logic built into the processors support a "glueless" interface for easy system design. Through a private bus, the two Pentium processors 75/9/1/12 arbitrate for the external bus and maintain cache coherency. Dual process- ng s supported in a system only if both processors are operating at identical core and bus frequencies. Within these restrictons, two processors of different stepplngs may operate togeth~ er n' a system. in this document, in order to distinguish between two Pentium processors. 75/9/1112 in dual processing mode, one CPU will be designated as the Primary processor with the other being the Dual processor. Note that this is a different concept than that of "master" and "checker" processors described above in the discussion on functional redundancy. Due to the advanced 3.3V SiCMOS process that it is produced on, the Pentium processor 75/9/11 12 dissipates less power than the Pentium processor 6/66. n addition to the SMM features described above, the Pentium processor 75/9/11 12 supports clock control. When the clock to the Pentium processor 75/9/1/12 is stopped, power dissipation is virtually eliminated. The combination of these improvements makes the Pentium processor 75/9/1/12 a good choice for energy-efficient desktop designs. Supporting an upgrade socket (Socket 5) in the system will provide end-user upgradability by the addition of a Future Pentium OverDrive processor. Typical applications will realize a 4%-7% performance increase by addition of a Future Pentium OverDrive processor. The Pentium processor 75/9/1/12 supports fractional bus operation. This allows the internal processor core to operate at high frequencies, while communicating with the external bus at lower frequencies. The external bus frequency operates at a selectable one-half or two-thirds fraction of the internal core frequency. The Pentium processor 75/911/12 contains an on-chip Advanced Programmable nterrupt Controller (APC). This APC implementation supports multiprocessor interrupt management (with symmetric interrupt distribution across all processors), multiple /O subsystem support, 8259A compatibility, and inter-processor interrupt supp'ort. 6

7 intel PENTUM PROCESSOR 75/9/1/12 2. PNOUT 2.1 Pinout and Pin Descriptions PENTUM PROCESSOR 75/9/1/12 PNOUT :r Z , AN AN YSS He A AU vee vee vee vee vee vee vee vee vee vee vee FLUSH. NC NC NC All! AD M A VSS VSS VSS VSS VSS VSS VSS VSS VSS YSS VSS YSS WJR. EADS ADse. All! AL AL YSS A3 A7 A1 All A14 A' All AD NC seyc BEll BE4 BEl. BEO' BUSCHC. HT' PWT NC AK AK All A2 A A A13 All A17 All ESET ell BEn DEli BU. BEll A2DY. HTt DC. AP AJ AJ YSS All A31 AO HLDA BREQ AH AH Al2 All lock. Y AG AG AF vce Al4 A27 ped S.,Acn vee - AF vss All peh' vss AE AE vee!w AU. APeH. PBREQ. vee AD AD vss NTH PBONTO iss Ae Ae vee RB NY PRDY PHT. vee AB AB vss Sill' HOLD iss AA AA vee 1GNNE NT WBlWTt PHTt vee vss PfU BOFF vss vee FReye. BF NA. BRDve. vee Y vss He BRDYt YSS W W vee He He KEN' EWBE. vee vss BTPeLK. AHOLD TOP SDE VEW vss u vee vss vee NV CAeHE. vee vss vee UO. vss s He P: BP vee vee He iss He P18P1 iss Q Q vee TRBTt eputyp FERR' PDBPD vee iss TS ERt iss vee Till TOO DP7 DS3 vee N iss Tel Dl2 Y iss vee PleD vee DD Dll vee l J vee D2 PleDD Dli Dl7 vee YSS DO D. vss YSS PleeL Dli iss G vee 1 3 OS3 Dli vee D4 D& Opt 61 DP vee 1 7 D Oil Dl4 E e D. DD DP DZ 21 Ol 1. D. Ol DP NC DD iss iss VSS YSS iss iss iss VBB iss vss iss vss 43 NC A He on D D22 vee vee vee vee vee vee vee vee vee vee vee vee 41 NC OPe D Oil DP 11 Oil D2 2. DG DPS DS D3 27 D D zz Figure 2. Pentium Processor 75/9/1/12 Pinout (Top Side View) 7

8 PENTUM PROCESSOR 75/9/1/ , l' D AN NC NC NC FLUSH. vee vee vcc vee vec YeC vce vcc vec vcc vec AO All AD~e. E3s. w'aw v?s v?s v?s v~s 3& v?s ~ v?s v~ v?s 3& & AL' NC PWT HTU, BUCHK BEO BEll BE4. BEll CYC Ne Ala A. Al& A14 All A11 AK AP DC. HTt A2OM. lev au. BEll BE7. elk E8U AU A17 A15 A13 A AJ BREa LDA ADS AH vaa Locn AG vee sullcn PCD AF A AS A He A A3 A7 A A2t A. All Ali... All AG A27 Al4 VCC o AP VBS PCHK A21 Y88 AE o AE vce PBREQ, APCHK Al3... VCC AD o AD VBS PBGNTt HTR YSS AC o AC vec PHT. PROf NUl RB YCC AD o AD VBS HOLD SMt Y88 AA o AA VCC PHTt WBNT. NT ONNE yee ZOO o VS DOFF. 'E V88 f vce BROYc, NA' BF FRClle. yee o o VBS BRDY Ne Y88 WOO o W VCC EWDE KENt He He YCC o o v srpclkt Y88 U vn AHOLD PN SDE VEW vce CAeHE NY vee V88 YCC o o YSS ~O YCC V88 o vee BP PJ He He VCC o o R vn P1BP NC. V88 a o Q vee PMOBPO FERR' TRSTt CPUTYP VCC o o VB EARl T118 Y88 N vec 13 P7 TOO TD VCC o VS OU TCK Y88 L o L yee &1 1 vee PlCO VCC o o YSS OSt DO Y88 J vee &7 58 PlCOO 1 vee o H VBS DS PlceLK Y88 G o Q vcc 55 D yce o DP D51 OPi D5 114 E o DU Oil vce OSO Dn D44 4 ~ ~ ~ w ~ ~ ~ ~ w o ~ ~ ~ DO ~ CO e ~ ~ ffi ~ m ~ ~ ~ ~ w ~ ~ ~ m m ~ ~ 1 ~C o?3 & v~ & & v'i. &,& & vi v'is,& ~ : DY. ~ OY B A ~C ~1 v~e v~e v~e v~c v~e v~c v~c v?c v?c v~c,?e v?e o?2 D?' ~5 ~ A , l' U 2 Z n Figure 3. Pentium Processor 75/9/1/12 (Pin Side View) Y88 Y88 Y AN All AL A AJ AH 8

9 PENTUM PROCESSOR 75/9/1/ PN CROSS REFERENCE TABLE FOR PENTUM PROCESSOR 75/9/1/12 Table 1. Pin Cross Reference by Pin Name Address A3 AL35 A9 AK3 A15 AK26 A21 AF34 A27 AG33 A4 AM34 A1 AN31 A16 AL25 A22 AH36 A28 AK36 A5 AK32 A11 AL31 A17 AK24 A23 AE33 A29 AK34 A6 AN33 A12 AL29 A1B AL23 A24 AG35 A3 AM36 A7 AL33 A13 AK2B A19 AK22 A25 AJ35 A31 AJ33 A8 AM32 A14 AL27 A2 AL21 A26 AH34 Data K34 13 B E3 1 G35 14 C33 27 C G5 2 J35 15 A35 2B A5 54 E1 3 G33 16 B32 29 C19 42 E9 55 G3 4 F36 17 C B4 56 H4 5 F34 1B A33 31 C J3 6 E B 32 C15 45 C5 5B J5 7 E33 2 B E7 59 K C29 34 C13 47 C3 6 L5 9 C37 22 A B 4 61 L3 1 C D36 C11 49 E5 62 M4 11 B36 24 C N C23 3B C9 51 F4 9

10 PENTUM PROCESSOR 75/9/1/12 Table 1. Pin Cross Reference by Pin Name (Contd.) Control A2M# AK8 BRDYC# YO;3 FLUSH # ANO? PEN# Z34 ADS# AJ5 BREO AJ1 FRCMC# Y35 PMO/BPO 3 ADSC# AM2 BUSCHK# ALO? HT# AK6 PM1/BP1 R4 AHOLD V4 CACHE# U3 HTM# AL5 PRDY AC5 AP AK2 CPUTYP 35 HLDA AJ3 PWT AL3 APCHK# AE5 D/C# AK4 HOLD AB4 RS# AC35 BEO# AL9 D/P# AE35 ERR# P4 RESET AK2 BE1# AK1 DPO 36 GNNE# AA35 SCYC AL17 BE2# AL11 DP1 3 NT AA33 SM# AB34 BE3# AK12 DP2 C25 NTR/LNTO AD34 SMACT# AG3 BE4# AL13 DP3 18 NV U5 TCK M34 BE5# AK14 DP4 CO? KEN# W5 TO N35 BE6# AL15 DP5 F6 LOCK# AH4 TOO N33 BE?# AK16 DP6 F2 M/O# T4 TMS P34 BOFF# Z4 DP? N5 NA# Y5 TRST# 33 BP2 S3 EADS# AM4 NM/LlNT1 AC33 W/R# AM6 BP3 S5 EWBE# W3 PCD AG5 WB/WT# AA5 BRDY# X4 FERR# 5 PCHK# AF4 APC Clock Control Dual Processor Private nterface PCCLK H34 CLK AK18 PBGNT# AD4 PCDO J33 [BF] Y33 PBREO# AE3 [DPEN#] STPCLK# V34 PHT# AA3 PCD1 L35 PHTM# AC3 [APCEN] 1

11 PENTUM PROCESSOR 75/9/1/12 Table 1. Pin Cross Reference by Pin Name (Contd.) Vee A7 A19 E37 L33 51 W1 AC1 AN9 AN21 A9 A21 G1 L W37 AC37 AN11 AN23 A11 A23 G37 N1 T34 V1 AE1 AN13 AN25 A13 A25 J1 N37 U1 V37 AE37 AN15 AN27 A15 A27 J37 Q1 U33 AA1 AG1 AN17 AN29 A17 A29 L1 Q37 U37 AA37 AG37 AN19 Vss M2 U35 A836 AM8 AM M36 V2 AD2 AM1 AM P2 V36 AD36 AM12 AM P36 X2 AF2 AM14 AM3 814 H2 R2 X36 AF36 AM16 AN H36 R36 Z2 AH2 AM K2 T2 Z36 AJ37 AM2 82 K36 T36 A82 AL37 AM22 A3 C1 535 W35 A37 R34 W33 X NCNC AL1 AN1 AN5 AL19 AN3 AN Design Notes For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to Vee. Unused active HGH inputs should be connected to GND. No Connect (NG) pins must remain unconnected. Connection of NC pins may result in component failure or incompatibility with processor steppings. 2.3 Quick Pin Reference This section gives a brief functional description of each of the pins. For a detailed description, see the "Hardware nterface" chapter in the Pentium t Family User's Manual, Volume 1. Note that all input pins must meet their AC/DC specifications to guarantee proper functional behavior. The # symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage. When a # symbol is not present after the signal name, the signalis active, or asserted at the high voltage level. The following pins exist on the Pentium processor 6/66 but have been removed from the Pentium processor 75/9/1/12: o 18T, U, V, 8TO-3 The following pins become /O pins when two Pentium processors 75/9/1/12 are operating in a dual processing environment: AD5#, CACHE#, HT#, HTM#, HLDA#, LOCK#, MO#, D/C#, W/R#, 5CVC 11

12 PENTUM PROCESSOR 75/9/1/12 Table 2. Quick Pin Reference Symbol Type' Name and Function A2M# When the address bit 2 mask pin is asserted, the Pentium processor 75/91 1/12 emulates the address wraparound at 1 Mbyte which occurs on the 886. When A2M# is asserted, the Pentium processor 75/9/1/12 masks physical address bit 2 (A2) before performing a lookup to the internal caches or driving a memory cycle on the bus. The effect of A2M # is undefined in protected mode. A2M# must be asserted only when the processor is in real mode. A2M# is internally masked by the Pentium processor 75/9/1/12 when configured as a Dual processor. A31-A3 11 As outputs, the address lines of the processor along with the byte enables define the physical area of memory or 11 accessed. The external system drives the inquire address to the processor on A31-A5. ADS# The address status indicates that a new valid bus cycle is currently being driven by the Pentium processor 75/9/1/12. ADSC# ADSC# is functionally identical to ADS #. AHOLD n response to the assertion of address hold, the Pentium processor 75/9/11 12 will stop driving the address lines (A31-A3), and AP in the next clock. The rest of the bus will remain active so data can be returned or driven for previously issued bus cycles. AP 11 Address parity is driven by the Pentium processor 75/9/1/12 with even parity information on all Pentium processor 75/9/1/12 generated cycles in the same clock that the address is driven. Even parity must be driven back to the Pentium processor 75/9/1/12 during inquire cycles on this pin in the same clock as EADS # to ensure that correct parity check status is indicated by the Pentium processor 75/9/1/12. APCHK# The address parity check status pin is asserted two clocks after EADS# is sampled active if the Pentium processor 75/9/1/12 has detected a parity error on the address bus during inquire cycles. APCHK # will remain active for one clock each time a parity error is detected (including during dual processing private snooping). [APCEN] Advanced Programmable nterrupt Controller Enable is a new pin that enables PCD1 or disables the on-chip APC interrupt controller. f sampled high at the falling edge of RESET, the APC is enabled. APCEN shares a pin with the Programmable nterrupt Controller Data 1 signal. BE7#-BE5# The byte enable pins are used to determine which bytes must be written to BE4#-BEO# 11 external memory, or which bytes were requested by the CPU for the current cycle. The byte enables are driven in the same clock as the address lines (A31-3). Unlike the Pentium processor 6/66, the lower 4-byte enables (BE3#-BEO#) are used on the Pentium processor 75/9/1/12 as APC D inputs and are sampled at RESET. After RESET, these behave exactly like the Pentium processor 6/66 byte enables. n dual processing mode, BE4# is used as an input during Flush cycles. 12

13 PENTUM PROCESSOR 75/9/1/12 Table 2. Quick Pin Reference (Contd.) Symbol Type' Name and Function [BF] Bus Frequency determines the bus-to-core frequency ratio. BF is sampled at RESET, and cannot be changed until another non-warm (1 ms) assertion of RESET. Additionally, BF must not change values while RESET is active. For proper operation of the Pentium processor 75/9/1/12 this pin should be strapped high or low. When BF is strapped to Vee, the processor will operate at a 2/3 bus/core frequency ratio. When BF is strapped to Vss, the processor will operate at a 1/2 bus/core frequency ratio. f BF is left floating, the Pentium processor 75/9/1/ 12 defaults to a 2/3 bus ratio. Note that core operation at either 75 MHz or 9 MHz does not allow 1/2 bus/core frequency, while core operation at 12 MHz does not allow 2/3 bus core frequency. BOFF# The backoff input is used to abort all outstanding bus cycles that have not yet completed. n response to BOFF #, the Pentium processor 75/9/1/12 will float all pins normally floated during bus hold in the next clock. The processor remains in bus hold until BOFF# is negated, at which time the Pentium processor 75/9/1/ 12 restarts the aborted bus cycle(s) in their entirety. BP[3:2] The breakpoint pins (BP3-) correspond to the debug registers, DR3-DRO. These PM/BP[1:] pins externally indicate a breakpoint match when the debug registers are programmed to test for breakpoint matches. BP1 and BPO are multiplexed with the performance monitoring pins (PM1 and PMO). The PB1 and PBO bits in the Debug Mode Control Register determine if the pins are configured as breakpoint or performance monitoring pins. The pins come out of RESET configured for performance monitoring. BRDY# The burst ready input indicates that the external system has presented valid data on the data pins in response to a read or that the external system has accepted the Pentium processor 75/9/1/12 data in response to a write request. This signal is sampled in the T2, T12 and T2P bus states. BRDYC# This signal has the same functionality as BRDY #. BREQ The bus request output indicates to the external system that the Pentium processor 75/9/1/12 has internally generated a bus request. This signal is always driven whether or not the Pentium processor 75/9/1/12 is driving its bus. BUSCHK# The bus check input allows the system to signal an unsuccessful completion of a bus cycle. f this pin is sampled active, the Pentium processor 75/9/1/12 will latch the address and control signals in the machine check registers. f, in addition, the MCE bit in CR4 is set, the Pentium processor 75/9/1/12. will vector to the machine check exception. CACHE# For Pentium processor 75/9/1 /12-initiated cycles the cache pin indicates internal cacheability of the cycle (if a read), and indicates a burst write back cycle (if a write). f this pin is driven inactive during a read cycle, the Pentium processor 75/ 9/1/12 will not cache the returned data, regardless of the state of the KEN # pin. This pin is also used to determine the cycle length (number of transfers in the cycle). 13

14 PENTUM PROCESSOR 75/9/1/12 Table 2. Quick Pin Reference (Contd.) Symbol Type- Name and Function ClK The clock input provides the fundamental timing for the Pentium processor 75/9/ 1/12. ts frequency is the operating frequency of the Pentium processor 75/9/ 1/12 external bus, and requires TTL levels. All external timing parameters except TD, TDO, TMS, TRST #, and PCDO-1 are specified with respect to the rising edge of ClK. NOTE: t is recommended that CLK begin toggling within 15 ms after Vee reaches its proper operating level. This recommendation is only to ensure long-term reliability of the device. CPUTYP CPU type distinguishes the Primary processor from the Dual processor. n a single processor environment, or when the Pentium processor 75/9/1/12 is acting as the Primary processor in a dual processing system, CPUTYP should be strapped to Vss. The Dual processor should have CPUTYP strapped to Vee. For the Future Pentium OverDrive processor, CPUTYP will be used to determine whether the bootup handshake protocol will be used (in a dual socket system) or not (hi a single socket system). D/C# The data/code output is one of the primary bus cycle definition pins. t is driven valid in the same clock as the ADS# signal is asserted. D/C# distinguishes between data and code or special cycles. D/P# The dual/primary processor indication. The Primary processor drives this pin low when it is driving the bus, otherwise it drives this pin high. D/P# is always driven. D/P# can be sampled for the current cycle with ADS# (like a status pin). This pin is defined only on the Primary processor. D63-DO 11 These are the 64 data lines for the processor. Lines D7 -DO define the least significant byte of the data bus; lines D63-D56 define the most significant byte of the data bus. When the CPU is driving the data lines, they are driven during the T2, T12, or T2P clocks for that cycle. During reads, the CPU samples the data bus when BRDY # is returned. DP7-DPO 11 These are the data parity pins for the processor. There is one for each byte of the data bus. They are driven by the Pentium processor 75/9/1/12 with even parity information on writes in the same clock as write data. Even parity information must be driven back to the Pentium processor 75/9/1/12 on these pins in the same clock as the data to ensure that the correct parity check status is indicated by the Pentium processor 75/9/1/12. DP7 applies to D63-56, DPO applies to D7-. [DPEN#] 11 Dual processing enable is an output of the Dual processor and an input of the PCDO Primary processor. The Dual processor drives DPEN # low to the Primary processor at RESET to indicate that the Primary processor should enable dual processor mode. DPEN # may be sampled by the system at the falling edge of RESET to determine if Socket 5 is occupied. DPEN # shares a pin with PCDO. EADS# This signal indicates that a valid external address has been driven onto the Pentium processor 75/9/1/12 address pins to be used for an inquire cycle. EWBE# The external write buffer empty input, when inactive (high), indicates that a write cycle is pending in the external system. When the Pentium processor 75/9/1/12 generates a write, and EWBE# is sampled inactive, the Pentium processor 75/9/ 1/12 will hold off all subsequent writes to all E- or M-state lines in the data cache until all write cycles have completed, as indicated by EWBE# being active. 14

15 PENTUM PROCESSOR 75/9/1/12 Table 2. Quick Pin Reference (Contd.) Symbol Type Name and Function FERR# The floating point error pin is driven active when an unmasked floating point error occurs. FERR # is similar to the ERROR # pin on the ntel387 math coprocessor. FERR # is included for compatibility with systems using DOS type floating point error reporting. FERR # is never driven active by the Dual processor. FLUSH# When asserted, the cache flush input forces the Pentium processor 75/9/1/12 to write back all modified lines in the data cache and invalidate its internal caches. A Flush Acknowledge special cycle will be generated by the Pentium processor 75/9/ 1/12 indicating completion of the write back and invalidation. f FLUSH # is sampled low when RESET transitions from high to low, tristate test mode is entered. f two Pentium processors 75/9/1/12 are operating in dual processing mode in a system and FLUSH # is asserted, the Dual processor will perform a flush first (without a flush acknowledge cycle), then the Primary processor will perform a flush followed by a flush acknowledge cycle. FRCMC# The functional redundancy checking master/checker mode input is used to determine whether the Pentium processor 75/9/1/12 is configured in master mode or checker mode. When configured as a master, the Pentium processor 75/9/ 1/12 drives its output pins as required by the bus protocol. When configured as a checker, the Pentium processor 75/9/1 /12 tristates all outputs (except ERR # and TOO) and samples the output pins. The configuration as a master/checker is set after RESET and may not be changed other than by a subsequent RESET. HT# The hit indication is driven to reflect the outcome of an inquire cycle. f an inquire cycle hits a valid line in either the Pentium processor 75/9/1/12 data or instruction cache, this pin is asserted two clocks after EADS# is sampled asserted. f the inquire cycle misses the Pentium processor 75/9/1/12 cache, this pin is negated two clocks after EADS#. This pin changes its value only as a result of an inquire cycle and retains its value between the cycles. HTM# The hit to a modified line output is driven to reflect the outcome of an inquire cycle. t is asserted after inquire cycles which resulted in a hit to a modified line in the data cache. t is used to inhibit another bus master from accessing the data until the line is completely written back. HLDA The bus hold acknowledge pin goes active in response to a hold request driven to the processor on the HOLD pin. t indicates that the Pentium processor 75/9/1/ 12 has floated most of the output pins and relinquished the bus to another local bus master. When leaving bus hold, HLDA will be driven inactive and the Pentium processor 75/9/1/12 will resume driving the bus. f the Pentium processor 75/ 9/1/12 has a bus cycle pending, it will be driven in the same clock that HLDA is de-asserted. 15

16 PENTUM PROCESSOR 75/9/1/12 intet~ Table 2. Quick Pin Reference (eontd.) Symbol Type Name and Function HOLD n response to the bus hold request, the Pentium processor 75/9/1/12 will float most of its output and input/output pins and assert HLDA after completing all outstanding bus cycles. The Pentium processor 75/9/1/12 will maintain its bus in this state until HOLD is de-asserted. HOLD is not recognized during LOCK cycles. The Pentium processor 75/9/1/12 will recognize HOLD during reset. ERR# The internal error pin is used to indicate two types of errors, internal parity errors and functional redundancy errors. f a parity error occurs on a read from an internal array, the Pentium processor 75/9/1/12 will assert the ERR# pin for one clock and then shutdown. f the Pentium processor 75/9/1/12 is configured as a checker and a mismatch occurs between the value sampled on the pins and the corresponding value computed internally, the Pentium processor 75/9/1/12 will assert ERR # two clocks after the mismatched value is returned. GNNE# This is the ignore numeric error input. This pin has no effect when the NE bit in CRO is set to 1. When the CRO.NE bit is, and the GNNE# pin is asserted, the Pentium processor 75/9/1 /12 will ignore any pending unmasked numeric exception and continue executing floating-point instructions for the entire duration that this pin is asserted. When the CRO.NE bit is, GNNE # is not asserted, a pending unmasked numeric exception exists (SW.ES = 1), and the floating point instruction is one of FNT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FEN, FDS, or FSETPM, the Pentium processor 75/9/1/12 will execute the instruction in spite of the pending exception. When the CRO.NE bit is, GNNE# is not asserted, a pending unmasked numeric exception exists (SW.ES = 1), and the floating-point instruction is one other than FNT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FEN, FDS, or FSETPM, the Pentium processor 75/9/1/12 will stop execution and wait for an external interrupt. GNNE# is internally masked when the Pentium processor 75/9/1/12 is configured as a Dual processor. NT The Pentium processor 75/9/1/12 nitialization input pin forces the Pentium processor 75/9/1/12 to begin execution in a known state. The processor state after NT is the same as the state after RESET except that the internal caches, write buffers, and floating point registers retain the values they had prior to NT. NT may NOT be used in lieu of RESET after power-up. f NT is sampled high when RESET transitions from high to low, the Pentium processor 75/9/1/12 will perform built-in self test prior to the start of program execution. NTR/UNTO An active maskable nterrupt input indicates that an external interrupt has been generated. f the F bit in the EFLAGS register is set, the Pentium processor 75/9/ 1/12 will generate two locked interrupt acknowledge bus cycles and vector to an interrupt handler after the current instruction execution is completed. NTR must remain active until the first interrupt acknowledge cycle is generated to assure that the interrupt is recognized. f the local APC is enabled, this pin becomes local nterrupt O. 16

17 PENTUM PROCESSOR 75/9/1/12 Table 2. Quick Pin Reference (Contd.) Symbol Type Name and Function NV The nvalidation input determines the final cache line state (5 or ) in case of an inquire cycle hit. t is sampled together with the address for the inquire cycle in the clock EAD5 # is sampled active. KEN# The cache enable pin is used to determine whether the current cycle is cacheable or not and is consequently used to determine cycle length. When the Pentium processor 75/9/1/12 generates a cycle that can be cached (CACHE # asserted) and KEN # is active, the cycle will be transformed into a burst line fill cycle. LlNTO/NTR f the APC is enabled, this pin is local nterrupt o. f the APC is disabled, this pin is interrupt. LlNT1/NM f the APC is enabled, this pin is local nterrupt 1. f the APC is disabled, this pin is non-maskable interrupt. LOCK # The bus lock pin indicates that the current bus cycle is locked. The Pentium processor 75/9/1/12 will not allow a bus hold when LOCK# is asserted (but AHOLD and BOFF # are allowed). LOCK # goes active in the first clock of the first locked bus cycle and goes inactive after the BRDY # is returned for the last locked bus cycle. LOCK # is guaranteed to be de asserted for at least one clock between back to-back locked cycles. M/O# The memory/input-output is one f the primary bus cycle definition pins. t is driven valid in the same clock as the AD5# signal is asserted. M/O# distinguishes between memory and 1/ cycles. NA# An active next address input indicates that the external memory system is ready to accept a new bus cycle although all data transfers for the current cycle have not yet completed. The Pentium processor 75/9/1/12 will issue AD5# for a pending cycle two clocks after NA# is asserted. The Pentium processor 75/9/1/12 supports up to 2 outstanding bus cycles. NM/LlNT1 The non-maskable interrupt request signal indicates that an external nonmaskable interrupt has been generated. f the local APC is enabled, this pin becomes local interrupt 1. PBGNT# 1/ Private bus grant is the grant line that is used when two Pentium processors 751 9/1/12 are configured in dual processing mode, in order to perform private bus arbitration. PBGNT# should be left unconnected if only one Pentium processor 751 9/1/12 exists in a system. PBREQ# 1/ Private bus request is the request line that is used when two Pentium processors 75/9/1/12 are configured in dual processing mode, in order to perform private bus arbitration. PBREQ# should be left unconnected if only one Pentium processor 75/9/1/12 exists in a system. PCD The page cache disable pin reflects the state of the PCD bit in CR3, the Page Directory Entry, or the Page Table Entry. The purpose of PCD is to provide an external cacheability indication on a page by page basis. 17

18 PENTUM PROCESSOR 75/9/1/12 Table 2. Quick Pin Reference (Contd.) Symbol Type' Name and Function PCHK# The parity check output indicates the result of a parity check on a data read. t is driven with parity status two clocks after BRDY # is returned. PCHK # remains low one clock for each clock in which a parity error was detected. Parity is checked only for the bytes on which valid data is returned., When two Pentium processors 75/9/1/12 are operating in dual processing mode, PCHK # may be driven two or three clocks after BRDY # is returned. PEN# The parity enable input (along with CR4.MCE) determines whether a machine check exception will be taken as a result of a data parity error on a read cycle. f this pin is sampled active in the clock a data parity error is detected, the Pentium processor 75/9/1/12 will latch the address and control signals of the cycle with the parity error in the machine check registers. f, in addition, the machine check enable bit in CR4 is set to "1", the Pentium processor 75/9/1/12 will vector to the machine check exception before the beginning of the next instruction. PHT# /O Private hit is a hit indication used when two Pentium processors 75/9/1/12 are configured in dual processing mode, in order to maintain local cache coherency. PHT# should be left unconnected if only one Pentium processor 75/9/1/12 exists in a system. PHTM# /O Private modified hit is a hit indication used when two Pentium processors 75/9/ 1/12 are configured in dual processing mode, in order to maintain local cache coherency. PHTM# should be left unconnected if only one Pentium processor 75/ 9/1/12 exists in a system. PCCLK The APC interrupt controller serial data bus clock is driven into the programmable interrupt controller clock input of the Pentium processor 75/9/1/12. PCDO 1 /O Programmable interrupt controller data lines -1 of the Pentium processor 75/ [DPEN#] 9/1/12 comprise the data portion of the APC 3 wire bus. They are open drain [APCEN] outputs that require external pull-up resistors. These signals share pins with OPEN # and APCEN. PM/BP[1:] These pins function as part of the performance monitoring feature. The breakpoint 1 pins are multiplexed with the performance monitoring 1- pins. The PB1 and PBO bits in the Debug Mode Control Register determine if the pins are configured as breakpoint or performance monitoring pins. The pins come out of RESET configured for performance monitoring. PRDY The probe ready output pin indicates that the processor has stopped normal execution in response to the R/S# pin going active, or Probe Mode being entered. PWT The page write through pin reflects the state of the PWT bit in CR3, the page directory entry, or the page table entry. The PWT pin is used to provide an external write back indication on a page-by-page basis. 18

19 PENTUM PROCESSOR 75/9/1/12 Table 2. Quick Pin Reference (Contd.) Symbol Type' Name and Function R/S# The run/stop input is an asynchronous, edge-sensitive interrupt used to stop the normal execution of the processor and place it into an idle state. A high to low transition on the R/S# pin will interrupt the processor and cause it to stop execution at the next instruction boundary. RESET RESET forces the Pentium processor 75/9/1/12 to begin execution at a known state. All the Pentium processor 75/9/1/12 internal caches will be invalidated upon the RESET. Modified lines in the data cache are not written back. FLUSH #, FRCMC# and NT are sampled when RESET transitions from high to low to determine if tristate test mode or checker mode will be entered, or if BST will be run. SCYC The split cycle output is asserted during misaligned LOCKed transfers to indicate that more than two cycles will be locked together. This signal is defined for locked cycles only. t is undefined for cycles which are not locked. SM# The system management interrupt causes a system management interrupt request to be latched internally. When the latched SM # is recognized on an instruction boundary, the processor enters System Management Mode. SMACT# An active system management interrupt active output indicates that the processor is operating in System Management Mode. STPCLK# Assertion of the stop clock input signifies a request to stop the internal clock of the Pentium processor 75/9/1/12 thereby causing the core to consume less power. When the CPU recognizes STPCLK #, the processor will stop execution on the next instruction boundary, unless superseded by a higher priority interrupt, and generate a stop grant acknowledge cycle. When STPCLK # is asserted, the Pentium processor 75/9/1/12 will still respond to interprocessor and external snoop requests. TCK The testability clock input provides the clocking function for the Pentium processor 75/9/1/12 boundary scan in accordance with the EEE Boundary Scan interface (Standard ). t is used to clock state information and data into and out of the Pentium processor 75/9/1/12 during boundary scan. 19

20 PENTUM PROCESSOR 75/9/1/12 Table 2. Quick Pin Reference (Contd.) Symbol Type" Name and Function TO The test data input is a serial input for the test logic. TAP instructions and data are shifted into the Pentium processor 75/9/1/12 on the TO pin on the rising edge of TCK when the TAP controller is in an appropriate state. TOO The test data output is a serial output of the test logic. TAP instructions and data are shifted out of the Pentium processor 75/9/1/12 on the TOO pin on TCK's falling edge when the TAP controller is in an appropriate state. TMS The value of the test mode select input signal sampled at the rising edge of TCK controls the sequence of TAP controller state changes. TRST# When asserted, the test reset input allows the TAP controller to be asynchronously initialized. Vcc The Pentium processor 75/9/1/12 has V power inputs. VSS The Pentium processor 75/9/1/12 has 53 ground inputs. W/R# Write/read is one of the primary bus cycle definition pins. t is driven valid in the same clock as the AOS# signal is asserted. W/R# distinguishes between write and read cycles. WB/WT# The write back/write through input allows a data cache line to be defined as write back or write through on a line-by-line basis. As a result, it determines whether a cache line is initially in the S or E state in the data cache... The pins are classified as nput or Output based on their function n Master Mode. See the Functional Redundancy Checking section in the "Error Detection" chapter of the Pentium Family User's Manual, Vol. 1, for further information. 2

21 PENTUM PROCESSOR 75/9/1/ Pin Reference Tables Table 3. Output Pins Name Active Level When Floated ADS#* Low Bus Hold, BOFF # ADSC# Low Bus Hold, BOFF # APCHK# Low BE7#-BE5# Low Bus Hold, BOFF # BREQ High CACHE#* Low Bus Hold, BOFF # D/P#** FERR#*' HT#* HTM#* HLDA* ERR# n/a Low Low Low High Low LOCK#* Low Bus Hold, BOFF # M/O#*, D/C#*, W/R#* n/a Bus Hold, BOFF# PCHK# BP3-2, PM1 BP1, PMO/BPO PRDY Low High High PWT, PCD High Bus Hold, BOFF # SCYC' High Bus Hold, BOFF # SMACT# Low TOO n/a All states except Shift-DR and Shift-R NOTES: All output and input/output pins are floated during tristate test mode and checker mode (except ERR#). These are /O signals when two Pentium@> processors 75/9/1/12 are operating in dual processing mode. These signals are undefined when the CPU is configured as a Dual Processor. 21

22 PENTUM PROCESSOR 75/9/1/12 Table 4. nput Pins Name Active Level Synchronousl Asynchronous nternal Resistor Qualified A2M#* Low Asynchronous AHOLD High Synchronous BF High Synchronous/RESET Pullup BOFF# Low Synchronous BRDY# Low Synchronous Bus State T2, T12, T2P BRDYC# Low Synchronous Pullup Bus State T2, T12, T2P BUSCHK# Low Synchronous Pullup BRDY# CLK n/a CPUTYP High Synchronous/RESET EADS# Low Synchronous EWBE# Low Synchronous BRDY# FLUSH # Low Asynchronous FRCMC# Low Asynchronous HOLD High Synchronous GNNE#* Low Asynchronous NT High Asynchronous NTR High Asynchronous NV High Synchronous EADS# KEN # Low Synchronous First BRDY#/NA# NA# Low Synchronous Bus State T2,TD,T2P NM High Asynchronous PEN# Low Synchronous BRDY# PCCLK High Asynchronous Pull up RS# n/a Asynchronous Pullup RESET High Asynchronous SM# Low Asynchronous Pullup STPCLK# Low Asynchronous Pullup TCK n/a Pullup TD n/a Synchronous/TCK Pullup TCK TMS n/a Synchronous/TCK Pullup TCK TRST# Low Asynchronous Pullup WB/WT# n/a Synchronous First BRDY # NA# Undefined when the CPU S configured as a Dual processor. 22

23 PENTUM PROCESSOR 75/9/1/12 Name Table 5. nput/output Pins Active Qualified nternal When Floated Level (when an input) Resistor A31-A3 nfa Address Hold, Bus Hold, BOFF # EADS# AP nfa Address Hold, Bus Hold, BOFF # EADS# BE4#-BEO# Low Address Hold, Bus Hold, BOFF # RESET Pulldown* D63-DO nfa Bus Hold, BOFF # BRDY# DP7-DPO nfa Bus Hold, BOFF # BRDY# PCDO[DPEN #] PCD1 [APCEN] Pullup Pulldown NOTES: All output and input/output pins are floated during tristate test mode (except TDO) and checker mode (except ERR# and TDO). BE3#-BEO# have Pulldowns during RESET only. Table 6. nter-processor /O Pins Name Active Level nternal Resistor PHT# Low Pullup PHTM# Low Pullup PBGNT# Low Pullup PBREQ# Low Pullup NOTE: For proper inter-processor operation, the system cannot load these signals. 23

24 PENTUM PROCESSOR 75/9/1/ Pin Grouping According to Function Table 7 organizes the pins with respect to their function. Table 7. Pin Functional Grouping Function Pins Clock ClK nitialization RESET,NT Address Bus A31-A3, BE7#-BEO# Address Mask A2M# Data Bus D63-DO Address Parity AP,APCHK# APC Support PCClK, PCDO-1 Data Parity DP7-DPO, PCHK#, PEN# nternal Parity Error ERR# System Error BUSCHK# Bus Cycle Definition MO#, D/C#, W/R#, CACHE#, SCVC, lock# Bus Control ADS#,ADSC#,BRDV#,BRDVC#,NA# Page Cacheability PCD,PWT Cache Control KEN #, WB/WT # Cache Snooping/Consistency AHOlD, EADS#, HT#, HTM#, NV Cache Flush FlUSH# Write Ordering EWBE# Bus Arbitration BOFF#,BREQ,HOlD,HlDA Dual Processing Private Bus Control PBGNT#, PBREQ#, PHT#, PHTM# nterrupts NTR,NM Floating Point Error Reporting FERR#,GNNE# System Management Mode SM#, SMACT# Functional Redundancy Checking FRCMC# (ERR#) TAP Port TCK, TMS, TD, TOO, TRST # Breakpoint/Performance Monitoring PMO/BPO, PM1/BP1, BP3-2 Power Management STPClK# Miscellaneous Dual Processing CPUTYP, D/P# Probe Mode RS#, PRDV 24

25 PENTUM PROCESSOR 75/9/1/12 3. ELECTRCAL SPECFCATONS This section describes the electrical differences between the Pentium processor 6/66 and the Pentium processor 75/9/1/12 and the DC and AC specifications. 3.1 Electrical Differences Between Pentium Processor 75/9/11 12 and Pentium Processor 6/66 Pentium Processor Difference in 6/66 Electrical Pentium Processor Characteristic 75/9/1/12 5V Power Supply 5V TTL nputs/outputs 3.3V Power Supply 3.3V nputs/outputs Pentium Processor Pentium Processor 6/66 Buffer Models 75/9/1/12 Buffer Models.. The upgrade socket specifies two 5V nputs (section 6..).. The sections that follow will briefly point out some ways to design with these electrical differences V POWER SUPPLY The Pentium processor 75/9/1/12 has all Vee 3.3V inputs. By connecting all Pentium processor 6/66 Vee inputs to a common and dedicated power plane, that plane can be converted to 3.3V for the Pentium processor 75/9/1/12. The ClK and PCClK inputs can tolerate a 5V input signal. This allows the Pentium processor 75/9/ 1/12 to use 5V or 3.3V clock drivers V NPUTS AND OUTPUTS The inputs and outputs of the Pentium processor 75/9/1/12 are 3.3V JEDEC standard levels. Both inputs and outputs are also TTL-compatible, although the inputs cannot tolerate voltage swings above the 3.3V VN max. For Pentium processor 75/9/1/12 outputs, if the Pentium processor 6/66 system support components use TTL-compatible inputs, they will interface to the Pentium processor 75/9/1/12 without extra logic. This is because the Pentium processor 75/9/1/12 drives according to the 5V TTL specification (but not beyond 3.3V). For Pentium processor 75/9/1/12 inputs, the voltage must not exceed the 3.3V VH3 maximum specification. System support components can consist of 3.3V devices or open-collector devices. 3.3V support components may interface to the Pentium processor 6/66 since they typically meet 5V TTL specifications. n an open-collector configuration, the external resistor may be biased with the CPU Vee; as the CPU's Vee changes from 5V to 3.3V, so does this signal's maximum drive. The ClK and PCClK inputs of the Pentium processor 75/9/1/12 are 5V tolerant, so they are electrically identical to the Pentium processor 6/66 clock input. This allows a Pentium processor 6/66 clock driver to drive the Pentium processor 75/9/ 1/12. All pins, other than the ClK and PCClK inputs, are 3.3V-only. f an 8259A interrupt controller is used, for example, the system must provide level converters between the 8259A and the Pentium processor 75/9/1/ V PENTUM PROCESSOR 75/9/11 12 BUFFER MODELS The structure of the buffer models of the Pentium processor 75/9/1/12 are the same as those of the Pentium processor 6/66, but the values of the components change since the Pentium processor 75/9/1/12 buffers are 3.3V buffers on a different process. Despite this difference, the simulation results of Pentium processor 75/9/1/12 buffers and Pentium processor 6/66 buffers look nearly identical. Since the OpF AC specifications of the Pentium processor 75/9/1/12 are derived from the Pentium processor 6/66 specifications, the system should see little difference between the AC behavior of the Pentium processor 75/9/1/12 and the Pentium processor 6/66. To meet specifications, simulate the AC timings with Pentium processor 75/9/1/12 buffer models. Pay special attention to the new signal quality restrictions imposed by 3.3V buffers. 25

26 PENTUM PROCESSOR 75/9/1/ Absolute Maximum Ratings The values listed below are stress ratings only. Functional operation at the maximums is not implied or guaranteed. Functional operating conditions are given in the AC and DC specification tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the Pentium processor 75/9/1/12 contains protective circuitry to resist damage from static electric discharge, always take precautions to avoid high static voltages or electric fields. Case temperature under bias C to 11 C Storage temperature C to 15 C 3V Supply voltage with respect to Vss V to + 4.6V 3V Only Buffer DC nput Voltage -.5V to VCC +.5; not to exceed VCC3 max(2) 5V Safe Buffer DC nput Voltage V to 6.5V(1,3) NOTES: 1. Applies to ClK and PCClK. 2. Applies to all Pentium processor 75/9/11 12 inputs except ClK and PCClK. 3. See overshoot/undershoot transient spec.,. WARNNG: Stressing the device beyond the '~bsolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. 3.3 DC Specifications Tables 8,9, and 1 list the DC specifications which apply to the Pentium processor 75/9/1/12. The Pentium processor 75/9/1/12 is a 3.3V part internally. The ClK and PCClK inputs may be a 3.3V or 5V inputs. Since the 3.3V (5V-safe) input levels defined in Table 9 are the same as the 5V TTL levels, the ClK and PCClK inputs are compatible with existing 5V clock driverll. The power dissipation specification in Table 11 is provided for design of thermal solutions during operation in a sustained maximum level. This is the worst case power the device would dissipate in a system. This number is used for design of a thermal solution for the device. Table V DC Preliminary Specifications TCASE = to 7 C; VCC = 3.3V +5% Symbol Parameter Min Max Unit Notes VL3 nput low Voltage V TTL level(3) VH3 nput High Voltage 2. Vcc+.3 V TTL level(3) VOl3 Output low Voltage.4 V TTL level(1, 3) VOH3 Output High Voltage 2.4 V TTL level(2, 3) CC3 Power Supply Current NOTES: 1. Parameter measured at 4 mao 2. Parameter measured at 3 mao V TTL le\lels apply to all signals except ClK and PCClK. 4. This value should be used for power supply design. t was determined using a worst case instruction mix and Vee + 5%. Power supply transient response and decoupling capacitors must be sufficient to handle the instantaneous current changes occurring during transitions from stop clock to full active modes. For more information, refer to section

27 PENTUM PROCESSOR 75/9/1/12 Table V (5V-Safe) DC Specifications Symbol Parameter Min Max Unit Notes Vl5 nput low Voltage V Tllevel(1) VH5 nput High Voltage V TL level(1) NOTES: 1. Applies to ClK and PCClK only. Table 1. nput and Output Characteristics Symbol Parameter Min Max Unit Notes CN nput Capacitance 15 pf 4 Co Output Capacitance 2 pf 4 CliO 1/ Capacitance 25 pf 4 CClK ClK nput Capacitance 15 pf 4 CTN Test nput Capacitance 15 pf 4 CTOUT Test Output Capacitance 2 pf 4 CTCK Test Clock Capacitance 15 pf 4 nput leakage Current ±15 p.a o < VN < VCC3(1) LO Output leakage Current ±15 p.a o < VN < VCC3(1) H nput leakage Current 2 p.a VN = 2.4V(3) nput leakage Current -4 p.a VN =.4V(2) NOTES: 1. This parameter is for input without pullup or pulldown. 2. This parameter is for input with pull up. 3. This parameter is for input with pulldown. 4. Guaranteed by design. 27

28 PENTUM PROCESSOR 75/9/1/12 Table 11. Preliminary Power Dissipation Requirements for Thermal Solution Design Parameter Typical(1) Max(2) Unit Notes Active Power Dissipation B.O Stop Grant and Auto Halt 1.47 Powerdown Power Dissipation Stop Clock Power Dissipation.2 <.5 Watts 4 NOTES: 1. This is the typical power dissipation in a system. This value was the average value measured in a system using a typical device at Vee = 3.3V running typical applications. This value is highly dependent upon the specific system configuration. 2. Systems must be designed to thermally dissipate the maximum active power dissipation. t is determined using worst case instruction mix with Vee = 3.3V and also takes into account the thermal time constants of the package. 3. Stop Grant! Auto Halt Powerdown Power Dissipation is determined by asserting the STPClK # pin or executing the HALT instruction. 4. Stop Clock Power Dissipation is determined by asserting the STPClK# pin and then removing the external ClK input. 3.4 AC Specifications The AC specifications of the Pentium processor 751 9/1/12 consist of setup times, hold times, and valid delays at pf PRVATE BUS When two Pentium processors 75/911/12 are operating in dual processor mode, a "private bus" exists to arbitrate for the CPU bus and maintain local cache coherency. The private bus consists of two pinout changes: 1. Five piris are added: PBREQ#, PBGNT#, PHT#, PHTM#, D/P#. 2. Ten output pins become 1/ pins: ADS#, D/C#, W/R#, MO#, CACHE#, LOCK#, HT#, HTM#, HLDA, SCVC. The new pins are given AC specifications of valid delays at pf, setup times, and hold times. Simulate with these parameters and their respective 1/ buffer models to guarantee that proper timings are met. The AC specification gives input setup and hold times for the ten signals that become 1/ pins. These setup and hold times must only be met when a dual processor is present in the system POWER AND GROUND For clean on-chip power distribution, the Pentium processor 75/9/1/12 has 53 VCC (power) and 53 VSS (ground) inputs. Power and ground connections must be made to all external Vcc and Vss pins of the Pentium processor 75/9/1/12. On the circuit board all VCC pins must be connected to a 3.3V VCC plane. All VSS pins must be connected to a VSS plane DECOUPLNG RECOMMENDATONS Liberal decoupling capacitance should be placed near the Pentium processor 75/9/1/12. The Pentium processor 75/9/1/12 driving its large address and data buses at high frequencies can cause transient power surges, particularly when driving large capacitive loads. Low inductance capacitors and interconnects are recommended for best high frequency electrical performance. nductance can be reduced by shortening circuit board traces between the Pentium processor 75/9/1/12 and decoupling capacitors as much as possible. These capacitors should be evenly distributed around each component on the 3.3V plane. Capacitor values should be chosen to ensure they eliminate both low and high frequency noise components. 2B

29 PENTUM PROCESSOR 75/9/1/12 For the Pentium processor 75/9/1/12, the power consumption can transition from a low level of power to a much higher level (or high to low power) very rapidly. A typical example would be entering or exiting the Stop Grant state. Another example would be executing a HALT instruction, causing the Pentium processor 75/9/1/12 to enter the Auto HALT Powerdown state, or transitioning from HALT to the Normal state. All of these examples may cause abrupt changes in the power being consumed by the Pentium processor 75/9/1/12. Note that the Auto HALT Powerdown feature is always enabled even when other power management features are not implemented. Bulk storage capacitors with a low ESR (Effective Series Resistance) in the 1 to 1 pj range are required to maintain a regulated supply voltage during the interval between the time the current load changes and the point that the regulated power supply output can react to the change in load. n order to reduce the ESR, it may be necessary to place several bulk storage capacitors in parallel. These capacitors should be placed near the Pentium processor 75/9/1/12 (on the 3.3V plane) to ensure that the supply voltage stays within specified limits during changes in the supply current during operation CONNECTON SPECFCATONS All NC and NC pins must remain unconnected. For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to Vee. Unused active high inputs should be connected to ground AC TMNG TABLES AC Timing Table for a 5-MHz Bus The AC specifications given in Tables 12 and 13 consist of output delays, input setup requirements and input hold requirements for a 5-MHz external bus. All AC specifications (with the exception of those for the TAP signals and APC signals) are relative to the rising edge of the ClK input. All timings are referenced to 1.5V for both "" and "1" logic levels unless otherwise specified. Within the sampling window, a synchronous input must be stable for correct Pentium processor 75/9/11 12 operation. Table 12. Pentium Processor 61\75, 815\ 1 AC Specifications for 5-MHz Bus Operation < Vee < 3.465V, TeASE = to 7 C, CL = pf Symbol Parameter Min Max Unit Figure Notes Frequency MHz Max Core Freq = 1 t1a ClK Period ns 4 t1b ClK Period Stability ±25 ps 1,25 t2 ClK High Time 4. ns t3 ClKlowTime 4. ns 4 ClKFaliTime ns 4 (2.V -.8V), (1,5) t5 ClK Rise Time ns 4 (.8V-2.V), (1,5) t6a ADS#,ADSC#, PWT, PCD, ns 5 BEO-7#, M/O#, D/C#, CACHE#, SCYC, W/R# Valid Delay 29

30 PENTUM PROCESSOR 75/9/1/12 Table 12. Pentium Processor 61\75,815\ 1 AC Specifications for 5-MHz Bus Operation (Contd.) < Vee < 3.465V, TeASE = to 7 C, CL = pf Symbol Parameter Min Max Unit Figure Notes tab AP Valid Delay ns 5 tae A3-A31, LOCK# Valid Delay ns 5 t7 ADS#, ADSC#, AP, A3-A31, PWT, PCD, 1. ns 6 1 BEO-7#, M/O#, D/C#, W/R#, CACHE#, SCYC, LOCK # Float Delay ta APCHK#, ERR#, FERR#, PCHK# Valid ns 5 4 Delay t9a BREQ, HLDA, SMACT # Valid Delay ns 5 4 ~ t1a HT# Valid Delay ns 5 t1b HTM# Valid Delay ns 5 t11a PMO-1, BPO-3 Valid Delay ns 5 t11b PRDY Valid Delay ns 5 t12-63, DPO-7 Write Data Valid Delay ns 5 t13-63, DPO-3 Write Data Float Delay 1. ns 6 1 t14 A5-A31 Setup Time 6.5 ns 7 26 t15 A5-A31 Hold Time 1. ns 7 t16a NV, AP Setup Time 5. ns 7 t16b EADS# Setup Time 6. ns 7 t17 EADS#, NV, AP Hold Time 1. ns 7 t18a KEN # Setup Time 5. ns 7 t18b NA #, WB/WT # Setup Time 4.5 ns 7 t19 KEN #, WB/WT #, NA # Hold Time 1. ns 7 t2 BRDY#, BRDYC# Setup Time 5. ns 7 t21 BRDY #, BRDYC# Hold Time 1. ns 7 t22 BOFF # Setup Time 5.5 ns 7 t22a AHOLD Setup Time 6. ns 7 t23 AHOLD, BOFF # Hold Time 1. ns 7 3

31 PENTUM PROCESSOR 75/9/1/12 Table 12. Pentium Processor 61\ 75, 815\ 1 AC Specifications for 5-MHz Bus Operation (Contd.) < Vee < 3.465V, TeASE = to 7 C, CL = pf Symbol Parameter Min Max Unit Figure Notes t24 BUSCHK#, EWBE#, HOLD, PEN# Setup 5. ns 7 Time t25 BUSCHK #, EWBE #, PEN # Hold Time 1. ns 7 t25a HOLD Hold Time 1.5 ns 7 t26 A2M#, NTR, STPClK# Setup Time 5. ns 7 12,16 t27 A2M#, NTR, STPClK# Hold Time 1. ns 7 13 t28 NT, FlUSH#, NM, SM#,GNNE# Setup 5. ns 7 12,16,17 Time t29 NT, FlUSH#, NM, SM#,GNNE# Hold 1. ns 7 13 Time t3 NT, FlUSH#, NM, SM#,GNNE# Pulse 2. ClKs 7 15,17 Width, Async t31 RS# Setup Time 5. ns 7 12,16,17 t32 RS# Hold Time 1. ns 7 13 t33 RS# pulse Width, Async. 2. ClKs 7 15,17 t34-63, DPO-7 Read Data Setup Time 3.8 ns 7 t35-63, DPO-7 Read Data Hold Time 2. ns 7 t36 RESET Setup Time 5. ns 8 11,12,16 t37 RESET Hold Time 1. ns 8 11,13 t38 RESET Pulse Width, Vee & ClK Stable 15 ClKs 8 11,17 t39 RESET Active After Vee & ClK Stable 1. ms 8 Power up 4 Reset Configuration Signals (lnt, FlUSH#, 5. ns 8 12,16,17 FRCMC#) Setup Time 41 Reset Configuration Signals (NT, FlUSH#, 1. ns 8 13 FRCMC#) Hold Time 31

32 PENTUM PROCESSOR 75/9/1/12 Table 12. Pentium Processor 61\75, 815\1 AC Specifications for 5-MHz Bus Operation (Contd.) < Vee < 3.465V, TeASE = to 7 C, CL = pf Symbol Parameter Min Max Unit Figure Notes 42a Reset Configuration Signals (NT, FLUSH #, 2. ClKs 8 To RESET falling FRCMC#) Setup Time, Async. edge(16) t42b Reset Configuration Signals (NT, FLUSH #, 2. ClKs 8 To RESET falling FRCMC#, BRDYC#, BUSCHK#) Hold Time, edge(27) Async. 42c Reset Configuration Signals (BRDYC#, 3. ClKs 8 To RESET falling BUSCHK#) Setup Time, Async. edge(27) 42d Reset Configuration Signal BRDYC# Hold 1. ns To RESET falling Time, RESET driven synchronously edge(1,27) 43a BF, CPUTYP Setup Time 1. ms 8 To RESET falling edge(22) t43b BF, CPUTYP Hold Time 2. ClKs 8 To RESET falling edge(22) t43c APCEN Setup Time 2. ClKs 8 To RESET falling edge 43d APCEN Hold Time 2. ClKs 8 To RESET falling edge 44 TCK Frequency 16. MHz 45 TCKPeriod 62.5 ns 4 46 TCK High Time 25. ns t47 TCKlowTime 25. ns 48 TCK Fall Time 5. ns 4 (2.V -.8V) (1,8,9) t49 TCK Rise Time 5. ns 4 (.8V -2.V) (1,8,9) t5 TRST # Pulse Width 4. ns 1 Asynchronous(1 ) t51 TD, TMS Setup Time 5. ns 9 7 t52 TD, TMS Hold Time 13. ns 9 7 t53 TDO Valid Delay ns 9 8 t54 TDO Float Delay 25. ns 9 1,8 t55 All Non-Test Outputs Valid Delay ns 9 3,8,1 32

33 PENTUM PROCESSOR 75/9/1/12 Table 12. Processor 61\75, 815\ 1 AC Specifications for 5-MHz Bus Operation (Contd.) < Vee < 3.465V, TeASE = to 7 C, CL = pf Symbol Parameter Min Max Unit Figure Notes t5e All Non-Test Outputs Float Delay 25. ns 9 1,3,6,1 t57 All Non-Test nputs Setup Time 5. ns 9 3,7,1 t58 All Non-Test nputs Hold Time 13. ns 9 3,7,1 APC AC Specifications teoa PCCLK Frequency MHz teob PCCLK Period ns 4 teoc PCCLK High Time 9. ns 4 tatld PCCLK Low Time 9. ns 4 teoe PCCLK Rise Time ns 4 teof PCCLK Fall Time ns 4 teog PCDO-1 Setup Time 3. ns 7 ToPCCLK teoh PCDO-1 Hold Time 2.5 ns 7 ToPCCLK teoi PCDO-1 Valid Delay (LtoH) ns 5 From PCCLK(28,29) teoi PCDO-1 Valid Delay (HtoL) ns 5 From PCCLK(28,29) 33

34 PENTUM PROCESSOR 75/9/1/12 Table 13. Processor 61\75, 815\ 1 Dual Processor Mode AC Specifications for 5 MHz Bus Operation < Vee < 3.465V, TeASE = to 7 C, CL = pf Symbol Parameter Min Max Unit Figure Notes t8a PBREQ#, PBGNT# Valid Delay ns 5 18 taob PHT#;PHTM# Flight Time 2. ns 11 3 t81a PBREQ#, PBGNT# Setup Time 8. ns 7 18 t82 PBREQ#, PBGNT# Hold Time 1. ns 7 18,24 t83a A5-A31 Setup Time 6.5 ns 7 18,21,26 t83b D/C#, W/R#, CACHE#, lock#, 6. ns 7 18,21 SCYC Setup Time t83c ADS#, M/O# Setup Time 8. ns 7 18,21 ta3d HT#, HTM# Setup Time 8. ns 7 18,21 t839 HlDA Setup Time 6. ns 7 18,21 ta4 ADS#, D/C#, W/R#, M/O#, 1. ns 7 18,21 CACHE #, lock #,A5-A31, HlDA, HT #, HTM #, SCYC Hold Time tas DPEN# Valid Time 1. ClKs 18,19,23 t86 DPEN # Hold Time 2. ClKs 18,2,23 t87 APC D (BEO#-BE3#) Setup Time 2. ClKs 8 To RESET falling edge(23) t88 APC D (BEO#-BE3#) Hold Time 2. ClKs 8 From RESET falling edge(23) tag D/P# Valid Delay ns 5 Primary Processor Only 34

35 PENTUM PROCESSOR 75/9/1/ AC Timing Tables for a 6-MHz Bus The AC specifications given in Tables 14 and 15 consist of output delays, input setup requirements and input hold requirements for a 6-MHz external bus. All AC specifications (with the exception of those for the TAP signals and APC signals) are relative to the rising edge of the ClK input. All timings are referenced to 1.5V for both "" and "1" logic levels unless otherwise specified. Within the sampling window, a synchronous input must be stable for correct Pentium processor 75/9/11 12 operation. Table 14. Pentlum@ Processor 735\9 AC Specifications for 6-MHz Bus Operation < Vee < 3.465V, TeASE = to 7 C, CL = pf Symbol Parameter Min Max Unit Figure Notes Frequency MHz 4 t1a ClK Period ns 4 t1b ClK Period Stability ±25 ps 4 Adjacent Clocks,(1,25) t2 ClK High Time 4. ns t3 ClKlowTime 4. ns t4 ClKFallTime ns 4 (2.V -.8V) (1,5) t5 ClK Rise Time ns 4 (.8V -2.V) (1,5) tsa ADS#, ADSC#, PWT, PCD, BEO"7#, ns 5 M/O#, D/C#, CACHE#, SCVC, W/R# Valid Delay tsb AP Valid Delay ns 5 tae A3-A31, lock# Valid Delay ns 5 t7 ADS#, ADSC#, AP, A3-A31, PWT, 1. ns 5 1 PCD, BEO-7#, M/O#, D/C#, W/R#, CACHE#, SCVC, lock# Float Delay taa APCHK#, ERR#, FERR# Valid Delay ns 5 4 tab PCHK# Valid Delay ns 5 4 t9a BREa, HlDA Valid Delay ns 5 4 t9b SMACT# Valid Delay ns 5 t1a HT# Valid Delay ns 5 t1b HTM # Valid Delay ns 5 t11a PMO-1, BPO-3 Valid Delay ns 5 t11b PRDV Valid Delay ns 5 t12-63, DPO-7 Write Data Valid Delay ns 5 35

36 PENTUM PROCESSOR 75/9/1/12 Table 14. Pentium Processor 735\9 AC Specifications for 6-MHz Bus Operation (Contd.) < Vee < 3.465V, TeASE = to 7 C, CL = pf Symbol Parameter Min Max Unit Figure Notes t13 63, DPO 3 Write Data Float Delay 1. ns 6 1 t14 A5 A31 Setup Time 6. ns 7 26 t15 A5 A31 Hold Time 1. ns 7 t16a NV, AP Setup Time 5. ns 7 t16b EADS# Setup Time 5.5 ns 7 t17 EADS#, NV, AP Hold Time 1. ns 7 t18a KEN # Setup Time 5. ns 7 t18b NA#, WB/WT# Setup Time 4.5 ns 7 t19 KEN#, WB/WT#, NA# Hold Time 1. ns 7 t2 BRDY#, BRDYC# Setup Time 5. ns 7 t21 BRDY#, BRDYC# Hold Time 1. ns 7 t22 AHOLD, BOFF # Setup Time 5.5 ns 7 t23 AHOLD, BOFF # Hold Time 1. ns 7 t24 BUSCHK#, EWBE#, HOLD, PEN# Setup 5. ns 7 Time t25 BUSCHK#, EWBE#, PEN# Hold Time 1. ns 7 t25a HOLD Hold Time 1.5 ns 7 t26 A2M#, NTR, STPCLK# Setup Time 5. ns 7 12,16 t27 A2M#, NTR, STPCLK# Hold Time 1. ns 7 13 t28 NT, FLUSH#, NM, SM#, GNNE# Setup 5. ns 7 12,16,17 Time t29 NT, FLUSH#, NM, SM#, GNNE# Hold 1. ns 7 13 Time t3 NT, FLUSH#, NM, SM#, GNNE# Pulse 2. CLKs 15,17 Width, Async t31 RS# Setup Time 5. ns 7 12,16,17 t32 RS# Hold Time 1. ns 7 13 t33 RS# Pulse Width, Async. 2. CLKs 7 15,17 36

37 PENTUM PROCESSOR 75/9/1/12 Table 14. Pentium Processor 735\9 AC Specifications for 6-MHz Bus Operation (Contd.) < Vee < 3.465V, TeASE = to 7 C, CL = pf Symbol Parameter Min Max Unit Figure Notes t34-63, OPO-7 Read Oata Setup Time 3. ns 7 t35-63, OPO-7 Read Oata Hold Time 2. ns 8 t36 RESET Setup Time 5. ns 8 11,12,16 t37 RESET Hold Time 1. ns 8 11, 13 t38 RESET Pulse Width, Vee & ClK Stable 15 ClKs 8 11, 17 t39 RESET Active After Vee & ClK Stable 1. ms 8 Power up t4 Reset Configuration Signals (NT, FLUSH #, 5. ns 8 12,16,17 FRCMC#) Setup Time t41 Reset Configuration Signals (NT, FLUSH #, 1. ns 8 13 FRCMC #) Hold Time t42a Reset Configuration Signals (NT, FLUSH #, 2. ClKs 8 To RESET falling FRCMC#) Setup Time, Async. edge(16) 42b Reset Configuration Signals (NT, FLUSH #, 2. ClKs 8 To RESET falling FRCMC#, BROYC#, BUSCHK#) Hold Time, edge (27) Async. 42c Reset Configuration Signals (BROYC#, 3. ClKs 8 To RESET falling BUSCHK#) Setup Time, Async. edge(27) t42d Reset Configuration Signal BROYC# Hold 1. ns To RESET falling Time, RESET driven synchronously edge(1,27) t43a BF, CPUTYP Setup Time 1. ms 8 To RESET falling edge(22) t43b BF, CPUTYP Hold Time 2. ClKs 8 To RESET falling edge(22) t43c APCEN Setup Time 2. ClKs 8 To RESET falling edge t43d APCEN Hold Time 2. ClKs 8 To RESET falling edge t44 TCK Frequency 16. MHz 8 t45 TCK Period 62.5 ns 4 t46 TCK High Time 25. ns t47 TCKlowTime 25. ns 37

38 PENTUM PROCESSOR 75/9/1/12 Table 14. Pentium Processor 735\9 AC Specifications for SO-MHz Bus Operation (Contd.) < Vee < 3.465V, TeASE = to 7 C, CL = O.pF Symbol Parameter Min Max Unit Figure Notes 48 TCKFaliTime 5. ns 4 (2.V -.8V)(1,8,9) 49 TCK Rise Time 5. ns 4 (O.8V -2.V)(1,8,9) tso TRST # Pulse Width 4. ns 1 Asynchronous(1 ) ts1 TD, TMS Setup Time 5. ns 9 7 ts2 TD, TMS Hold Time 13. ns 9 7 ts3 TOO Valid Delay ns 9 8 ts4 TOO Float Delay 25. ns 9 1,8 tss All Non-Test Outputs Valid Delay ns 9 3,8,1 tss All Non-Test Outputs Float Delay 25. ns 9 1,3,8,1 ts7 All Non-Test nputs Setup Time 5. ns 9 3,7,1 ts8 All Non-Test nputs Hold Time 13. ns 9 3,7,1 APC AC Specifications tsoa PCCLK Frequency MHz 4 tsob PCCLK Period ns 4 tsoc PCCLK High Time 9. ns 4 tsod PCCLK Low Time 9. ns 4 teoe PCCLK Rise Time ns 4 teo! PCCLK Fall Time ns 4 tsog PCDO-1 Setup Time 3. ns 7 ToPCCLK tsoh PCDO-1 Hold Time 2.5 ns 7 ToPCCLK teoi PCDO-1 Valid Delay (LtoH) ns 5 From PCCLK(28,29) teoj PCDO-1 Valid Delay (HtoL) ns 5 From PCCLK(28,29) 38

39 PENTUM PROCESSOR 75/9/1/12 Table 15. Pentium Processor 735\9 Dual Processor Mode AC Specifications for 6-MHz Bus Operation < Vec < 3A65V, TCASE = to 7 C, CL = pf Symbol tsoa tsob t81a Parameter PBREQ#, PBGNT# Valid Delay PH T #, PHTM # Flight Time PBREQ#, PBGNT# Setup Time 182 PBREQ#, PBGNT# Hold Time ts3a 183b ts3e ts3d ts3e ts4 A5-A31 Setup Time D/C#, W/R#, CACHE#, lock#, SCVC Setup Time ADS#, M/O# Setup Time HT #, HTM # Setup Time HlDA Setup Time ADS#, D/C#, W/R#, M/O#, CACHE#, lock#, A5-A31, HlDA, HT#, HTM#, SCVC Hold Time 185 DPEN # Valid Time ts6 ts7 ts8 ts9 DPEN # Hold Time APC D (BEO#-BE3#) Setup Time APC D (BEO#-BE3#) Hold Time D/P# Valid Delay Min Max Unit Figure Notes ns ns ns ns 7 18,24 3. ns 7 18,21,26 4. ns 7 18,21 6. ns 7 18,21 6. ns 7 18,21 6. ns 7 18,21 1. ns 7 18,21 1. ClKs 18,19,23 2. ClKs 18,2,23 2. ClKs 8 To RESET falling edge(23) 2. ClKs 8 From RESET falling edge(23) ns 5 Primary Processor Only AC Timing Tables for a 66-MHz Bus The AC specifications given in Tables 16 and 17 consist of output delays, input setup requirements and input hold requirements for a 66-MHz external bus. All AC specifications (with the exception of those for the TAP signals and AP C signals) are relative to the rising edge of the ClK input. All timings are referenced to 1.5V for both "" and "1" logic levels unless otherwise specified. Within the sampling window, a synchronous input must be stable for correct Pentium processor 75/9/11 12 operation. 39

40 PENTUM PROCESSOR 75/9/1/12 Table 16. Pentium Processor 815\ 1 AC Specifications for 66-MHz Bus Operation < Vcc < 3.465V, T CASE = to 7 C, CL = pf Symbol Parameter Min Max Unit Figure Notes Frequency MHz t1a ClKPeriod ns 4 t1b ClK Period Stability ±25 ps Adjacent Clocks(1,2S) t2 ClK High Time 4. ns t3 ClKlowTime 4. ns 4 ClKFaliTime ns 5 (2.V-O.8V)(1) ts ClK Rise Time ns 4 (.8V-2.V)(1) 16a ADSC#, PWT, PCD, BEO-7#, D/C#, ns 5 W/R#, CACHE#, SCYCValid Delay tsb AP Valid Delay ns 5 16e A3-A31, lock# Valid Delay ns 5 tsd ADS#, M/O# Valid Delay ns 5 t7 ADS#, ADSC#, AP, A3-A31, PWT, 1. ns 6 1 PCD, BEO-7#, M/O#, D/C#, W/R#, CACHE#, SCYC, lock# Float Delay taa APCHK#, ERR#, FERR# Valid Delay ns 5 4 tab PCHK# Valid Delay ns 5 4 tsa BREQ, HlDA Valid Delay ns 5 4 tsb SMACT# Valid Delay ns 5 4 t1a HT# Valid Delay ns 5 t1b HTM# Valid Delay ns 5 t11a PMO-1, BPO-3 Valid Delay ns 5 t11b PRDY Valid Delay ns 5 t12-63, DPO-7 Write Data Valid Delay ns 5 t13-63, DPO-3 Write Data Float Delay 1. ns 6 1 t14 A5-A31 Setup Time 6. ns 7 26 t15 A5-A31 Hold Time 1. ns 7 4

41 PENTUM PROCESSOR 75/9/1/12 Table 16. Pentlum Processor 815\ 1 AC Specifications for 66-MHz Bus Operation (Contd.) < Vee < 3.465V, TeAsE = to 7 C, CL = pf Symbol Parameter Min Max Unit Figure Notes t16a NV, AP Setup Time 5. ns 7 t16b EADS # Setup Time 5.5 ns 7 t17 EADS#, NV, AP Hold Time 1. ns 7 t18a KEN # Setup Time 5. ns 7 t18b NA #, WB/WT # Setup Time 4.5 ns 7 t19 KEN#, WB/WT#, NA# Hold Time 1. ns 7 t2 BRDY#, BRDYC# Setup Time 5. ns 7 t21 BRDY#, BRDYC# Hold Time 1. ns 7 t22 AHOlD, BOFF # Setup Time 5.5 ns 7 t23 AHOlD, BOFF # Hold Time 1. ns 7 t24 BUSCHK#, EWBE#, HOLD, PEN# Setup 5. ns 7 Time t25a BUSCHK#, EWBE#, PEN# Hold Time 1. ns 7 t25b HOLD Hold Time 1.5 ns 7 t26 A2M #, NTR, STPClK # Setup Time 5. ns 7 12,16 t27 A2M#,NTR, STPClK# Hold Time 1. ns 7 13 t28 NT, FLUSH #, NM, SM #, GNNE # Setup 5. ns 7 12,16,17 Time t29 NT, FLUSH #, NM, SM #, GNNE # Hold 1. ns 7 13 Time t3 NT, FlUSH#, NM, SM#,GNNE# Pulse 2. ClKs 15,17 Width, Async t31 RS# Setup Time 5. ns 7 12,16,17 t32 RS# Hold Time 1. ns 7 13 t33 RS# Pulse Width, Async. 2. ClKs 15,17 t34 DO-D63, DPO 7 Read Data Setup Time 3. ns 7 t35 DO D63, DPO-7 Read Data Hold Time 2. ns 7 t36 RESET Setup Time 5. ns 8 11,12,16 41

42 PENTUM PROCESSOR 75/9/1/12 Table 16. Pentium Processor 815\ 1 AC Specifications for 66-MHz Bus Operation (Contd.) < Vee < 3.465V, TeASE = to 7 C, CL = pf Symbol Parameter Min Max Unit Figure Notes t37 RESET Hold Time 1. ns 8 11,13 t38 RESET Pulse Width, Vee & CL K Stable 15. CLKs 8 11,17 t39 RESET Active After Vee & CLK Stable 1. ms 8 Power up t4 Reset Configuration Signals (NT, FLUSH #, 5. ns 8 12,16,17 FRCMC#) Setup Time t41 Reset Configuration Signals (NT, FLUSH #, 1. ns 8 13 FRCMC#) Hold Time 42a Reset Configuration Signals (NT, FLUSH #, 2. CLKs 8 To RESET falling FRCMC#) Setup Time, Async. edge(16) 42b Reset Configuration Signals (NT, FLUSH #, 2. CLKs 8 To RESET falling FRCMC#, SRDYC#, SUSCHK#) Hold Time, edge(27) Async. 42c Reset Configuration Signals (SRDYC#, 3. CLKs 8 To RESET falling SUSCHK#) Setup Time, Async. edge(27) 42d Reset Configuration Signal SRDYC# Hold 1. ns To RESET falling Time, RESET driven synchronously edge(1,27) t43a SF, CPUTYP Setup Time 1. ms 8 To RESET falling edge(22) 43b SF, CPUTYP Hold Time 2. CLKs 8 To RESETfalling edge(22) 43c APCEN Setup Time 2. CLKs 8 To RESET falling edge 43d APCEN Hold Time 2. CLKs 8 To RESET falling edge 44 TCK Frequency 16. MHz 45 TCKPeriod 62.5 ns 4 46 TCK High Time 25. ns 47 TCKLowTime 25. ns t48 TCKFallTime 5. ns 4 (2.V -.8V)(1,8,9) 49 TCK Rise Time 5. ns 4 (.8V-2.V)(1,8,9) t5 TRST # Pulse Width 4. ns 1 Asynchronous(1 ) t51 TD, TMS Setup Time 5. ns

43 PENTUM PROCESSOR 75/9/1/12 Table 16. Processor 815\ 1 AC Specifications for 66-MHz Bus Operation (Contd.) < VCC < 3.465V, TCASE= to 7 C, CL = pf Symbol Parameter Min Max Unit Figure Notes ts2 TD, TMS Hold Time 13. ns 9 7 ts3 TOO Valid Delay ns 9 8 ts4 TOO Float Delay 25. ns 9 1,8 tss All Non-Test Outputs Valid Delay ns 9 3,8,1 tss All Non-Test Outputs Float Delay 25. ns 9 1,3,8,1 ts7 All Non-Test nputs Setup Time 5. ns 9 3,7, 1 ts8 All Non-Test nputs Hold Time 13. ns 9 3,7,1 APC AC Specifications tsoa PCCLK Frequency MHz tsob PCCLK Period ns 4 tsoc PCCLK High Time 9. ns 4 taod PCCLK Low Time 9. ns 4 tsoe PCCLK Rise Time ns 4 t6f PCCLK Fall Time ns 4 tsog PCDO-1 Setup Time 3. ns 7 ToPCCLK tsoh PCDO-1 Hold Time 2.5 ns 7 ToPCCLK taoi PCDO-1 Valid Delay (LtoH) ns 5 From PCCLK(28,29) taoj PCDO-1 Valid Delay (HtoL) ns 5 From PCCLK(28,29) 43

44 PENTUM PROCESSOR 75/9/1/12 Table 17. Pentium Processor 815\ 1 Dual Processor Mode AC Specifications for 66-MHz Bus Operation < VCC < 3.465V, TCASE = to 7 C, Cl = pf Symbol Parameter Min Max Unit Figure Notes teoa PBREQ#, PBGNT# Valid Delay ns 5 18 teob PHT#, PHTM# FlightTime 2. ns 11 3 te1a PBREQ#, PBGNT# Setup Time 8. ns 7 18 te2 PBREQ#, PBGNT# Hold Time 1. ns 7 18,24 te3a A5 A31 Setup Time 3. ns 7 18,21,26 te3b D/C#, W/R#, CACHE#, lock #, SCYC 4. ns 7 18,21 Setup Time te3c ADS#, MO# Setup Time 5.8 ns 7 18,21 te3d HT#, HTM# Setup Time 6. ns 7 18,21 te3e HlDA Setup Time 6. ns 7 18,21 te4 ADS#, D/C#, W/R#, MO#, CACHE#, 1. ns 7 18,21 lock#, A5-A31, HlDA, HT#, HTM#, SCYC Hold Time te5 OPEN # Valid Time 1. ClKs 18,19,23 te6 OPEN # Hold Time 2. ClKs 18,2,23 te7 APC 1 (BEO#-BE3#) Setup Time 2. ClKs 8 To RESET falling edge(23) tee APC 1 (BEO#-BE3#) Hold Time 2. ClKs 8 From RESET falling edge(23) te9 D/P# Valid Delay ns 5 Primary Processor Only NOTES: Notes 2,6, and 14 are general and apply to all standard TTL signals used with the Pentium!!> Processor family. 1. Not 1% tested. Guaranteed by designl characterization. 2. TTL input test waveforms are assumed to be to 3V transitions with WnS rise and fall times. 3. Non-test outputs and inputs are the normal output or input signals (besides TCK, TRST #, TD, TDO, and TMS). These timings correspond to the response Of these signals due to boundary scan operations. 4. APCHK#, FERR#, HlDA, ERR#, lock#, and PCHK# are glitch-free outputs. Glitch-free signals monotonically transition without false transitions (i.e., glitches). 5..8V1ns ~ ClK input riselfall time ~ ev/ns. 6..3V/ns ~ input riselfall time ~ 5V/ns. 7. Referenced to TCK rising edge. e. Referenced to TCK falling edge ns can be added to the maximum TCK rise and fall times for every 1 MHz of frequency below 33 MHz. 1. During probe mode operation, do not use the boundary scan timings (t55.5s). 11. FRCMC# should be tied to Vee (high) to ensure proper operation of the Pentium processor 75/9/1/12 as a primary processor. 12. Setup time is required to guarantee recognition on a specific clock. Pentium processor 75/9/1/12 must meet this specification for dual processor operation for the FLUSH # and RESET signals. 44

45 PENTUM PROCESSOR 75/9/1/ Hold time is required to guarantee recognition on a specific clock. Pentium processor 75/9/1/12 must meet this specification for dual processor operation for the FLUSH # and RESET signals. 14. All TTL timings are referenced from 1.5V. 15. To guarantee proper asynchronous recognition, the signal must have been de-asserted (inactive) for a minimum of 2 clocks before being returned active and must meet the minimum pulse width. 16. This input may be driven asynchronously. However, when operating two processors in dual processing mode, FLUSH # and RESET must be asserted synchronously to both processors. 17. When driven asynchronously, RESET, NM, FlUSH#, RS#, NT, and SM# must be de-asserted (inactive) for a minimum of 2 clocks before being returned active. 18. Timings are valid only when dual processor is present. 19. Maximum time DPEN# is valid from rising edge of RESET. 2. Minimum time DPEN # is valid after falling edge of RESET. 21. The D/C#, MO#, W/R#, CACHE#, and A5-A31 signals are sampled only on the ClK that ADS# is active. 22. BF and CPUTYP should be strapped to Vee or Vss. 23. RESET is synchronous in dual processing mode and functional redundancy checking mode. All signals which have a setup or hold time with respect to a falling or rising edge of RESET in UP mode, should be measured with respect to the first processor clock edge in which RESET is sampled either active or inactive in dual processing and functional redundancy checking modes. 24. The PHT# and PHTM# signals operate at the core frequency (75, 9 or 1 MHz). 25. These signals are measured on the rising edge of adjacent ClKs at 1.5V. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal and external clocks, the jitter frequency spectrum should not have any power spectrum peaking between 5 KHz and 113 of the ClK operating frequency. The amount of jitter present must be accounted for as a component of ClK skew between devices. 26. n dual processing mode, timing t14 is replaced by t83a. Timing t14 is required for external snooping (e.g., address setup to the ClK in which EADS# is sampled active) in both uniprocessor and dual processor modes. 27. BRDYC# and BUSCHK# are used as reset configuration signals to select buffer size. 28. This assumes an external pull up resistor to Vee and a lumped capacitive load such that the maximum RC product does not exceed R = 15n, C = 24 pf. 29. This assumes an external pullup resistor to Vee and a lumped capacitive load such that the minimum RC product does not fall below R = 15n, C = 2 pf. 3. This is a flight time specification, that includes both flight time and clock skew. The flight time is the time from where the unloaded driver crosses 1.5V (5% of min Vee), to where the receiver crosses the 1.5V level (5% of min Vee). See Figure 11. Each valid delay is specified for a pf load. The system designer should use /O buffer modeling to account for signal flight time delays. 45

46 PENTUM PROCESSOR 75/9/1/12 2.Y. O.8Y. Tv = t5, t49, tboe; Tw = t4, t4b, tbof; Tx = t3, t47, tbod Ty = t1, t45, tbob; Tz = t2, t4b, tsoc Figure 4. Clock Waveform Signal Tx = tb, tb, t9, t1, t11, t12, tboi, tbo, tb9 Figure 5. Valid Delay Timings

47 PENTUM PROCESSOR 75/9/1/12 Ty Signal Tx = t7, t13; Ty = t6min, t12min Figure 6. Float Delay Timings elk Tx Ty \'---- Signal VALD Tx = t14, t16, t1 B, t2, t22, t24, t26, t2b, t31, t34, t6g (to PCCLK),tB1, tb3 Ty = t15, t17, t19, t21, t23, t25, t27, t29, t32, t35, t6h (to PCCLK), tb2, tb Figure 7. Setup and Hold Timings 47

48 PROCESSOR 75/9/1/12 CLK RESET 1.s.~ T Conflg Tw Tx T = 14, Tu = 141, Tv = 137, T w =142, 143a, 143c, 187, Tx = 143b, 143d, 188, Ty = 138,139, Tz = Figure 8. Reset and Configuration Timings TCK Tv Tw TO TMS TOO Output Signals nput Signals \\\\\\~ Bt Ts ~ S\\SSSS Tr = 157, Ts = 158, Tu = 154, Tv = 151, Tw = 152, Tx = 153, Ty = 155, T:z = 156 Figure 9. Test Timings Tz

49 PENTUM PROCESSOR 75/9/1/12 TRST Tx = t Figure 1. Test Reset Timings Signal Leval Vee 85% Vee 5% Vee ~--",* % Vee V ~ T me Figure 11. 5% Vee Measurement of Flight Time 49

50 PENTUM PROCESSOR 75/9/1/12 4. MECHANCAL SPECFCATONS The Pentium processor 75/9/1/12 is packaged in a 296-pin staggered pin grid array package. The pins are arraoged in a 37 x 37 matri.x and the package dimensions are 1.95" x 1.95" (Table 18). A 1.25" x 1.25" copper tungsten heat spreader may be attached to the top of the ceramic. This package design with spreader is being phased out in favor of a package which has no attached spreader. n this section, both spreader and non-spreader packages are shown. The mechanical specifications for the Pentium processor 75/9/1/12 are provided in Table 19. Figure 12 shows the package dimensions. Table 18_ Package nformation Summary Package Type Total Pins Pin Array Package Size Pentium Processor 75/9/1/12 SPGA x " x 1.95" 4.95 cm x 4.95 cm 5

51 PENTUM PROCESSOR 75/9/1/12 Table 19. Package Dimensions with Spreader Family: Ceramic Staggered Pin Grid Array Package Symbol Millimeters nches Min Max Notes Min Max Notes A Solid Lid Solid Lid A Solid Lid Solid Lid A B D D D Square Square D D E E F.127 Diagonal.5 Diagonal L N S Table 2. Package Dimensions without Spreader Family: 296 Pin Ceramic Pin Grid Array Package Symbol Millimeters nches Min Max Notes Min Max Notes A Ceramic Lid Ceramic Lid A Ceramic Lid Ceramic Lid A B D D D ncludes Fillet ncludes Fillet e F.127 Flatness of the top of the.5 Flatness of the top of the package. measured package. measured diagonally diagonally L N 296 Total Pins 296 Total Pins S

52 PENTUM PROCESSOR 75/9/1/12 ~ D ~ D ~ PlnC3 ~ 45 CHAMFER REF (NDEx CORNER) Figure 12. Pentlum Processor 75/9/1/12 Package Dimensions (with Spreader)

53 PENTUM PROCESSOR 75/9/1/12 Seating ~ ~Lt-.. L. e1 'T".L r 9 l 2.2l! 1.52 REF. 45 ndex Chamfer (ndex Corner) PinC3 Bottom View (Pin Side Up) A-+!: :+ A i:'-: A2~~ Side View Top View Figure 13. Pentium Processor 75/9/1/12 Package Dimensions (without Spreader) 53

54 PENTUM PROCESSOR 75/9/1/12 5. THERMAL SPECFCATONS Due to the advanced 3.3V BiCMOS process that it is produced on, the Pentium processor 75/9/11 12 dissipates less power than the Pentium processor 6/66. The Pentium processor 75/9/1/12 is specified for proper operation when case temperature, T CASE, (T cl is within the specified range of O C to 7 C. 5.1 Measuring Thermal Values The Pentium processor 75/9/1/12 package will include a heat spreader. To verify that the proper T C (case temperature) is maintained, it should be measured at the center of the package top surface (opposite of the pins). The measurement is made in the same way with or without a heat sink attached. When a heat sink is attached a hole (smaller than.15" diameter) should be drilled through the heat sink to allow probing the center of the package. See Figure 13 for an illustration of how to measure T C. To minimize the measurement errors, it is recommended to use the following approach: Use 36-gauge or finer diameter K, T, or J type thermocouples. The laboratory testing was done using a thermocouple made by Omega (part number: 5TC-TTK-36-36). Attach the thermocouple bead or junction to the center of the package top surface using high thermal conductivity cements. The laboratory testing was done by using Omega Bond (part number: OB-1). The thermocouple should be attached at a 9-degree angle as shown in Figure 14. The hole size should be smaller than.15" in diameter THERMAL EQUATONS AND DATA For the Pentium processor 75/9/1/12, an ambient temperature, T A (air temperature around the processor), is not specified directly. The only restriction is that T C is met. To calculate T A values, the following equations may be used: where: T A and T C = (JCA = P = T A = T C - (P CA) ambient and case temperature. (OC) case-to-ambient thermal resistance. (OC/Watt) junction-to-ambient thermal resistance. (OC/Watt) junction-to-case thermal resistance. (OC/Watt) maximum power consumption (Watt) Table 21 lists the (JCAvalues for the Pentium processor 75/9/1/12 with passive heat sinks. Figure 15 shows Table 21 in graphic format Figure 14_ Technique for Measuring TC 54

55 PENTUM PROCESSOR 75/9/1/12 Table 21. Thermal Resistances for Packages with Spreader Heat Sink n nches 8JC ("C/Watt) 8CA(OC/Watt) vs. Laminar Airflow (linear ft/min) x1.95xO x1.95xO x1.95xO x1.95xO x1.95xO x1.95xO x1.95 x x1.95x x1.95x Without Heat Sink Table 22. Thermal Resistances for Packages without Spreader 8CA(OC/Watt) vs. Laminar Airflow (linear ft/min) Heat Sink in nches 8JC ("C/Watt) ~ Without Heat Sink NOTES: Heat sinks are omni directional pin aluminum alloy. Features were based on standard extrusion practices for a given height Pin size ranged from 5 to 129 mils Pin spacing ranged from 93 to 175 mils Based thickness ranged from 79 to 2 mils Heat sink attach was.5" of thermal grease. Attach thickness of.2" will improve performance approximately.3e/walt 55

56 PENTUM PROCESSOR 75/9/1/ O--OLFM -OOLFM -2LFM LFM -6LFM -8LFM O+-----~--~~~ ~----~ _----~----~ o Heat Sink Height (in) Figure 15. Thermal Resistance vs. Heatslnk Height (Spreader Package) ~ ~ '"...., '"..c: OLFM -ll-1lfm -.r.-2 LFM ~4LFM ""*""6 LFM -e-8l'm Heat Sink Height (n) Figure 16. Thermal Resistance vs. Heatsink Height (Non-Spreader Package) 56

57 PENTUM PROCESSOR 75/9/1/12 6. FUTURE PENTUM OverDrive PROCESSOR SOCKET SPECFCATON 6.1 ntroduction The Future Pentium OverDrive processor is an enduser single-chip CPU upgrade product for Pentium processor 75/9/1/12-based systems. The Future Pentium OverDrive processor will speed up most software applications by 4% to 7%. t is binary compatible with the Pentium processor 75/9/ 1/12. An upgrade socket (Socket 5) has been defined along with the Pentium processor 75/9/1/12 as part of the processor architecture. Upgradability can be supported by implementing either a single socket or a dual socket strategy for Pentium processor 75/9/1/ 12-based systems. A single socket system will include a 32-pin SPGA Socket 5. When this system configuration is upgraded, the Pentium processor 75/9/1/12 is simply replaced by the Future Pentium OverDrive processor. A dual socket system will include a 296-pin SPGA socket for the Pentium processor 75/9/1/12 and a 32-pin SPGA Socket 5 for the second processor. n dual socket systems, Socket 5 can be filled with either the Dual processor or the Future Pentium OverDrive processor UPGRADE OBJECTVES Systems using the Pentium processor 75/9/1/ 12, and equipped with only one processor socket, must use socket 5 to also accept the Future Pentium OverDrive processor. Systems equipped with two processor sockets must use Socket 5 as the second socket to contain either the Pentium processor 75/ 9/1/12 Dual processor or the Future Pentium OverDrive processor. nclusion of Socket 5 in Pentium processor 75/9/ 1/12 systems provides the end-user with an easy and cost-effective way to increase system performance. The paradigm of simply installing an additional component into an easy to use Zero nsertion Force (ZF) Socket to achieve enhanced system performance is familiar to the millions of end-users and dealers who have purchased ntel math coprocessor upgrades to boost system floating point performance. The majority of upgrade installations which take advantage of Socket 5 will be performed by end users and resellers. Therefore, it is important that the design be "end-user easy," and that the amount of training and technical expertise required to install the upgrade processors be minimized. Upgrade installation instructions should be clearly described in the system user's manual. n addition, by making installation simple and foolproof, PC manufacturers can reduce the risk of system damage, warranty claims and service calls. Feedback from ntel's math coprocessor upgrade customers highlights three main characteristics of end user easy designs: accessible socket location clear indication of upgrade component orientation minimization of insertion force The Future Pentium OverDrive processor will support the 8243NX PClset. Unlike the Pentium processor 75/9/1/12, the Future Pentium Over Drive processor will not support the Cache Controller and Cache SRAM chip set NTEL VERFCATON PROGRAM The ntel Verification Program ensures that a Pentium processor 75/9/1/12-based personal computer meets a minimum set of design criteria for reliable and straight-forward CPU upgradability with a Future Pentium OverDrive processor. Testing performed at the ntel Verification Labs confirms that Future Pentium OverDrive processor specifications for mechanical, thermal, electrical, functional, and end-user installation attributes have been met. While system designs may exceed these minimum design criteria, the intent is to provide end-users with confidence that computer systems based on verified designs can be upgraded with Future Pentium Over Drive processors. The OEM submits production-ready designs to one of ntel's worldwide Verification Labs for testing. The OEM benefits from advance testing of the design prior to availablitiy of the Future Pentium OverDrive processor. By identifying and resolving upgradability problems before a system is introduced, the OEM increases system quality and reduces future support costs associated with end-user calls and complications when the CPU upgrade is ultimately installed. 57