Cypress Semiconductor

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1 C3 Cypress Semiconductor USB3.0 Solution Ken Higashiyama June 13, 2012 Cypress Semiconductor

2 USB 3.0 Ecosystem USB 3.0 PC SHIPMENT 262 MU 525 MU 624 MU 673 MU USB 3.0 PENETRATION 50.3% 90.7% 99.6% 100% AMD SHIPPED ITS 1 ST USB 3.0 CHIPSET (A75, A70M) APRIL 2011 INTEL LAUNCHED ITS IVY BRIDGE CPU AND COMPANION USB 3.0 CHIPSET (Z77) APRIL 2012 Source: In-Stat Wired USB May, USB 3.0 SUPERSPEED PRODUCTS CERTIFIED TO DATE Cypress Semiconductor 2

3 USB 3.0 Interface Host Device D+ USB2.0 Signals D- VBUS USB3.0 GND Additional Signals SSTX SSRX USB 3.0 has two pairs of differential signals in addition to USB 2.0 signals Cypress Semiconductor 3 3

4 USB 3.0 Applications HP Fujitsu StarTech Gigabyte Buffalo Asus Asus Gigabyte Dell Sony Toshiba Acer Asus PC PCIX/XPRESS CARD MOTHERBOARD Ximea Visiosens Black Magic Point Grey VIDEO & IMAGING Rotac OTHER Buffalo STORAGE Dane-Elec Buffalo LaCie Western Digital Active Seagate DISPLAY ADAPTOR Samsung HUB LaCie IDS MONITOR RAID Super Talent Cypress Semiconductor 4

5 Video Compression USB 2.0, NO COMPRESSION USB 2.0, MJPEG COMPRESSION IMAGE SENSOR FPGA FX2 IMAGE SENSOR MJPEG FPGA FX2 LIMITED VIDEO QUALITY, LOW FRAME RATE LOW COST IMPLEMENTATION GOOD ENOUGH IMAGE QUALITY BUT LOSSY USB 2.0, H.264 COMPRESSION USB 3.0, NO COMPRESSION DRAM IMAGE SENSOR H.264 FPGA FX2 IMAGE SENSOR FPGA FX3 HIGHER BOM COST AND MORE BOARD SPACE BETTER IMAGE QUALITY FOR MOST APPLICATIONS LOWER BOM COST AND SMALLER BOARD HIGHEST IMAGE QUALITY Cypress Semiconductor 5

6 FX3 Overview: Target Applications CONSUMER CAMERAS GAMING INDUSTRIAL CAMERAS MEDICAL IMAGING SURVEILLANCE VIDEO CONFERENCING SCANNERS BIOMETRICS HD VIDEO CAPTURE DATA ACQUISITION AUDIO MIXER INSERT YOUR DESIGN HERE Cypress Semiconductor 6

7 PARTNERSHIPS TO HELP YOU SUCCEED 1. BUILDING STRONG USB 3.0 REPUTATION 2. WORKING WITH DISTRIBUTION AND PARTNERS Microsoft USB Test Tool (MUTT) using FX3 Avnet Kintex 7 Board Using FX3* Arrow/Nuvation Board Using FX3* Tokyo Electron Devices Board Using FX3* 3. BROADENING EVALUATION CHOICES Braintechnology FX3 Mezzanine Board* Enclustra FX3 Xilinx Adapter Board* 4. CREATING REFERENCE DESIGNS * ORDER BOARDS DIRECTLY FROM DISTRIBUTOR, SUPPLIER Aptina Demo 3 using FX3* Net Vision SVI-06 Image Sensor Adapter Board* Cypress Semiconductor 7

8 What is FX3? Add USB3.0 capability to any system General Programmable Interface (GPIF II) to any processor/asic Enable fast data processing and customization Fully accessible 32-bit ARM9 core with 512kB of embedded SRAM µp ASIC FPGA GPIF II JTAG ARM9 512kB SRAM 32 End Points USB 3.0 USB 2.0 OTG EZ-Dtect UART SPI I2C I2S Cypress Semiconductor 8

9 FX2LP vs. FX3 Feature EZ-USB FX2LP EZ-USB FX3 USB Controller USB 2.0 USB 3.0 USB 2.0 OTG Data Processing Capability 8051 ARM926 GPIF General Programmable Interface 16-bit 32-bit Clock Rate 48 MHz 100 MHz No. of States Supported Programmability GPIF Designer GPIF Designer II 10x Performance, With The Same Familiar Architecture Cypress Semiconductor 9

10 FX3 Booting FX3 can be the main processor or co-processor in a system PMODE[2:0] Configures the booting options FX3 booting options PMODE[2:0] F00 F01 F11 F0F F1F 1FF 0F1 Boot Option Sync ADMUX (16-bit) Async ADMUX (16-bit) USB Boot Async SRAM (16-bit) I 2 C* (on failure, USB Boot) I 2 C* Only SPI (on failure, USB Boot) * If EEPROM is used for I 2 C booting, 1 kohm pull up resistors should be placed on the SCL and SDA lines for 1 MHz EEPROM communication. Cypress Semiconductor 10

11 FX3 SDK Components FX3 Development Tools GPIF II Designer Integrated C/C++ Development Environment FX3 Firmware Stack Customer Firmware FX3 Firmware Examples FX3 Framework FX3 Host Software (Windows PC) Application Examples USB Control Center Compiler Assembler Linker Debugger FX3 API Library Cypress Generic USB Driver RTOS Windows USB DI Customer Software Cypress provided Software Third Party Software Available Today! Cypress Semiconductor 11 11

12 GPIF II Hardware: Overview Following diagram depicts the concept of internal and external inputs/outputs of the GPIF II Engine INTR_CPU CPU_IN ARM9 Internal Inputs and outputs of the GPIF II External Inputs and outputs of the GPIF II GPIFII Engine DMA System FX3 Cypress Semiconductor 12

13 GPIF II Hardware: Overview Cypress Semiconductor 13

14 GPIF II Hardware: Signal Types Alphas Outputs that depend on the transition 8 alphas (4 user defined) Example: sample_din Betas Outputs that depend on the state 31 Betas (4 user defined) Example: data_count_incr Lambdas Inputs that go into transition equations 32 Lambdas (16 user defined) Can use 4 per transition Example: data_comp Cypress Semiconductor 14

15 GPIF II Hardware: Control signals OE: Output Enable Provides control over the output drivers that determine if the bus is driven or tristate WE: Write Enable Disables output drivers DLE: Data Latch Enable Allows control over latching data from the data bus Normally combined with WE ALE: Address Latch Enable Allows control to latch address values DRQ: DMA Request Provides a DMA request output that is controlled by state machine and responds to DACK signal DACK: DMA Acknowledge Not a separate function but is used to control behaviour of DRQ Cypress Semiconductor 15

16 GPIF II Hardware: CPU Interrupts Triggered by INTR_CPU action and other GPIF events Handled in firmware with callback function Void CyFxGpifCB (CyU3PGpifEventType event,uint8_t currentstate) INTR_CPU generates a CYU3P_GPIF_EVT_SM_INTERRUPT event Passes a currentstate parameter which indicates the state of the State Machine State numbers are assigned to state names from GPIF II designer in H file Cypress Semiconductor 16

17 GPIF II Hardware: Counters Implemented in GPIF II hardware Can be reset or updated by state machine Can generate limit or match signals as a trigger Address Counter Can check if the counter matches the current address Control Counter Can check if the counter matches the current control inputs Data Counter Can check if counter matches current data Cypress Semiconductor 17

18 GPIF II Designer: Design Work Flow 1. Design State Machine 2. Setup GPIF II interface in GPIF II Designer 3. Create State Machine in GPIF II Designer 4. Build design into C header file 5. Simulate State Machine 6. Integrate design into C firmware application code Cypress Semiconductor 18

19 GPIF II Designer: Supplied interfaces 7 Cypress supplied interfaces Even with supplied interface it is still flexible Cypress Semiconductor 19

20 GPIF II Designer: Interface Settings Peripherals Enabling I2C, SPI, UART, and I2S will have effect on GPIF II port The peripheral selection is only used by the tool to calculate the available pin count. User is responsible for setting up the FX3 I/O Matrix in the firmware application code. Master and Slave Initiate transfer or respond to a transfer Interface clocking Synchronous or Asynchronous Internal or External Control Signals and GPIOs GPIF II state machine inputs/output Unused control signals can be override by firmware DMA flags Special hardware flags controlled by DMA engine not GPIF II Cypress Semiconductor 20

21 GPIF II Designer: Custom Interfaces State machine canvas allows you to drag and drop states and transitions Transition based upon internal GPIF II signals as well as user defined signals Actions are macros that simplify GPIF II outputs Cypress Semiconductor 21

22 GPIF II Designer: Actions Actions control internal and external outputs Relevant actions LOAD_DATA_COUNT Sets up a hardware counter Can be configured in a variety of ways We will use it to keep track of data in our buffer COUNT_DATA Increment data counter IN_DATA Sample data from data bus and send it to a socket or register INTR_CPU Generates CPU interrupt to alert FX3 FX3 can query which state the GPIF is in when it receives the interrupt Details about more actions can be found in the GPIF II guide Cypress Semiconductor 22

23 GPIF II Designer: API Calls CyU3PGpifLoad Load GPIF II waveform descriptor into FX3 memory CyU3PGpifSMStart Start GPIF II from initial state CyU3PGpifSMSwitch Transitions state machine into a new state without stopping the machine CyU3PGpifSMControl Pause and Resume GPIF II Cypress Semiconductor 23

24 GPIF II Designer: Simulation State Machine Path: The path that is followed through the state machine due to a series of inputs Cypress Semiconductor 24

25 GPIF II Designer: Simulation Define State Machine Path not inputs GPIF II Designer creates input signals based on path Displays output signals Determines Current State Cypress Semiconductor 25

26 Tour of GPIF II Designer Tour completed outside of powerpoint Cypress Semiconductor 26

27 Lab 1 : Objectives Setup IO configuration in GPIF II Designer Layout complex state machine in GPIF II Designer Run timing simulation in GPIF II Designer Build GPIF II Designer project Integrate GPIF II header file into FX3 firmware Image Sensor Module Cypress Semiconductor 27

28 Lab 1: Physical Interface 3 inputs Handled by GPIF II so no firmware intervention necessary on these signals Data bus Goes directly into DMA through the GPIF II Hardware 1 output Handled in firmware not GPIF descriptor I2C control lines Control image sensor configuration Handled in firmware PCLK Frame Valid GPIF II Line Valid USB3 FX3 GPIO Data bus Reset# Image Sensor I2C Master I2C control Cypress Semiconductor 28

29 Lab 1: Timing Diagram Frame valid (FV) high during active frame Line valid (LV) high during active line Pixel Clock (PCLK) always running PCLK can be used as clock source for GPIF II Data only valid when LV and FV are both high Data latched on positive clock edge of PCLK Active Frame FV Vertical Blanking Line 1 Line 2 Line R-1 Line R LV Zoomed in Active Line LV Horizontal Blanking PCLK DATA D0 D1 D2 Dc Cypress Semiconductor 29

30 Lab 1: Design Considerations FX3 Image Sensor Module GPIF II Socket #1 GPIF II Socket #2 USB Socket Buffer Chain UVC Header UVC Payload Cypress Semiconductor 30

31 Lab 1: Interface Definition I2C enabled for communications FX3 is in a slave role Synchronous because we will be using a clock External Clock source since clock is coming from image sensor Data format is little endian out of image sensor 8 bit data bus width from image sensor with no address lines 2 input: FV, LV 1 output: nreset Cypress Semiconductor 31

32 Lab 1: State Machine Cypress Semiconductor 32

33 Collaterals FX3 Data Sheet Application Notes AN EZ-USB FX3 I2C Boot Option AN Booting EZ-USB FX3 over High-Speed USB AN Booting EZ-USB FX3 over Synchronous ADMux Interfaces AN EZ-USB FX3 SPI Boot Option AN EZ-USB FX3 Hardware Design Guidelines and Schematic Checklist AN Designing with the EZ-USB FX3 Slave FIFO Interface AN Slave FIFO Interface for EZ-USB FX3: 5-Bit Address Mode AN Getting Started with FX3 AN USB 3.0 EZ-USB FX3 Orientation AN Migrating from EZ-USB FX2LP Based Design to EZ-USB FX3 Based Design Cypress Semiconductor 33

34 Collaterals Videos Cypress EZ-USB FX3 Technology Overview EZ-USB FX3 Maximum Throughput Demo GPIF II Designer Introduction Software Development Kit FX3 DVK Cypress Semiconductor 34

35 Cypress Semiconductor 35