AMULET3i an Asynchronous System-on-Chip

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Randolf Hardy
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1 3i an Asynchronous System-on-Chip or Adventures in self-timed microprocessors The time is out of joint; O cursed spite William Shakespeare For the times they are a changin Bob Dylan 3i - an Asynchronous System-on-Chip October 18th

2 Why Asynchronous Logic? Low power Do nothing when there is nothing to be done Modularity Added design freedom and component reusability Electromagnetic Interference (EMI) Clocks concentrate noise energy at particular frequencies Security? Surprise the hackers Crazy idea Very few other people are were doing it 3i - an Asynchronous System-on-Chip October 18th

3 How is it done? By handshaking Request Message passing Sender Receiver Acknowledge Rendezvous only when necessary Form into pipelines Stage Stage Stage Non-local action disallowed (mostly) 3i - an Asynchronous System-on-Chip October 18th

4 What s hard about it? Synchronous design allows: Static design of logic Non-local interactions Big choice of design tools Slowing down the clock if timing errors made Asynchronous logic works well only for local interactions Individual blocks of logic are straightforward Timing must be carefully accounted for (self-timing) Simple pipelines are easy Interactions between distant blocks hard (e.g. result forwarding) Many synchronous structures impossible :-) Lack of suitable design/verification tools 3i - an Asynchronous System-on-Chip October 18th

5 1 (1994) What have we done? ARM6 compatible processor (almost) Feasibility study 1.0 µm transistors 3i (2000) 2e (1996) ARM9 compatible processor Memory, DMA controller, bus, 0.35 µm transistors Commercial application ARM7 compatible processor Asynchronous cache 0.5 µm transistors 3i - an Asynchronous System-on-Chip October 18th

6 ARM6 Field strength (dbµv m -1 ) e EMC 10 2e Field strength (dbµv m -1 ) Frequency (MHz) EN standard Enough justification for an 3 product Frequency (MHz) 3i - an Asynchronous System-on-Chip October 18th

7 3i - an Asynchronous System-on-Chip 3 microprocessor (ARMv4T) 3 Test interface controller test 8 Kbytes RAM DMArq 8 Kbyte RAM DMA controller MARBLE 16 Kbyte ROM MARBLE/ Synchronous Bridge delay Memory interface asynchronous synchronous data addr chip selects DRAM control 16 Kbytes ROM Flexible multi-channel DMA controller Programmable external memory interface MARBLE, a fully asynchronous on-chip bus Bridge to on-chip synchronous bus Synchronous peripheral subsystem peripheral I/Os Configuration registers Software debug support Test interface 3i - an Asynchronous System-on-Chip October 18th

8 Prefetch IRQ FIQ 3 Processor Branch prediction branch addresses indirect PC load Instr Memory Thumb Unwanted cycle suppression Automatic halt mode Thumb decoder forwarding Decode & Reg. Rd. store data FIFO Unrestricted register forwarding Execute addr. Data Interface Load/store with out-of-order completion Reorder Buffer Register Write memory skip load data Data Memory Dual ( Harvard ) bus interface Support for precise exceptions 3i - an Asynchronous System-on-Chip October 18th

9 Process-level Parallelism PC Inc Branch add Link Thumb Iteration Control Immediate Decode Decode Arbiter Shift ALU Reorder buffer CAM read CAM write Col/CC Multiply Forward Register read Branch Instruction with options Registers Branch Memory Address out Memory Example: decode & execute stages Various threads many invoked conditionally Skewed pipeline latches (to lower power & EMI) Variable stage delay (e.g. stretching cycle for series shift) Differing pipeline depths (extra buffer for LDM/STM) 3i - an Asynchronous System-on-Chip October 18th

10 Reorder Buffer The reorder buffer is a key feature of 3. Data memory Register read Execute Reorder buffer Register write Forwarding It allows instructions to complete in any order. It resolves register dependencies. It allows register forwarding. It permits low-overhead memory management It supports exact page fault exceptions All of this and asynchronous too! 3i - an Asynchronous System-on-Chip October 18th

11 Reorder Buffer The insight is obvious (with hindsight): Reg. Reg. Reg. Reg. Data can arrive down any path at any time, providing their targets are mutually exclusive Read out waits for each register to be filled in turn, then copies out the result (or not if unwanted) Copy out frees the register but does not delete the data 3i - an Asynchronous System-on-Chip October 18th

12 Memory system 8Kbytes of RAM is accessible via two local buses AmuInstAdr InstBus IAI 3 Core DAI AmuWriteData AmuDataAdr InstDec Logic RIA RRI MID Inst Port MIA DataBus 8Kbyte RAM Data Port RDA RWD DataDec/ Arbiter RRD SDA SWD MRD MDA MWD Initiator Target Initiator A D MARBLE A D A D The RAM is dual-port (at this level) The instruction bus is simpler so it has a higher bandwidth 3i - an Asynchronous System-on-Chip October 18th

13 Memory structure The local RAM is divided into 1Kbyte sub-blocks 1Kbyte RAM 1Kbyte RAM 1Kbyte RAM Arbiter Arbiter Arbiter Ibuffer Dbuffer Ibuffer Dbuffer Ibuffer Dbuffer Local Instruction bus Local Data bus 3 microprocessor Initiator Initiator/Target MARBLE MARBLE Unified RAM model Close to dual-port efficiency Roughly half of instruction fetches are satisfied from the Ibuffers 3i - an Asynchronous System-on-Chip October 18th

14 MARBLE Centrally arbitrated, multi-channel, asynchronous on-chip bus Separate, decoupled transfer phases for address and data Standard master and slave interfaces Supports: 8-, 16- and 32-bit transfers, bus locking, sequential bursts, Synchronous bridge A slave interface for clocked peripherals Performs synchronisation in the usual way (with usual risks) Supports: conventional clocked peripherals. External bus interface Self-timed memory interface (software calibratable delays) Usable as external test interface Supports: 8-, 16- and 32-bit memories, SRAM, DRAM, 3i - an Asynchronous System-on-Chip October 18th

15 DMAC making models with Balsa MARBLE MARBLE domain Target Initiator Data Address Address Data DMA controller Arbitration DMA registers Address Data Channel Requests Transfer engine Transfer engine self timed region async. control request reset DMA SPI (sync control) clocked island Client Requests DMAirq/DMAfiq SOCB clock DMArq[n] About transistors Regular structures (i.e. register banks) in full custom design Control synthesised from Balsa description (first sizable example) Cheats slightly by letting a clock into one corner 3i - an Asynchronous System-on-Chip October 18th

16 3i Vital Statistics Transistor count RAM (total) DMA controller EMI Total (asynchronous subsystem) Geometry 0.35µm, 3 layer metal (using ARM s generic design rules) Area 3i ~25mm 2 3 ~3mm 2 Note: the local RAMs are relatively large in these generic, ASIC rules. 3i - an Asynchronous System-on-Chip October 18th

17 System Performance (Measured) Peak Native MIPS 79 MIPS (96 in Thumb code) 149 kdhrystones 1 /s 85 Dhrystone MIPS (ARM) 108 kdhrystones/s 62 Dhrystone MIPS (Thumb) (-30%) 3i power average 130 mw 60% is within the processor core (simulation result) 660 MIPS/W for the system 1100 MIPS/W for the processor core About 15% slower than expected awaiting silicon process information For comparison: 0.35µm ARM9 120 MHz, (133 Dhrystone MIPS) 800 MIPS/W 1. Dhrystone 2.1 benchmark (normalised to VAX MIPS) 3i - an Asynchronous System-on-Chip October 18th

18 Bus Speeds (Simulated) Local RAM bandwidths Speed depends on bus and whether the level 0 cache hits or not. Instruction bus hit 9.5ns (105Mwords/s) Instruction bus miss 12ns (83Mwords/s) Data bus hit 13ns (77Mwords/s) Data bus miss 16ns (63Mwords/s) In typical code >50% of instruction fetches are hits. MARBLE Total bandwidth 85Mword/s For any one initiator 55Mwords/s Caveat: these are from simulations the absolute numbers may be lower. 3i - an Asynchronous System-on-Chip October 18th

19 Comments 3i is about 2x faster than 2e The speed-up is about 1.4x when normalised for the different processes (0.35µm vs. 0.5µm) This is less than was expected The performance is heavily limited by memory bandwidth There should be another 30% here (CPU >100 MIPS) (The designer moved continents too soon!) The Thumb decompression logic is the limiting factor in Thumb code Speed was not a design priority here Simulated performance not met (not yet known why) MIPS -15% MIPS/W +35% considerably better than ARM9! 3i - an Asynchronous System-on-Chip October 18th

20 DRACO Telecommunications peripherals DMAC EMI ROM CTRL 3 RAM RAM RAM RAM RAM RAM RAM RAM DECT Radio Communications Controller 3i - an Asynchronous System-on-Chip October 18th

21 Conclusions Asynchronous logic: can be competitive with conventional designs has particular advantages with low-power and low EMI think portable systems may be the only solution to some tasks on big chips especially block interconnections but designing big systems is a lot of work it s hard to catch up with the big companies 3i - an Asynchronous System-on-Chip October 18th

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