Computer and Digital System Architecture

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1 Computer and Digital System Architecture EE/CpE-810-A Bruce McNair 1-1/37

2 Week 8 ARM processor cores Furber Ch /37

3 FPGA architecture Interconnects I/O pin Logic blocks Switch block 1-3/37

4 FPGA logic block config config inputs 1 output Lookup Table (LUT) FF 0 1-4/37

5 FPGA LUT config config inputs Lookup Table (LUT) FF 1 0 output Note: Xylinx Virtex-7 FPGAs provide 6-input LUTs with up to ~2M logic cells 2-input LUT example Input Output function A B AND OR XOR NAND NOR A 2-input LUT can implement 16 logical functions /37

6 ASIC/FPGA development Schematic design HDL design Design optimization ASIC standard cell mapping FPGA macrocell mapping Placement Routing Mask generation Programming 1-6/37

7 ASIC/FPGA development Schematic design HDL design Design optimization Design iterations ASIC standard cell mapping FPGA macrocell mapping Placement Routing Mask generation Programming 1-7/37

8 FPGA placement/routing 1-8/37

9 ASIC/FPGA development Schematic design HDL design Design optimization ASIC standard cell mapping Placement FPGA macrocell mapping Soft core Routing Hard core Mask generation Programming 1-9/37

10 Typical ARM core designs ARM core Memory management Cache Signal processing Interface logic 1-10/37

11 ARM cores 1-11/37

12 ARM7TDMI example core ARM7TDMI ARM7 device: 3.3 V logic 32-bit integer core 3 stage pipeline Optional use of Thumb 16-bit compressed instruction set On-chip JTAG Debug support Multiplier with 64-bit result EmbeddedICE support 1-12/37

13 ARM7TDMI example core ARM7TDMI ARM7 device: 3.3 V logic 32-bit integer core 3 stage pipeline EmbeddedICE support Applications: Optional use of Thumb 16-bit compressed instruction set On-chip JTAG Debug support Multiplier with 64-bit result D-Link ADSL Router Apple ipod Lego Mindstors NXT Nokia cellular phones Nintendo DS Gameboy Advance Roomba 500 series Sirius Satellite radio Automotive systems 1-13/37

14 ARM7TDMI organization extern0 extern1 Embedded ICE scan chain 2 scan chain 0 opc, r/w mreq, trans mas[1:0] A[31:0] D[31:0] ARM processor core other signals Din[31:0] Dout[31:0] bus splitter JTAG TAP controller scan chain 1 TCK TMSTRST TDI TDO 1-14/37

15 ARM7TDMI core interface signals clock control configuration interrupts initialization bus control debug coprocessor interface power mclk wait eclk bigend irq ¼q isync reset enin enout enouti abe ale ape dbe tbe busen highz busdis ecapclk dbgrq breakpt dbgack exec extern1 extern0 dbgen rangeout0 rangeout1 dbgrqi commrx commtx opc cpi cpa cpb Vdd Vss ARM7 TDMI ARM7TDMI core core A[31:0] Din[31:0] Dout[31:0] D[31:0] bl[3:0] r/w mas[1:0] mreq seq lock trans mode[4:0] abort Tbit tapsm[3:0] ir[3:0] tdoen tck1 tck2 screg[3:0] drivebs ecapclkbs icapclkbs highz pclkbs rstclkbs sdinbs sdoutbs shclkbs shclk2bs TRST TCK TMS TDI TDO memory interface MMU interface state TAP information boundary scan extension JTAG controls 1-15/37

16 ARM7TDMI core interface signals A[31:0] trans: Translation control for user/ supervisor mode mode: CPSR[4:0] bits (processor mode) ARM7TDMI core Din[31:0] Dout[31:0] D[31:0] bl[3:0] r/w mas[1:0] mreq seq lock Memory interface abort: Disallowed access trans mode[4:0] abort MMU interface Tbit State Tbit: ARM or Thumb instruction set 1-16/37

17 ARM7TDMI memory interface timing mclk A[31:0], r /w, mas, lock, trans, opc Din[31:0] Dout[31:0] enout mreq, seq abort 1-17/37

18 TAP: Additional scan chains can be added to JTAG ARM7TDMI core interface signals tapsm[3:0] ir[3:0] tdoen tck1 tck2 screg[3:0] TAP information Boundary scan extension: Allow for additional JTAG paths ARM7TDMI core drivebs ecapclkbs lcapclkbs highz pclkbs rstclkbs sdinbs sdoutbs shclkbs shclk2bs boundary scan extension TRST TCK TMS TDI TDO JTAG controls 1-18/37

19 ARM7TDMI core interface signals clock control configuration mclk wait eclk bigend Bigend: memory access mode (bigendian or little-endian) interrupts initialization bus control irq fiq isync reset enin enout enouti abe ale ape dbe tbe busen highz busdis ecapclk ARM7TDMI core isync: interrupt latency can be reduced if they are already synchronized externally reset: start execution at enout: ARM performing write cycle ape: control latch to retime addresses if needed by external logic 1-19/37

20 ARM7TDMI core interface signals debug coprocessor interface dbgrq breakpt dbgack exec extern1 extern0 dbgen rangeout0 rangeout1 dbgrqi commrx commtx opc cpl cpa cpb ARM7TDMI core power Vdd Vss power: +5 or +3 volt power supply 1-20/37

21 ARM7TDMI hard core ARM7TDMI standard core characteristics 350 nm CMOS Process 74,209 Transistors 2.1 mm 2 core 87 mw 3.3 V 0-66 MHz clock 60 MIPS 690 MIPS/W ARM7TDMI implementations 250 nm CMOS Process 0.9 V 12,000 MIPS/W ARM7TDMI-S Synthesizable core 1-21/37

22 Improving performance ARM7 core External memory FPGA/ASIC 1-22/37

23 Improving performance ARM7 core External memory FPGA/ASIC ARM7 core Memory cache External memory FPGA/ASIC 1-23/37

24 Time to execute a program T prog N inst CPI f clk N inst = number of instructions CPI = average cycles per instruction f clk = clock speed of processor 1-24/37

25 ARM8 core organization addresses prefetch unit memory (doublebandwidth) read data write data PC instructions integer unit CPinst CPdata To get around memory speed bottleneck, fetch more data/instruction information per access. Assume two sequential memory accesses in 1.5 cycles from on-chip cache memory. coprocessor(s) 1-25/37

26 ARM8 vs ARM7TDMI pipeline comparison ARM7TDMI Fetch Decode Execute Instruction fetch Thumb decompr ARM decode reg read Shift/ALU reg write ARM8 Instruction fetch r.read Shift/ALU decode Data mem access Reg write Fetch Decode Execute Memory Write Prefetch unit Integer unit 1-26/37

27 ARM8 integer unit organization instructions PC+8 coprocessor instructions inst decode decode register read coproc data multiplier ALU/shifter +4 mux write pipeline execute write data address read data memory forwarding paths register write Rot/sgnx write 1-27/37

28 ARM8 core ARM8 core ARM810 On-chip cache ARM8 standard core characteristics 500 nm CMOS Process 124,554 Transistors ~5-6 mm 2 core 0-72 MHz clock MIPS 1-28/37

29 ARM8 core ARM8 standard core characteristics 500 nm CMOS Process 124,554 Transistors ~5-6 mm 2 core 0-72 MHz clock MIPS vs. ARM7TDMI hard core ARM7TDMI standard core characteristics 350 nm CMOS Process 74,209 Transistors 2.1 mm 2 core 87 mw 3.3 V 0-66 MHz clock 60 MIPS 690 MIPS/W 1-29/37

30 ARM9TDMI pipeline FETCH next pc +4 I-cache fetch pc + 4 DECODE pc + 8 r15 I decode register read instruction decode immediate fields EXECUTE B, BL MOV pc SUBS pc +4 LDM/ STM mux postindex pre-index mul ALU shift reg shift forwarding paths execute BUFFER/ DATA load/store address byte repl. D-cache buffer/ data rot/sgn ex WRITE- BACK LDR pc register write write-back 1-30/37

31 ARM9TDMI vs ARM7TDMI pipeline comparison ARM7TDMI Fetch Decode Execute Instruction fetch Thumb decompr ARM decode reg read Shift/ALU reg write ARM9TDMI Instruction fetch r.read Shift/ALU decode Data mem access Reg write Fetch Decode Execute Memory Write 1-31/37

32 ARM9TDMI characteristics 250 nm CMOS Process 2.1 mm 2 core ARM9TDMI core characteristics 110,000 Transistors 150 mw 2.5 V MHz clock 220 MIPS 1500 MIPS/W 1-32/37

33 ARM9TDMI vs. ARM7TDMI Parameter Process Transistors MIPS Core area Power MIPS/W Clock ARM9 250 nm 110, mm V MHz ARM7 350 nm 74, mm V MHz 1-33/37

34 ARM10TDMI core Increased clock speed Clocks/instruction reduced 3-stage 5-stage pipeline ARM7 ARM9 ARM /37

35 ARM10TDMI pipeline branch prediction addr. calc. data memory access data write Instruction fetch decode r.read decode shift/alu multiply Multiplier partials add reg write Fetch Issue Decode Execute Memory Write 1-35/37

36 ARM10TDMI pipeline Additional Issue stage added to decode Multiplier critical path shortened branch prediction addr. calc. data memory access data write Instruction fetch decode r.read decode shift/alu multiply Multiplier partials add reg write Fetch Issue Decode Execute Memory Write Lengthened memory cycle time Lengthened memory cycle time 1-36/37

37 ARM10TDMI reduction in cycles/instruction Double memory fetch allows improved prediction backwards branches assumed true (as in loops) forward branches assumed false Non-blocking load/store: if execution is not dependent on load/store access delay, let it proceed. branch prediction addr. calc. data memory access data write Instruction fetch decode r.read decode shift/alu multiply Multiplier partials add reg write Fetch Issue Decode Execute Memory Write Double-width memory access allows load/store multiple register operations to occur in parallel 1-37/37

October, Saeid Nooshabadi. Overview COMP3221. Memory Interfacing. Microprocessors and Embedded Systems

October, Saeid Nooshabadi. Overview COMP3221. Memory Interfacing. Microprocessors and Embedded Systems Overview COMP 3221 Microprocessors and Embedded Systems Lectures 31: Memory and Bus Organisation - I http://www.cse.unsw.edu.au/~cs3221 October, 2003 Memory Interfacing Memory Type Memory Decoding D- Access