Interfacing. Introduction. Introduction Addressing Interrupt DMA Arbitration Advanced communication architectures. Vahid, Givargis

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1 Interfacing Introduction Addressing Interrupt DMA Arbitration Advanced communication architectures Vahid, Givargis Introduction Embedded system functionality aspects Processing Transformation of data Implemented using processors Storage Retention of data Implemented using memory Communication Transfer of data between processors and memories Implemented using buses Called interfacing Vahid, Givargis - 2 -

2 A simple bus Wires: Uni-directional or bi-directional One line may represent multiple wires Bus Sets of wires with a single function Address bus, data bus, control bus Single set of wires collecting all functions cpu rd'/wr enable addr[0:15] data[0:7] memory Vahid, Givargis Timing Diagrams Common method for describing a protocol Time proceeds to the right on the x axis Control signal: Active high: wr Asserted when 1 Active low: wr Asserted when 0 Data signal: Valid: Data on the bus can be read/written Not valid Data on the bus is meaningless Vahid, Givargis - 4 -

3 Timing Diagrams Protocol: Defines how communication takes place May have subprotocols Bus cycles Each bus cycle may be several clock cycles Vahid, Givargis Timing Diagrams: Read example rd'/wr 1 enable 2 3 addr data T setup T read 4 1 rd' asserted starts read bus cycle 2 address placed on addr address must be stable at least T setup before enable asserted 3 enable asserted Triggers memory to place data on data wires Not later than after the time delay T read 4 data ready on data wires Vahid, Givargis - 6 -

4 Timing Diagrams: Write example rd'/wr enable addr data T setup T write wr asserted starts write bus cycle address placed on addr address must be stable at least T setup before enable asserted data placed on data wires data must be stable at least T setup before enable asserted enable asserted triggers memory save data found on data wires must remain asserted for at least T write Vahid, Givargis Basic protocol concepts Actor Master: initiates the communication Slave: responds to master Direction Sender: Data source Receiver: Data destination Time multiplexing Share a single set of wires for multiple pieces of data Subsequent bytes of a word Data/Address Saves wires at expense of time Vahid, Givargis - 8 -

5 Time multiplexing master req slave master req slave data[0:15] data[0:15] data addr data addr mux d[0:7] demux mux d[0:15] demux req req d data[8:15] data[0:7] addr[0:15] data[0:15] d Vahid, Givargis Strobe protocol master req slave 1 Master asserts req to receive data 2 Slave puts data on bus Within T a d[0:7] Master receives data Master deasserts req req 4 Slave ready for next request data T a Vahid, Givargis

6 Handshake protocol master req slave 1 Master asserts req to receive data ack 2 Slave puts data on bus d[0:7] 3 Slave asserts ack 3 4 Master receives data 4 Master deasserts req req ack 5 Slave deasserts ack Slave ready for next request data Vahid, Givargis Strobe/handshake protocol: Fast master req slave 1 Master asserts req to receive data wait d[0:7] 2 Slave puts data on bus Within T a The wait line is unused 2 3 Master receives data 3 Master deasserts req req 4 Slave ready for next request wait data T a Vahid, Givargis

7 Strobe/handshake protocol: Slow master req slave 1 Master asserts req to receive data wait 2 Slave can't put data on bus within T a Slave asserts wait d[0:7] 3 Slave puts data on bus 4 Slave deasserts wait req Master receives data Master deasserts req wait 6 Slave ready for next request data T a Vahid, Givargis I/O Addressing communicates using some of its pins Port-based I/O or parallel I/O has one or more n-bit ports Software reads and writes a port just like a register Bus-based I/O has address, data and control ports cpu port 0 port 1 port k memory bus Vahid, Givargis

8 I/O Addressing Parallel I/O peripheral (PIO) Processor only supports bus-based I/O But parallel I/O needed Ports are managed by a dedicated peripheral cpu PIO port 0 port 1 memory port k bus Vahid, Givargis I/O Addressing Extended parallel I/O Processor supports port-based I/O But more ports needed One or more PIO extending total number of ports cpu port 0 port 1 port k PIO port k+1 port k+2 port k+m memory bus Vahid, Givargis - -

9 Memory mapped and Standard I/O Processor uses the same bus to talk to Memory Peripherals There are two main ways to communicate Memory-mapped I/O Standard I/O Vahid, Givargis Memory mapped I/O Peripheral registers occupy addresses in same address space as memory E.g. Bus has -bit address Lower 32K map to memory Upper 32k map to peripherals Requires no special instructions Assembly instructions involving memory work with peripherals as well E.g. MOV, LOAD, STORE, ADD, Standard I/O requires special instructions to move data between peripheral registers and memory E.g. IN, OUT Vahid, Givargis

10 Standard I/O No loss of memory addresses to peripherals E.g. Bus has -bit address All 64K map to memory when M/IO set to 0 all 64K map to peripherals when M/IO set to 1 Simpler address decoding logic in peripherals When the number of peripherals much smaller than address space, high-order address bits are ignored Smaller and/or faster comparators Additional pin on bus indicates whether a memory or peripheral access M/IO Vahid, Givargis Interrupts Suppose a peripheral intermittently receives data, which must be serviced by the processor Processor can poll the peripheral regularly To see if data has arrived Wastes a lot of time Peripheral can interrupt the processor when ready Requires one or more extra pin or pins Interrupt pins: 0, 1, If is 1 Processor suspends current program Jumps to an Interrupt Service Routine, or ISR Accomplishes the requested I/O operation Vahid, Givargis

11 Interrupts Different interrupt signals (0, 1, ) have different service routines (ISR0, ISR1, ) What is the address of the correct ISR? Fixed interrupt Address built into microprocessor, cannot be changed Either ISR or jump to actual ISR stored at address Vectored interrupt Peripheral must provide the address Common when microprocessor has multiple peripherals connected by a system bus Compromise: interrupt address table Vahid, Givargis Fixed ISR location [1A] is executing its main program [1B] P1 receives input data in a register with address 0x8000 [2] P1 asserts to request servicing by the microprocessor [3] After completing instruction at 100, sees asserted, saves the PC s value of 100, and sets PC to the ISR fixed location of [4A] The ISR reads data from 0x8000, modifies the data, and writes the resulting data to 0x8001 [4B] After being read, P1 de-asserts [5] The ISR returns, thus restoring PC to 100+1=101, where resumes executing Vahid, Givargis

12 Fixed ISR location : MOV R0, 0x8000 R0= PC=100 LR= [1A] is executing its main program [1B] P1 receives input data in a register with address 0x8000 Vahid, Givargis Fixed ISR location : MOV R0, 0x8000 R0= PC=100 LR= [2] P1 asserts to request servicing by the microprocessor Vahid, Givargis

13 Fixed ISR location : MOV R0, 0x8000 R0= PC=100 [3] After completing instruction at 100, sees asserted, saves the PC s value of 100, and sets PC to the ISR fixed location of Vahid, Givargis Fixed ISR location : MOV R0, 0x8000 R0= PC= [3] After completing instruction at 100, sees asserted, saves the PC s value of 100, and sets PC to the ISR fixed location of Vahid, Givargis

14 Fixed ISR location : MOV R0, 0x8000 R0= PC= [4A] The ISR reads data from 0x8000, modifies the data, and writes the resulting data to 0x800 [4B] After being read, P1 de-asserts Vahid, Givargis Fixed ISR location : MOV R0, 0x8000 R0=13 PC=17 [4A] The ISR reads data from 0x8000, modifies the data, and writes the resulting data to 0x8001 Vahid, Givargis

15 Fixed ISR location : MOV R0, 0x8000 R0=13 PC=18 13 [4A] The ISR reads data from 0x8000, modifies the data, and writes the resulting data to 0x8001 Vahid, Givargis Fixed ISR location : MOV R0, 0x8000 R0=13 PC= [5] The ISR returns, thus restoring PC to 100+1=101, where resumes executing Vahid, Givargis

16 Fixed ISR location : MOV R0, 0x8000 R0=13 PC= [5] The ISR returns, thus restoring PC to 100+1=101, where resumes executing Vahid, Givargis Vectored interrupt [1A] is executing its main program [1B] P1 receives input data in a register with address 0x8000 [2] P1 asserts to request servicing by the microprocessor [3] After completing instruction at 100, sees asserted, saves the PC s value of 100, and asserts A [4] P1 detects A and puts interrupt address vector on the data bus [5A] jumps to the address on the bus (). The ISR reads data from 0x8000, modifies the data, and writes the resulting data to 0x8001 [5B] After being read, P1 de-asserts [6] The ISR returns, thus restoring PC to 100+1=101, deassrts A and resumes executing Vahid, Givargis

17 Vectored interrupt : MOV R0, 0x8000 A R0= PC=100 LR= [1A] is executing its main program [1B] P1 receives input data in a register with address 0x8000 Vahid, Givargis Vectored interrupt : MOV R0, 0x8000 A R0= PC=100 LR= [2] P1 asserts to request servicing by the microprocessor Vahid, Givargis

18 Vectored interrupt : MOV R0, 0x8000 A R0= PC=100 [3] After completing instruction at 100, sees asserted, saves the PC s value of 100, and asserts A Vahid, Givargis Vectored interrupt : MOV R0, 0x8000 A R0= PC=100 [4] P1 detects A and puts interrupt address vector on the data bus Vahid, Givargis

19 Vectored interrupt : MOV R0, 0x8000 A R0= PC= [5A] jumps to the address on the bus (). The ISR reads data from 0x8000, modifies the data, and writes the resulting data to 0x8001 Vahid, Givargis Vectored interrupt : MOV R0, 0x8000 A R0= PC= [5A] jumps to the address on the bus (). The ISR reads data from 0x8000, modifies the data, and writes the resulting data to 0x8001 Vahid, Givargis

20 Vectored interrupt : MOV R0, 0x8000 A R0=13 PC=17 [5A] jumps to the address on the bus (). The ISR reads data from 0x8000, modifies the data, and writes the resulting data to 0x8001 Vahid, Givargis Vectored interrupt : MOV R0, 0x8000 A R0=13 PC=18 13 [5A] jumps to the address on the bus (). The ISR reads data from 0x8000, modifies the data, and writes the resulting data to 0x8001 Vahid, Givargis

21 Vectored interrupt : MOV R0, 0x8000 A R0=13 PC=18 13 [5B] After being read, P1 de-asserts Vahid, Givargis Vectored interrupt : MOV R0, 0x8000 A R0=13 PC= [6] The ISR returns, thus restoring PC to 100+1=101, deassrts A and resumes executing Vahid, Givargis

22 Vectored interrupt : MOV R0, 0x8000 A R0=13 PC= [6] The ISR returns, thus restoring PC to 100+1=101, deassrts A and resumes executing Vahid, Givargis Interrupt address table Compromise between fixed and vectored interrupts One interrupt pin Table in memory holding ISR addresses Maybe 256 words Peripheral doesn t provide ISR address But rather index into table Fewer bits are sent by the peripheral Can move ISR location without changing peripheral Vahid, Givargis

23 Additional interrupt issues Maskable (MI) vs. Non-Maskable (NMI) interrupts Maskable Programmer can set bit that causes processor to ignore interrupt Important when in the middle of time-critical code Non-maskable A separate interrupt pin that can t be masked Typically reserved for drastic situations, like power failure requiring immediate backup of data to nonvolatile memory Vahid, Givargis Additional interrupt issues Jump to ISR Some microprocessors treat jump same as call of any subroutine Complete state saved (PC, registers) May take hundreds of cycles Others only save partial state PC only ISR must not modify registers Or else must save them first Assembly-language programmer must be aware of which registers stored Vahid, Givargis

24 Direct memory access Buffering Temporarily storing data in memory before processing Data accumulated in peripherals commonly buffered Microprocessor could handle this with ISR Storing and restoring microprocessor state inefficient Regular program must wait DMA (Direct Memory Access) controller is more efficient Vahid, Givargis Direct memory access Separate single-purpose processor leaves control of system bus to DMA controller can meanwhile execute its regular program No inefficient storing and restoring state due to interrupt service routine call Regular program need not wait unless it requires the system bus For Harvard archictectures Processor can fetch and execute instructions as long as they don t access data memory If they do, processor stalls Vahid, Givargis

25 Peripheral to memory transfer with vectored interrupt [1A] is executing its main program [1B] P1 receives input data in a register with address 0x8000 [2] P1 asserts to request servicing by the microprocessor [3] After completing instruction at 100, sees asserted, saves the PC s value of 100, and asserts A [4] P1 detects A and puts interrupt address vector on the data bus [5A] jumps to the address on the bus (). The ISR reads data from 0x8000 and writes it to 0x0001 [5B] After being read, P1 de-asserts [6] The ISR returns, thus restoring PC to 100+1=101, deassrts A and resumes executing Vahid, Givargis Peripheral to memory transfer with vectored interrupt : MOV R0, 0x : MOV 0x0001, R0 A R0= PC=100 LR= 0x0000 0x0001 0x7FFF [1A] is executing its main program [1B] P1 receives input data in a register with address 0x8000 Vahid, Givargis

26 Peripheral to memory transfer with vectored interrupt : MOV R0, 0x : MOV 0x0001, R0 A R0= PC=100 LR= 0x0000 0x0001 0x7FFF [2] P1 asserts to request servicing by the microprocessor Vahid, Givargis Peripheral to memory transfer with vectored interrupt : MOV R0, 0x : MOV 0x0001, R0 A R0= PC=100 0x0000 0x0001 0x7FFF [3] After completing instruction at 100, sees asserted, saves the PC s value of 100, and asserts A Vahid, Givargis

27 Peripheral to memory transfer with vectored interrupt : MOV R0, 0x : MOV 0x0001, R0 A R0= PC=100 0x0000 0x0001 0x7FFF [4] P1 detects A and puts interrupt address vector on the data bus Vahid, Givargis Peripheral to memory transfer with vectored interrupt : MOV R0, 0x : MOV 0x0001, R0 A R0= PC= 0x0000 0x0001 0x7FFF [5A] jumps to the address on the bus (). The ISR reads data from 0x8000 and writes it to 0x0001 Vahid, Givargis

28 Peripheral to memory transfer with vectored interrupt : MOV R0, 0x : MOV 0x0001, R0 A R0= PC= 0x0000 0x0001 0x7FFF [5A] jumps to the address on the bus (). The ISR reads data from 0x8000 and writes it to 0x0001 Vahid, Givargis Peripheral to memory transfer with vectored interrupt : MOV R0, 0x : MOV 0x0001, R0 A R0= PC=17 0x0000 0x0001 0x7FFF [5A] jumps to the address on the bus (). The ISR reads data from 0x8000 and writes it to 0x0001 Vahid, Givargis

29 Peripheral to memory transfer with vectored interrupt : MOV R0, 0x : MOV 0x0001, R0 A R0= PC=18 0x0000 0x0001 0x7FFF [5B] After being read, P1 de-asserts Vahid, Givargis Peripheral to memory transfer with vectored interrupt : MOV R0, 0x : MOV 0x0001, R0 A R0= PC=101 0x0000 0x0000 0x7FFF [6] The ISR returns, thus restoring PC to 100+1=101, deassrts A and resumes executing Vahid, Givargis

30 Peripheral to memory transfer with vectored interrupt : MOV R0, 0x : MOV 0x0001, R0 A R0=13 PC=101 0x0000 0x0000 0x7FFF [6] The ISR returns, thus restoring PC to 100+1=101, deassrts A and resumes executing Vahid, Givargis Peripheral to memory transfer with DMA [1A] is executing its main program. It has already configured the DMA ctrl registers [1B] P1 receives input data in a register with address 0x8000. [4] After executing instruction 100, the sees DREQ asserted, releases the system bus, asserts DACK, and resumes execution. stalls only if it needs the system bus to continue executing [3] DMA ctrl asserts DREQ to request control of system bus [5] DMA ctrl asserts ACK, reads data from 0x8000 and writes it to 0x0001 [2] P1 asserts REQ to request servicing by DMA ctrl [7A] deasserts DACK and resumes control of the bus [6] DMA deasserts DREQ and ACK completing handshake with P1 [7B] P1 deasserts REQ Vahid, Givargis

31 Peripheral to memory transfer with DMA # # No ISR needed!! # DACK DREQ R0= PC=100 LR= 0x0000 DMA ctrl 0x0001 0x7FFF P1: 0x8000 0x8000 ACK REQ 0x0001 [1A] is executing its main program. It has already configured the DMA ctrl registers [1B] P1 receives input data in a register with address 0x8000. Vahid, Givargis Peripheral to memory transfer with DMA # # No ISR needed!! # DACK DREQ R0= PC=100 LR= 0x0000 DMA ctrl 0x0001 0x7FFF P1: 0x8000 0x8000 ACK REQ 0x0001 [3] DMA ctrl asserts DREQ to request control of system bus [2] P1 asserts REQ to request servicing by DMA ctrl Vahid, Givargis

32 Peripheral to memory transfer with DMA # # No ISR needed!! # DACK DREQ R0= PC=100 LR= 0x0000 DMA ctrl 0x0001 0x7FFF P1: 0x8000 0x8000 ACK REQ 0x0001 [4] After executing instruction 100, the sees DREQ asserted, releases the system bus, asserts DACK, and resumes execution. stalls only if it needs the system bus to continue executing Vahid, Givargis Peripheral to memory transfer with DMA # # No ISR needed!! # DACK DREQ R0= PC=101 LR= 0x0000 DMA ctrl 0x0001 0x7FFF P1: 0x8000 0x8000 ACK REQ 0x0001 [4] After executing instruction 100, the sees DREQ asserted, releases the system bus, asserts DACK, and resumes execution. stalls only if it needs the system bus to continue executing Vahid, Givargis

33 Peripheral to memory transfer with DMA # # No ISR needed!! # DACK DREQ R0= PC=102 LR= 0x0000 DMA ctrl 0x0001 0x7FFF P1: 0x8000 0x8000 ACK REQ 0x0001 [4] After executing instruction 100, the sees DREQ asserted, releases the system bus, asserts DACK, and resumes execution. stalls only if it needs the system bus to continue executing [5] DMA ctrl asserts ACK, reads data from 0x8000 and writes it to 0x0001 Vahid, Givargis Peripheral to memory transfer with DMA # # No ISR needed!! # DACK DREQ R0= PC=102 LR= 0x0000 DMA ctrl 0x0001 0x7FFF P1: 0x8000 0x8000 ACK REQ 0x0001 [6] DMA deasserts DREQ and ACK completing handshake with P1 Vahid, Givargis

34 Peripheral to memory transfer with DMA # # No ISR needed!! # DACK DREQ R0= PC=102 LR= 0x0000 DMA ctrl 0x0001 0x7FFF P1: 0x8000 0x8000 ACK REQ 0x0001 [7A] deasserts DACK and resumes control of the bus [7B] P1 deasserts REQ Vahid, Givargis Arbitration Multiple peripherals may request services from single resource simultaneously Microprocessor, DMA controller, Who is served first? Need an arbiter mechanism Different approaches Priority arbiter Daisy-chain arbiter Vahid, Givargis

35 Arbitration using a priority arbiter Single-purpose processor Peripherals make requests to arbiter Arbiter makes requests to resource Arbiter is connected to system bus For configuration purposes only A Priority Arbiter IREQ1 IACK1 P1 Pn IREQn IACKn Vahid, Givargis Arbitration using a priority arbiter 7 A program Priority Arbiter 3 IREQ1 IACK1 6 2 P1 2 Pn 8 ISR IREQn IACKn 1. Microprocessor is executing its program 2. Peripheral P1 needs servicing so asserts IREQ1; peripheral Pn also needs servicing so asserts IREQn 3. Priority arbiter sees at least one IREQ input asserted, so asserts 4. Microprocessor stops executing its program and stores its state 5. Microprocessor asserts A 6. Priority arbiter asserts IACK1 to acknowledge peripheral P1 7. Peripheral P1 puts its interrupt address vector on the system bus 8. Microprocessor jumps to the address of ISR read from data bus, ISR executes and returns and completes handshake with arbiter 9. Microprocessor resumes executing its program Vahid, Givargis

36 Arbitration using a priority arbiter Different types of priority Fixed priority Each peripheral has unique rank Highest rank is chosen first with simultaneous request Preferred when there is a clear difference in rank between peripherals Rotating priority (round-robin) Priority is changed based on history of servicing Better distribution of servicing Especially among peripherals with similar priority demands Vahid, Givargis Arbitration using daisy-chain Arbitration done by peripherals Built into peripheral or external logic added REQ input and ACK output added to each peripheral Peripherals connected to each other One peripheral connected to resource All others connected upstream Peripheral s REQ flows downstream to resource Resource s ACK flows upstream to requesting peripheral Closest peripheral has highest priority Vahid, Givargis

37 Arbitration using daisy-chain Advantages Easy to add/remove peripheral No system redesign needed Disadvantages Does not support rotating priority One broken peripheral causes loss of access to others P1 P2 P2 A ACKIN ACKOUT REQOUT REQIN ACKIN ACKOUT REQOUT REQIN ACKIN ACKOUT REQOUT REQIN 0 Vahid, Givargis Network-oriented oriented arbitration When multiple microprocessors share a bus, sometimes called a network Arbitration typically built into bus protocol Separate processors may try to write simultaneously This can cause collisions Data must be resent Don t want to start sending again at same time, so statistical methods are used to reduce chances Typically used for connecting multiple distant chips Trend: use to connect multiple on-chip processors Vahid, Givargis

38 Multilevel bus architectures Don t want one bus for all communication Some peripherals need High-speed bus interface Processor-specific bus interface Too many peripherals slows down bus A solution consists in using a multilevel bus architecture consisting of Processor-local bus Peripheral bus Bridge Vahid, Givargis Multilevel bus architectures Processor-local bus High speed and wide Used for most frequent communication Connects microprocessor, cache, memory controllers Peripheral bus Lower speed, narrower Used for less frequent communication Typically industry standard bus for portability ISA, PCI, SCSI Bridge Converts communication between busses Vahid, Givargis

39 Multilevel bus architectures L2 Cache Main Memory Cache controller Memory controller DMA controller Processor Local Bus P1.1 P1.N Bridge 1 Peripheral Bus 1 P2.1 P2.N Bridge 2 Peripheral Bus 2 Vahid, Givargis

EE414 Embedded Systems. Ch 6. Interfacing. Part 4/4: DMA & Arbitration

EE414 Embedded Systems. Ch 6. Interfacing. Part 4/4: DMA & Arbitration EE414 Embedded Systems Ch 6. Interfacing Part 4/4: DMA & Arbitration Byung Kook Kim School of Electrical Engineering Korea Advanced Institute of Science and Technology Overview Part D. DMA and Arbitration